////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: K.39
//  \   \         Application: netgen
//  /   /         Filename: gentest.v
// /___/   /\     Timestamp: Fri Mar 20 11:31:03 2009
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -ofmt verilog -intstyle silent -w gentest.ngc gentest.v 
// Device	: xcr3384xlTQ144-7
// Input file	: gentest.ngc
// Output file	: gentest.v
// # of Modules	: 1
// Design Name	: gentest
// Xilinx        : C:\Xilinx\10.1\ISE
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module gentest (
  reset_i, clock_i, armed_i, clear_warnings_i, out, incoming_data_i, warnings_i
);
  input reset_i;
  input clock_i;
  input armed_i;
  input clear_warnings_i;
  output [7 : 0] out;
  input [7 : 0] incoming_data_i;
  input [7 : 0] warnings_i;
  wire armed_i_IBUF_1;
  wire clear_warnings_i_IBUF_3;
  wire clock_i_IBUF_5;
  wire incoming_data_i_0_IBUF_14;
  wire incoming_data_i_1_IBUF_15;
  wire incoming_data_i_2_IBUF_16;
  wire incoming_data_i_3_IBUF_17;
  wire incoming_data_i_4_IBUF_18;
  wire incoming_data_i_5_IBUF_19;
  wire incoming_data_i_6_IBUF_20;
  wire incoming_data_i_7_IBUF_21;
  wire reset_i_IBUF_31;
  wire warning_register_0_N0;
  wire warning_register_0_mux0000;
  wire warning_register_0_mux00001;
  wire warning_register_0_mux000011_36;
  wire warning_register_0_not0001;
  wire warning_register_0_not00011;
  wire warning_register_0_not000111_39;
  wire warning_register_0_not000112_40;
  wire warning_register_0_not000113_41;
  wire warning_register_0_not000114_42;
  wire warning_register_0_not000115_43;
  wire warning_register_1_mux0000;
  wire warning_register_1_mux00001;
  wire warning_register_1_mux000011_47;
  wire warning_register_1_not0001;
  wire warning_register_1_not00011;
  wire warning_register_1_not000111_50;
  wire warning_register_1_not000112_51;
  wire warning_register_1_not000113_52;
  wire warning_register_1_not000114_53;
  wire warning_register_1_not000115_54;
  wire warning_register_2_mux0000;
  wire warning_register_2_mux00001;
  wire warning_register_2_mux000011_58;
  wire warning_register_2_not0001;
  wire warning_register_2_not00011;
  wire warning_register_2_not000111_61;
  wire warning_register_2_not000112_62;
  wire warning_register_2_not000113_63;
  wire warning_register_2_not000114_64;
  wire warning_register_2_not000115_65;
  wire warning_register_3_mux0000;
  wire warning_register_3_mux00001;
  wire warning_register_3_mux000011_69;
  wire warning_register_3_not0001;
  wire warning_register_3_not00011;
  wire warning_register_3_not000111_72;
  wire warning_register_3_not000112_73;
  wire warning_register_3_not000113_74;
  wire warning_register_3_not000114_75;
  wire warning_register_3_not000115_76;
  wire warning_register_4_mux0000;
  wire warning_register_4_mux00001;
  wire warning_register_4_mux000011_80;
  wire warning_register_4_not0001;
  wire warning_register_4_not00011;
  wire warning_register_4_not000111_83;
  wire warning_register_4_not000112_84;
  wire warning_register_4_not000113_85;
  wire warning_register_4_not000114_86;
  wire warning_register_4_not000115_87;
  wire warning_register_5_mux0000;
  wire warning_register_5_mux00001;
  wire warning_register_5_mux000011_91;
  wire warning_register_5_not0001;
  wire warning_register_5_not00011;
  wire warning_register_5_not000111_94;
  wire warning_register_5_not000112_95;
  wire warning_register_5_not000113_96;
  wire warning_register_5_not000114_97;
  wire warning_register_5_not000115_98;
  wire warning_register_6_mux0000;
  wire warning_register_6_mux00001;
  wire warning_register_6_mux000011_102;
  wire warning_register_6_not0001;
  wire warning_register_6_not00011;
  wire warning_register_6_not000111_105;
  wire warning_register_6_not000112_106;
  wire warning_register_6_not000113_107;
  wire warning_register_6_not000114_108;
  wire warning_register_6_not000115_109;
  wire warning_register_7_mux0000;
  wire warning_register_7_mux00001;
  wire warning_register_7_mux000011_113;
  wire warning_register_7_not0001;
  wire warning_register_7_not00011;
  wire warning_register_7_not000111_116;
  wire warning_register_7_not000112_117;
  wire warning_register_7_not000113_118;
  wire warning_register_7_not000114_119;
  wire warning_register_7_not000115_120;
  wire warnings_i_0_IBUF_129;
  wire warnings_i_1_IBUF_130;
  wire warnings_i_2_IBUF_131;
  wire warnings_i_3_IBUF_132;
  wire warnings_i_4_IBUF_133;
  wire warnings_i_5_IBUF_134;
  wire warnings_i_6_IBUF_135;
  wire warnings_i_7_IBUF_136;
  wire [7 : 0] warning_register;
  FDCE   warning_register_7 (
    .CE(warning_register_7_not0001),
    .CLR(reset_i_IBUF_31),
    .C(warning_register_0_N0),
    .D(warning_register_7_mux0000),
    .Q(warning_register[7])
  );
  FDCE   warning_register_6 (
    .CE(warning_register_6_not0001),
    .CLR(reset_i_IBUF_31),
    .C(warning_register_0_N0),
    .D(warning_register_6_mux0000),
    .Q(warning_register[6])
  );
  FDCE   warning_register_5 (
    .CE(warning_register_5_not0001),
    .CLR(reset_i_IBUF_31),
    .C(warning_register_0_N0),
    .D(warning_register_5_mux0000),
    .Q(warning_register[5])
  );
  FDCE   warning_register_4 (
    .CE(warning_register_4_not0001),
    .CLR(reset_i_IBUF_31),
    .C(warning_register_0_N0),
    .D(warning_register_4_mux0000),
    .Q(warning_register[4])
  );
  FDCE   warning_register_3 (
    .CE(warning_register_3_not0001),
    .CLR(reset_i_IBUF_31),
    .C(warning_register_0_N0),
    .D(warning_register_3_mux0000),
    .Q(warning_register[3])
  );
  FDCE   warning_register_2 (
    .CE(warning_register_2_not0001),
    .CLR(reset_i_IBUF_31),
    .C(warning_register_0_N0),
    .D(warning_register_2_mux0000),
    .Q(warning_register[2])
  );
  FDCE   warning_register_1 (
    .CE(warning_register_1_not0001),
    .CLR(reset_i_IBUF_31),
    .C(warning_register_0_N0),
    .D(warning_register_1_mux0000),
    .Q(warning_register[1])
  );
  FDCE   warning_register_0 (
    .CE(warning_register_0_not0001),
    .CLR(reset_i_IBUF_31),
    .C(warning_register_0_N0),
    .D(warning_register_0_mux0000),
    .Q(warning_register[0])
  );
  INV   warning_register_0_N01 (
    .I(clock_i_IBUF_5),
    .O(warning_register_0_N0)
  );
  AND2   warning_register_0_not000111 (
    .I0(warnings_i_0_IBUF_129),
    .I1(armed_i_IBUF_1),
    .O(warning_register_0_not00011)
  );
  AND2   warning_register_0_not000112 (
    .I0(warnings_i_0_IBUF_129),
    .I1(armed_i_IBUF_1),
    .O(warning_register_0_not000111_39)
  );
  INV   warning_register_0_not000113 (
    .I(incoming_data_i_0_IBUF_14),
    .O(warning_register_0_not000112_40)
  );
  OR2   warning_register_0_not000114 (
    .I0(clear_warnings_i_IBUF_3),
    .I1(warning_register_0_not00011),
    .O(warning_register_0_not000113_41)
  );
  AND2   warning_register_0_not000115 (
    .I0(warning_register_0_not000111_39),
    .I1(warning_register_0_not000112_40),
    .O(warning_register_0_not000114_42)
  );
  AND2   warning_register_0_not000116 (
    .I0(incoming_data_i_0_IBUF_14),
    .I1(warning_register_0_not000113_41),
    .O(warning_register_0_not000115_43)
  );
  OR2   warning_register_0_not000117 (
    .I0(warning_register_0_not000115_43),
    .I1(warning_register_0_not000114_42),
    .O(warning_register_0_not0001)
  );
  INV   warning_register_0_mux000011 (
    .I(incoming_data_i_0_IBUF_14),
    .O(warning_register_0_mux00001)
  );
  INV   warning_register_0_mux000012 (
    .I(clear_warnings_i_IBUF_3),
    .O(warning_register_0_mux000011_36)
  );
  OR2   warning_register_0_mux000013 (
    .I0(warning_register_0_mux00001),
    .I1(warning_register_0_mux000011_36),
    .O(warning_register_0_mux0000)
  );
  AND2   warning_register_1_not000111 (
    .I0(warnings_i_1_IBUF_130),
    .I1(armed_i_IBUF_1),
    .O(warning_register_1_not00011)
  );
  AND2   warning_register_1_not000112 (
    .I0(warnings_i_1_IBUF_130),
    .I1(armed_i_IBUF_1),
    .O(warning_register_1_not000111_50)
  );
  INV   warning_register_1_not000113 (
    .I(incoming_data_i_1_IBUF_15),
    .O(warning_register_1_not000112_51)
  );
  OR2   warning_register_1_not000114 (
    .I0(clear_warnings_i_IBUF_3),
    .I1(warning_register_1_not00011),
    .O(warning_register_1_not000113_52)
  );
  AND2   warning_register_1_not000115 (
    .I0(warning_register_1_not000111_50),
    .I1(warning_register_1_not000112_51),
    .O(warning_register_1_not000114_53)
  );
  AND2   warning_register_1_not000116 (
    .I0(incoming_data_i_1_IBUF_15),
    .I1(warning_register_1_not000113_52),
    .O(warning_register_1_not000115_54)
  );
  OR2   warning_register_1_not000117 (
    .I0(warning_register_1_not000115_54),
    .I1(warning_register_1_not000114_53),
    .O(warning_register_1_not0001)
  );
  INV   warning_register_1_mux000011 (
    .I(incoming_data_i_1_IBUF_15),
    .O(warning_register_1_mux00001)
  );
  INV   warning_register_1_mux000012 (
    .I(clear_warnings_i_IBUF_3),
    .O(warning_register_1_mux000011_47)
  );
  OR2   warning_register_1_mux000013 (
    .I0(warning_register_1_mux00001),
    .I1(warning_register_1_mux000011_47),
    .O(warning_register_1_mux0000)
  );
  AND2   warning_register_2_not000111 (
    .I0(warnings_i_2_IBUF_131),
    .I1(armed_i_IBUF_1),
    .O(warning_register_2_not00011)
  );
  AND2   warning_register_2_not000112 (
    .I0(warnings_i_2_IBUF_131),
    .I1(armed_i_IBUF_1),
    .O(warning_register_2_not000111_61)
  );
  INV   warning_register_2_not000113 (
    .I(incoming_data_i_2_IBUF_16),
    .O(warning_register_2_not000112_62)
  );
  OR2   warning_register_2_not000114 (
    .I0(clear_warnings_i_IBUF_3),
    .I1(warning_register_2_not00011),
    .O(warning_register_2_not000113_63)
  );
  AND2   warning_register_2_not000115 (
    .I0(warning_register_2_not000111_61),
    .I1(warning_register_2_not000112_62),
    .O(warning_register_2_not000114_64)
  );
  AND2   warning_register_2_not000116 (
    .I0(incoming_data_i_2_IBUF_16),
    .I1(warning_register_2_not000113_63),
    .O(warning_register_2_not000115_65)
  );
  OR2   warning_register_2_not000117 (
    .I0(warning_register_2_not000115_65),
    .I1(warning_register_2_not000114_64),
    .O(warning_register_2_not0001)
  );
  INV   warning_register_2_mux000011 (
    .I(incoming_data_i_2_IBUF_16),
    .O(warning_register_2_mux00001)
  );
  INV   warning_register_2_mux000012 (
    .I(clear_warnings_i_IBUF_3),
    .O(warning_register_2_mux000011_58)
  );
  OR2   warning_register_2_mux000013 (
    .I0(warning_register_2_mux00001),
    .I1(warning_register_2_mux000011_58),
    .O(warning_register_2_mux0000)
  );
  AND2   warning_register_3_not000111 (
    .I0(warnings_i_3_IBUF_132),
    .I1(armed_i_IBUF_1),
    .O(warning_register_3_not00011)
  );
  AND2   warning_register_3_not000112 (
    .I0(warnings_i_3_IBUF_132),
    .I1(armed_i_IBUF_1),
    .O(warning_register_3_not000111_72)
  );
  INV   warning_register_3_not000113 (
    .I(incoming_data_i_3_IBUF_17),
    .O(warning_register_3_not000112_73)
  );
  OR2   warning_register_3_not000114 (
    .I0(clear_warnings_i_IBUF_3),
    .I1(warning_register_3_not00011),
    .O(warning_register_3_not000113_74)
  );
  AND2   warning_register_3_not000115 (
    .I0(warning_register_3_not000111_72),
    .I1(warning_register_3_not000112_73),
    .O(warning_register_3_not000114_75)
  );
  AND2   warning_register_3_not000116 (
    .I0(incoming_data_i_3_IBUF_17),
    .I1(warning_register_3_not000113_74),
    .O(warning_register_3_not000115_76)
  );
  OR2   warning_register_3_not000117 (
    .I0(warning_register_3_not000115_76),
    .I1(warning_register_3_not000114_75),
    .O(warning_register_3_not0001)
  );
  INV   warning_register_3_mux000011 (
    .I(incoming_data_i_3_IBUF_17),
    .O(warning_register_3_mux00001)
  );
  INV   warning_register_3_mux000012 (
    .I(clear_warnings_i_IBUF_3),
    .O(warning_register_3_mux000011_69)
  );
  OR2   warning_register_3_mux000013 (
    .I0(warning_register_3_mux00001),
    .I1(warning_register_3_mux000011_69),
    .O(warning_register_3_mux0000)
  );
  AND2   warning_register_4_not000111 (
    .I0(warnings_i_4_IBUF_133),
    .I1(armed_i_IBUF_1),
    .O(warning_register_4_not00011)
  );
  AND2   warning_register_4_not000112 (
    .I0(warnings_i_4_IBUF_133),
    .I1(armed_i_IBUF_1),
    .O(warning_register_4_not000111_83)
  );
  INV   warning_register_4_not000113 (
    .I(incoming_data_i_4_IBUF_18),
    .O(warning_register_4_not000112_84)
  );
  OR2   warning_register_4_not000114 (
    .I0(clear_warnings_i_IBUF_3),
    .I1(warning_register_4_not00011),
    .O(warning_register_4_not000113_85)
  );
  AND2   warning_register_4_not000115 (
    .I0(warning_register_4_not000111_83),
    .I1(warning_register_4_not000112_84),
    .O(warning_register_4_not000114_86)
  );
  AND2   warning_register_4_not000116 (
    .I0(incoming_data_i_4_IBUF_18),
    .I1(warning_register_4_not000113_85),
    .O(warning_register_4_not000115_87)
  );
  OR2   warning_register_4_not000117 (
    .I0(warning_register_4_not000115_87),
    .I1(warning_register_4_not000114_86),
    .O(warning_register_4_not0001)
  );
  INV   warning_register_4_mux000011 (
    .I(incoming_data_i_4_IBUF_18),
    .O(warning_register_4_mux00001)
  );
  INV   warning_register_4_mux000012 (
    .I(clear_warnings_i_IBUF_3),
    .O(warning_register_4_mux000011_80)
  );
  OR2   warning_register_4_mux000013 (
    .I0(warning_register_4_mux00001),
    .I1(warning_register_4_mux000011_80),
    .O(warning_register_4_mux0000)
  );
  AND2   warning_register_5_not000111 (
    .I0(warnings_i_5_IBUF_134),
    .I1(armed_i_IBUF_1),
    .O(warning_register_5_not00011)
  );
  AND2   warning_register_5_not000112 (
    .I0(warnings_i_5_IBUF_134),
    .I1(armed_i_IBUF_1),
    .O(warning_register_5_not000111_94)
  );
  INV   warning_register_5_not000113 (
    .I(incoming_data_i_5_IBUF_19),
    .O(warning_register_5_not000112_95)
  );
  OR2   warning_register_5_not000114 (
    .I0(clear_warnings_i_IBUF_3),
    .I1(warning_register_5_not00011),
    .O(warning_register_5_not000113_96)
  );
  AND2   warning_register_5_not000115 (
    .I0(warning_register_5_not000111_94),
    .I1(warning_register_5_not000112_95),
    .O(warning_register_5_not000114_97)
  );
  AND2   warning_register_5_not000116 (
    .I0(incoming_data_i_5_IBUF_19),
    .I1(warning_register_5_not000113_96),
    .O(warning_register_5_not000115_98)
  );
  OR2   warning_register_5_not000117 (
    .I0(warning_register_5_not000115_98),
    .I1(warning_register_5_not000114_97),
    .O(warning_register_5_not0001)
  );
  INV   warning_register_5_mux000011 (
    .I(incoming_data_i_5_IBUF_19),
    .O(warning_register_5_mux00001)
  );
  INV   warning_register_5_mux000012 (
    .I(clear_warnings_i_IBUF_3),
    .O(warning_register_5_mux000011_91)
  );
  OR2   warning_register_5_mux000013 (
    .I0(warning_register_5_mux00001),
    .I1(warning_register_5_mux000011_91),
    .O(warning_register_5_mux0000)
  );
  AND2   warning_register_6_not000111 (
    .I0(warnings_i_6_IBUF_135),
    .I1(armed_i_IBUF_1),
    .O(warning_register_6_not00011)
  );
  AND2   warning_register_6_not000112 (
    .I0(warnings_i_6_IBUF_135),
    .I1(armed_i_IBUF_1),
    .O(warning_register_6_not000111_105)
  );
  INV   warning_register_6_not000113 (
    .I(incoming_data_i_6_IBUF_20),
    .O(warning_register_6_not000112_106)
  );
  OR2   warning_register_6_not000114 (
    .I0(clear_warnings_i_IBUF_3),
    .I1(warning_register_6_not00011),
    .O(warning_register_6_not000113_107)
  );
  AND2   warning_register_6_not000115 (
    .I0(warning_register_6_not000111_105),
    .I1(warning_register_6_not000112_106),
    .O(warning_register_6_not000114_108)
  );
  AND2   warning_register_6_not000116 (
    .I0(incoming_data_i_6_IBUF_20),
    .I1(warning_register_6_not000113_107),
    .O(warning_register_6_not000115_109)
  );
  OR2   warning_register_6_not000117 (
    .I0(warning_register_6_not000115_109),
    .I1(warning_register_6_not000114_108),
    .O(warning_register_6_not0001)
  );
  INV   warning_register_6_mux000011 (
    .I(incoming_data_i_6_IBUF_20),
    .O(warning_register_6_mux00001)
  );
  INV   warning_register_6_mux000012 (
    .I(clear_warnings_i_IBUF_3),
    .O(warning_register_6_mux000011_102)
  );
  OR2   warning_register_6_mux000013 (
    .I0(warning_register_6_mux00001),
    .I1(warning_register_6_mux000011_102),
    .O(warning_register_6_mux0000)
  );
  AND2   warning_register_7_not000111 (
    .I0(warnings_i_7_IBUF_136),
    .I1(armed_i_IBUF_1),
    .O(warning_register_7_not00011)
  );
  AND2   warning_register_7_not000112 (
    .I0(warnings_i_7_IBUF_136),
    .I1(armed_i_IBUF_1),
    .O(warning_register_7_not000111_116)
  );
  INV   warning_register_7_not000113 (
    .I(incoming_data_i_7_IBUF_21),
    .O(warning_register_7_not000112_117)
  );
  OR2   warning_register_7_not000114 (
    .I0(clear_warnings_i_IBUF_3),
    .I1(warning_register_7_not00011),
    .O(warning_register_7_not000113_118)
  );
  AND2   warning_register_7_not000115 (
    .I0(warning_register_7_not000111_116),
    .I1(warning_register_7_not000112_117),
    .O(warning_register_7_not000114_119)
  );
  AND2   warning_register_7_not000116 (
    .I0(incoming_data_i_7_IBUF_21),
    .I1(warning_register_7_not000113_118),
    .O(warning_register_7_not000115_120)
  );
  OR2   warning_register_7_not000117 (
    .I0(warning_register_7_not000115_120),
    .I1(warning_register_7_not000114_119),
    .O(warning_register_7_not0001)
  );
  INV   warning_register_7_mux000011 (
    .I(incoming_data_i_7_IBUF_21),
    .O(warning_register_7_mux00001)
  );
  INV   warning_register_7_mux000012 (
    .I(clear_warnings_i_IBUF_3),
    .O(warning_register_7_mux000011_113)
  );
  OR2   warning_register_7_mux000013 (
    .I0(warning_register_7_mux00001),
    .I1(warning_register_7_mux000011_113),
    .O(warning_register_7_mux0000)
  );
  IBUF   reset_i_IBUF (
    .I(reset_i),
    .O(reset_i_IBUF_31)
  );
  IBUF   clock_i_IBUF (
    .I(clock_i),
    .O(clock_i_IBUF_5)
  );
  IBUF   armed_i_IBUF (
    .I(armed_i),
    .O(armed_i_IBUF_1)
  );
  IBUF   clear_warnings_i_IBUF (
    .I(clear_warnings_i),
    .O(clear_warnings_i_IBUF_3)
  );
  IBUF   incoming_data_i_7_IBUF (
    .I(incoming_data_i[7]),
    .O(incoming_data_i_7_IBUF_21)
  );
  IBUF   incoming_data_i_6_IBUF (
    .I(incoming_data_i[6]),
    .O(incoming_data_i_6_IBUF_20)
  );
  IBUF   incoming_data_i_5_IBUF (
    .I(incoming_data_i[5]),
    .O(incoming_data_i_5_IBUF_19)
  );
  IBUF   incoming_data_i_4_IBUF (
    .I(incoming_data_i[4]),
    .O(incoming_data_i_4_IBUF_18)
  );
  IBUF   incoming_data_i_3_IBUF (
    .I(incoming_data_i[3]),
    .O(incoming_data_i_3_IBUF_17)
  );
  IBUF   incoming_data_i_2_IBUF (
    .I(incoming_data_i[2]),
    .O(incoming_data_i_2_IBUF_16)
  );
  IBUF   incoming_data_i_1_IBUF (
    .I(incoming_data_i[1]),
    .O(incoming_data_i_1_IBUF_15)
  );
  IBUF   incoming_data_i_0_IBUF (
    .I(incoming_data_i[0]),
    .O(incoming_data_i_0_IBUF_14)
  );
  IBUF   warnings_i_7_IBUF (
    .I(warnings_i[7]),
    .O(warnings_i_7_IBUF_136)
  );
  IBUF   warnings_i_6_IBUF (
    .I(warnings_i[6]),
    .O(warnings_i_6_IBUF_135)
  );
  IBUF   warnings_i_5_IBUF (
    .I(warnings_i[5]),
    .O(warnings_i_5_IBUF_134)
  );
  IBUF   warnings_i_4_IBUF (
    .I(warnings_i[4]),
    .O(warnings_i_4_IBUF_133)
  );
  IBUF   warnings_i_3_IBUF (
    .I(warnings_i[3]),
    .O(warnings_i_3_IBUF_132)
  );
  IBUF   warnings_i_2_IBUF (
    .I(warnings_i[2]),
    .O(warnings_i_2_IBUF_131)
  );
  IBUF   warnings_i_1_IBUF (
    .I(warnings_i[1]),
    .O(warnings_i_1_IBUF_130)
  );
  IBUF   warnings_i_0_IBUF (
    .I(warnings_i[0]),
    .O(warnings_i_0_IBUF_129)
  );
  OBUF   out_7_OBUF (
    .I(warning_register[7]),
    .O(out[7])
  );
  OBUF   out_6_OBUF (
    .I(warning_register[6]),
    .O(out[6])
  );
  OBUF   out_5_OBUF (
    .I(warning_register[5]),
    .O(out[5])
  );
  OBUF   out_4_OBUF (
    .I(warning_register[4]),
    .O(out[4])
  );
  OBUF   out_3_OBUF (
    .I(warning_register[3]),
    .O(out[3])
  );
  OBUF   out_2_OBUF (
    .I(warning_register[2]),
    .O(out[2])
  );
  OBUF   out_1_OBUF (
    .I(warning_register[1]),
    .O(out[1])
  );
  OBUF   out_0_OBUF (
    .I(warning_register[0]),
    .O(out[0])
  );
endmodule


`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule