Synthesis Log
Created on 11:31:04 AM 3/20/2009
Running XST Synthesis...
Please wait...
Release 10.1.03 - xst K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to C:/dwarf_fpgas/gen_test/synthesis/xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "gentest.prj"
Input Format : mixed
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : "gentest"
Output Format : NGC
Target Device : xcr3384xlTQ144-7
---- Source Options
Top Module Name : gentest
Generics, Parameters : { }
Verilog Macros : { }
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Mux Extraction : yes
CASE Implementation Style : full-parallel
Safe Implementation : no
Resource Sharing : yes
---- Target Options
Add IO Buffers : yes
Equivalent register Removal : yes
MACRO Preserve : yes
XOR Preserve : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Verilog 2001 : yes
Keep Hierarchy : yes
Netlist Hierarchy : as_optimized
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
Clock Enable : yes
wysiwyg : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "..\src\gen_test.v" in library gen_test
Module <gentest> compiled
No errors in compilation
Analysis of file <"gentest.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <gentest> in library <gen_test> with parameters.
SIZE = "00000000000000000000000000001000"
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <gentest>.
SIZE = 32'sb00000000000000000000000000001000
Module <gentest> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <gentest>.
Related source file is "..\src\gen_test.v".
Found 8-bit register for signal <warning_register>.
Summary:
inferred 8 D-type flip-flop(s).
Unit <gentest> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers : 8
1-bit register : 8
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers : 8
Flip-Flops : 8
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <gentest> ...
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
Top Level Output File Name : gentest
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : yes
Target Technology : xcr3384xlTQ144-7
Macro Preserve : yes
XOR Preserve : yes
Clock Enable : yes
wysiwyg : no
Design Statistics
# IOs : 28
Cell Usage :
# BELS : 81
# AND2 : 32
# INV : 25
# OR2 : 24
# FlipFlops/Latches : 8
# FDCE : 8
# IO Buffers : 28
# IBUF : 20
# OBUF : 8
=========================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.47 secs
-->
Total memory usage is 110264 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
simulation primitives and has to be used with UNISIM simulation library for
correct compilation and simulation.
INFO:NetListWriters - Setup Simulation - To perform a setup simulation, specify
values in the Maximum (MAX) field with the following command line modifier:
-SDFMAX
INFO:NetListWriters - Hold Simulation - To perform the most accurate hold
simulation, specify values in the Minimum (MIN) field with the following
command line modifier: -SDFMIN
INFO:NetListWriters:665 - For more information on how to pass the SDF switches
to the simulator, see your Simulator tool documentation.
Synthesis finished successfully.