(ExpressProject "NodeTimeDistribution"
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  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\nodetimedistribution.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (DRC_Scope "0")
    (DRC_Action "0")
    (DRC_Create_Warnings "FALSE")
    (DRC_View_Output "FALSE")
    (DRC_Preserved_Waived "FALSE")
    (DRC_Run_Electrical_Rules "TRUE")
    (DRC_Run_Physical_Rules "FALSE")
    (DRC_Report_File
       "M:\NODETIMEDISTRIBUTION\NTD_SCH_PCB\ALLEGRO\NODETIMEDISTRIBUTION.DRC")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Report_Netnames "FALSE")
    (DRC_Check_Single_Node_Nets "TRUE")
    (DRC_Run_Electrical_Custom_DRC "FALSE")
    (DRC_Check_No_Driving_Source "TRUE")
    (DRC_Check_Duplicate_NetNames "TRUE")
    (DRC_Check_Floating_Pins "TRUE")
    (DRC_Check_Physical_Power_Pins_Visibility "TRUE")
    (DRC_Check_PCB_Footprint_Property "TRUE")
    (DRC_Check_Normal_Convert_View_Sync "TRUE")
    (DRC_Check_Incorrect_PinGroup_Assignment "TRUE")
    (DRC_Check_High_Speed_Props_Syntax "TRUE")
    (DRC_Check_Missing_Pin_Numbers "TRUE")
    (DRC_Check_Device_With_No_Pins "TRUE")
    (DRC_Check_Power_Ground_Short "TRUE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Visible_Power_pins "FALSE")
    (DRC_Report_Unused_Part_Packages "TRUE")
    (DRC_Check_Name_Prop_For_HierBlocks "TRUE")
    (DRC_Run_Physical_Custom_DRC "FALSE")
    (Netlist_TAB "0")
    (OTHER_Part_Value "{Value}")
    (OTHER_Netlist_File "NODETIMEDISTRIBUTION.NET")
    (OTHER_Netlist_File2 "NODETIMEDISTRIBUTION.CMP")
    (OTHER_View_Output "TRUE")
    (OTHER_View_Output2 "FALSE")
    (OTHER_Formatter "orWirelist64.dll")
    (OTHER_PCB_Footprint "{PCB Footprint}")
    (OTHER_Switch0 "FALSE")
    (OTHER_Switch1 "TRUE")
    (OTHER_Switch2 "FALSE")
    (OTHER_Switch3 "FALSE")
    (OTHER_Switch4 "FALSE")
    (OTHER_Switch5 "FALSE")
    (OTHER_Switch6 "FALSE")
    ("Create Allegro Netlist" "TRUE")
    ("Allegro Netlist Directory" ".")
    ("View Allegro Netlist Files" "FALSE")
    ("Allegro Netlist Create DCF File" "FALSE")
    ("Update Allegro Board" "FALSE")
    ("Allegro Netlist Output Board File" "allegro\NODETIMEDISTRIBUTION.brd")
    ("Allegro Netlist Remove Etch" "FALSE")
    ("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
    ("Allegro Netlist Open Board in Allegro" "ALLEGRO")
    ("Allegro Setup Backup Versions" "3")
    ("Allegro Setup Ignore Constraints" "FALSE")
    ("Allegro Setup Part Type Length" "31")
    ("Allegro Netlist Combine Property String" "PCB Footprint")
    ("Allegro Netlist Ignore Fixed Property" "FALSE")
    ("Allegro Netlist User Defined Property" "FALSE")
    (Backannotation_TAB "0")
    ("Allegro Backannotation Run Genfeed" "TRUE")
    ("Allegro Backannotation Board File"
       "M:\NodeTimeDistribution\NTD_SCH_PCB\allegro\NODETIMEDISTRIBUTION.brd")
    ("Allegro Backannotation Netlist Directory"
       "M:\NodeTimeDistribution\NTD_SCH_PCB\allegro")
    ("Allegro Backannotation Output File" "allegro\NODETIMEDISTRIBUTION.swp")
    ("Allegro Backannotation Update Schematic" "TRUE")
    ("Allegro Backannotation View Output" "FALSE")
    ("Allegro Setup Output Warnings" "FALSE"))
  (Folder "Outputs"
    (File ".\nodetimedistribution.drc"
      (Type "Report"))
    (File ".\nodetimedistribution.net"
      (Type "Report"))
    (File ".\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat"))
    (File ".\pinview.dat"
      (Type "Report")
      (DisplayName "pinView.dat"))
    (File ".\netview.dat"
      (Type "Report")
      (DisplayName "netView.dat"))
    (File ".\funcview.dat"
      (Type "Report")
      (DisplayName "funcView.dat"))
    (File ".\compview.dat"
      (Type "Report")
      (DisplayName "compView.dat"))
    (File ".\allegro\nodetimedistribution.swp"
      (Type "Report")
      (DisplayName "NODETIMEDISTRIBUTION.swp")))
  (Folder "Referenced Projects")
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    (OFFPAGELEFT-L
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    (MAX6814
      (FullPartName "MAX6814.Normal")
      (LibraryName "C:\CADENCE\SPB_17.2\TOOLS\CAPTURE\LIBRARY\DRT3.OLB")
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    (C
      (FullPartName "C.Normal")
      (LibraryName "C:\CADENCE\SPB_17.2\TOOLS\CAPTURE\LIBRARY\DISCRETE.OLB")
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    ("CAP NP"
      (FullPartName "CAP NP.Normal")
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  (MPSSessionName "drthom")
  (LastUsedLibraryBrowseDirectory "C:\Cadence\SPB_17.2\tools\capture\library")
  (GlobalState
    (FileView
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      (Path "Design Resources" ".\nodetimedistribution.dsn"
         "NodeTimeDistribution")
      (Path "Design Resources" ".\nodetimedistribution.dsn" "BlkDiagram")
      (Path "Design Resources" ".\nodetimedistribution.dsn" "Design Cache")
      (Path "Outputs")
      (Select "Design Resources" ".\nodetimedistribution.dsn"
         "NodeTimeDistribution" "SCH, NTD WATCHDOG"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
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      (Schematic "NodeTimeDistribution")
      (Page "SCH, NTD, 8 WAY FAN-OUT"))
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      (Path
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      (Schematic "BlkDiagram")
      (Page "NTD_BLK_DIAGRAM")))
  (ISPCBBASICLICENSE "false"))
