<?xml version="1.0" encoding="UTF-8"?> <ExampleProgram> <Title> <Text Locale="US">Basic DMA.lvproj</Text> </Title> <Keywords> <Item>FPGA</Item> <Item>compact</Item> <Item>RIO</Item> <Item>basic</Item> <Item>DMA</Item> </Keywords> <Navigation> <Item>7618</Item> <Item>7680</Item> </Navigation> <FileType>LV Project</FileType> <Metadata> <Item Name="RTSupport">LV Project RT</Item> </Metadata> <ProgrammingLanguages> <Item>LabVIEW</Item> </ProgrammingLanguages> <RequiredSoftware> <NiSoftware MinVersion="8.0">LabVIEW</NiSoftware> </RequiredSoftware> <RequiredFPGAHardware> <Device> <Family>Backplanes</Family> <Family>Single Board RIO</Family> <Model>71C7</Model> <Model>729D</Model> <Model>70F6</Model> <Model>705E</Model> <Model>70F7</Model> <Model>70F8</Model> <Model>73F6</Model> <Model>73F7</Model> <Model>73F8</Model> <Model>73F9</Model> <Model>73FA</Model> <Model>73FB</Model> <Model>7373</Model> <Model>7375</Model> <Model>7397</Model> <Model>7398</Model> <Model>7399</Model> <Model>739A</Model> <Model>7378</Model> <Model>739B</Model> </Device> </RequiredFPGAHardware> </ExampleProgram> This project demonstrates a basic application using DMA to transfer data from an FPGA VI to a host VI. This example needs to be compiled for a specific FPGA target before use. For information on moving this example to another FPGA target, refer to ni.com/info and enter info code fpgaex. OS,Win;CPU,x86; true true false 0 My Computer/VI Server My Computer/VI Server true true false NI-cRIO9022-014C9009 134.89.11.103 TARGET_TYPE,RT;OS,VxWorks;CPU,PowerPC; 900x true 5000 1000 2 14 false 300 80 60 true 100 10000 0 0 false true true /c/ni-rt/startup/startup.rtexe true +* false /c/ni-rt/startup true true +* false true 3363 Main Application Instance/VI Server Main Application Instance/VI Server +* true true false false /c/ni-rt/system/www/www.log 80 /c/ni-rt/system/www c+* 60 +* PqVr/ifkAQh+lVrdPIykXlFvg12GhhQFR8H9cUhphgg=:pTe9HRlQuMfJxAG6QCGq7UvoUpJzAzWGKy5SbZ+roSU= 15 fpga cRIO-9101 false {2185D3E0-B785-4F92-A76B-5D00D930DBB6}resource=/crio_Analog Input Module/AI0;0;ReadMethodType=i16{6D544BD9-023D-43CE-9AED-AA4DF2C08516}NI 9201,Slot 1,0,cRIOModule.EnableHsInput=false,cRIOModule.EnableHsOutput=false,cRIOModule.MinConvTime=2.000000{EA068E54-7D64-4692-A52D-30170E64DF3A}"NumberOfElements=1023;DataType=7;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;WriteArbs=Arbitrate if Multiple Requestors Only;Implementation=2;DMA FIFO;FxpWordLength=32;FxpIntWordLength=32;FxpSigned=FALSE;FxpMin=0.000000;FxpMax=4294967295.000000;FxpDelta=1.000000"cRIO-9101//falseTARGET_TYPEFPGA AI0resource=/crio_Analog Input Module/AI0;0;ReadMethodType=i16Analog Input ModuleNI 9201,Slot 1,0,cRIOModule.EnableHsInput=false,cRIOModule.EnableHsOutput=false,cRIOModule.MinConvTime=2.000000cRIO-9101//falseTARGET_TYPEFPGADMA FIFO"NumberOfElements=1023;DataType=7;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;WriteArbs=Arbitrate if Multiple Requestors Only;Implementation=2;DMA FIFO;FxpWordLength=32;FxpIntWordLength=32;FxpSigned=FALSE;FxpMin=0.000000;FxpMax=4294967295.000000;FxpDelta=1.000000" FPGA Target 0 cRIO-9101//falseTARGET_TYPEFPGA true 4 RIO0::INSTR cRIO-9101 cRIO-9101/falseTARGET_TYPEFPGA 40 MHz Onboard Clock true 1 1 7 false "NumberOfElements=1023;DataType=7;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;WriteArbs=Arbitrate if Multiple Requestors Only;Implementation=2;DMA FIFO;FxpWordLength=32;FxpIntWordLength=32;FxpSigned=FALSE;FxpMin=0.000000;FxpMax=4294967295.000000;FxpDelta=1.000000" true true ##"A)A!!!!U!$E!Q`````Q2/97VF!!!+1!=&2'6Q>'A!.1$R!!!!!!!!!!%92GFG<V^%982B6(FQ:5.P<H2S<WQO9X2M!".!!AJ%982B)&>J:(2I!!!R!0%!!!!!!!!!!2*';7:P8U2J=G6D>'FP<CZD>'Q!&5!$$5:*2E^%;8*F9X2J<WY!-!$R!!!!!!!!!!%42GFG<V^*4V.U=G&U:7>Z,G.U<!!51!%,35]A5X2S982F:XE!%E!Q`````QB73%2-4G&N:1!!1!$RPAH!FA!!!!%:2GFG<V^"=G*0=(2J<WZT5X2S;7ZH,G.U<!!?1$$`````%&*F971A18*C)%^Q>'FP<H-!!%!!]<Y*Q*9!!!!"'5:J:G^@18*C4X"U;7^O=V.U=GFO:SZD>'Q!(E!Q`````R&8=GFU:3""=G)A4X"U;7^O=Q!L!0%!!!!!!!!!!2"';7:P8UVF<62Z='5O9X2M!"&!!AB315UA>(FQ:1!!%%!(#U2.13"$;'&O<G6M!!R!)1:8=GFU:4]!!!J!)16-<W.B<!"&!0'`[U5V!!!!!1Z';7:P8V.U982F,G.U<!!N1&!!$!!!!!%!!A!$!!1!"1!'!!=!#!!*!!I!#QJ';7:P)&.U982F!!!"!!Q!!!!)2%V")%:*2E]!!!0`!!1!!!!!!1!!!$&%45&B2EF'4V]S-$%R-4-S.45S-D9Z-TAS-$ER/45U/41R/49R.4%S-4-R-$%R/$EZ!!!!%U^Q>'FN;8JF)%:P=C"4;7ZH<'5!!!!44X"U;7VJ?G5A2G^S)&.J<G>M:1!#!!!!!!%!!!!!!! true 9 {EA068E54-7D64-4692-A52D-30170E64DF3A} 2 false 1023 2 {2185D3E0-B785-4F92-A76B-5D00D930DBB6}resource=/crio_Analog Input Module/AI0;0;ReadMethodType=i16{6D544BD9-023D-43CE-9AED-AA4DF2C08516}NI 9201,Slot 1,0,cRIOModule.EnableHsInput=false,cRIOModule.EnableHsOutput=false,cRIOModule.MinConvTime=2.000000{EA068E54-7D64-4692-A52D-30170E64DF3A}"NumberOfElements=1023;DataType=7;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;WriteArbs=Arbitrate if Multiple Requestors Only;Implementation=2;DMA FIFO;FxpWordLength=32;FxpIntWordLength=32;FxpSigned=FALSE;FxpMin=0.000000;FxpMax=4294967295.000000;FxpDelta=1.000000"cRIO-9101//falseTARGET_TYPEFPGA AI0resource=/crio_Analog Input Module/AI0;0;ReadMethodType=i16Analog Input ModuleNI 9201,Slot 1,0,cRIOModule.EnableHsInput=false,cRIOModule.EnableHsOutput=false,cRIOModule.MinConvTime=2.000000cRIO-9101//falseTARGET_TYPEFPGADMA FIFO"NumberOfElements=1023;DataType=7;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;WriteArbs=Arbitrate if Multiple Requestors Only;Implementation=2;DMA FIFO;FxpWordLength=32;FxpIntWordLength=32;FxpSigned=FALSE;FxpMin=0.000000;FxpMax=4294967295.000000;FxpDelta=1.000000" C:\Program Files\National Instruments\LabVIEW 8.5\examples\CompactRIO\FPGA Fundamentals\DMA\Basic DMA Acquisition\FPGA Bitfiles\Basic DMA - cRIO.l~87_FPGA Target_Basic DMA (FPGA).vi.lvbit 0 Slot 1 false false NI 9201 2.000000 {6D544BD9-023D-43CE-9AED-AA4DF2C08516} /crio_Analog Input Module/AI0 {2185D3E0-B785-4F92-A76B-5D00D930DBB6} {354657BB-9E55-418F-A967-896C445B71B8} 100 Clk40 50 40000000 50 40000000 40000000 250 40 MHz Onboard Clock false Clk40 false true 4 {2185D3E0-B785-4F92-A76B-5D00D930DBB6}resource=/crio_Analog Input Module/AI0;0;ReadMethodType=i16{6D544BD9-023D-43CE-9AED-AA4DF2C08516}NI 9201,Slot 1,0,cRIOModule.EnableHsInput=false,cRIOModule.EnableHsOutput=false,cRIOModule.MinConvTime=2.000000{EA068E54-7D64-4692-A52D-30170E64DF3A}"NumberOfElements=1023;DataType=7;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;WriteArbs=Arbitrate if Multiple Requestors Only;Implementation=2;DMA FIFO;FxpWordLength=32;FxpIntWordLength=32;FxpSigned=FALSE;FxpMin=0.000000;FxpMax=4294967295.000000;FxpDelta=1.000000"cRIO-9101//falseTARGET_TYPEFPGA AI0resource=/crio_Analog Input Module/AI0;0;ReadMethodType=i16Analog Input ModuleNI 9201,Slot 1,0,cRIOModule.EnableHsInput=false,cRIOModule.EnableHsOutput=false,cRIOModule.MinConvTime=2.000000cRIO-9101//falseTARGET_TYPEFPGADMA FIFO"NumberOfElements=1023;DataType=7;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;WriteArbs=Arbitrate if Multiple Requestors Only;Implementation=2;DMA FIFO;FxpWordLength=32;FxpIntWordLength=32;FxpSigned=FALSE;FxpMin=0.000000;FxpMax=4294967295.000000;FxpDelta=1.000000"