Node Timing Distribution
Circuit Description

Please refer to sheet 1, "Sch, NTD Watchdog" dwg # 100221317

5 Volts DC power enters the pcb on J1.  Transient voltage suppression is provided by D2.  C7 and C6 provide filtering. Each integrated circuit package has a 0.1uF capacitor on its power pin. 

1 PPS pulses enter the pcb through SMA connectors J5 (Primary) and J4 (Secondary).  J5's Primary 1PPS signal is fed into the watchdog timer IC U6 MAX6814.  If a pulse does not arrive within 1.6 seconds on pin 4 (WDI), pin 1 (WDO_N) will go low, changing the state of NAND latch U4.

The output of the NAND latch drives U4A and U5B, providing 1 PPS source status to the PC104 stack.  If this output signal on J2 pin 2 is LOW, the Primary 1 PPS is active.  HIGH means the Secondary 1 PPS is active.

The output of the NAND latch also drives Data Selector U1 pin 6.

Note that SMA connector J4 (Secondary) drives Data Selector U1 pin 2.

If the Primary 1 PPS pulse train is interrupted, the Secondary 1 PPS pulse train will be output.  When the Primary 1 PPS pulse train is restored, the Primary 1 PPS pulse train will again become active.

The Primary 1 PPS pulse train is connected to Data Selector U1 pin 1.  The Y output of U1 pin 5 drives the signal 1 PPS OUT, which is conencted to the opto isolators on sheet 2 "Sch, NTD, 8 Way Fan-out".

The signal 1 PPS OUT drives inverter U5C CD74HC4049, which in turn drives U5A U5F, U5E and U5D.  The outputs of these four inverters are coupled through current limiting resistors R2, R3, R4 and R5 to the base pins of NPN transistors Q1, Q2, Q3 and Q4.

The emitters of the NPN transistors are grounded.  The collectors of the NPN transistors are connected through current limiting resistors R8, R11, R14 and R17 to opto isolator ( 4N37S ) input diodes in U2, U3, U7, U8, U9, U10, U11 and U12.  A 15k resistor pull down  is tied from the emitter to the base of each output transistor.

Each opto isolator output transistor is connected to J8 "Isolated 1 PPS Outputs, 8 Channels".  Each of these eight channels is electrically isolated from the pcb, and from each other.

NOTE:  A DC power source and a pull-up resistor will be required on each 1 PPS receiving circuit external to this Node Timing Distribution PCB.