ADS1271 control protocol for MMB0 ================================= M. Ashton Texas Instruments Inc. This protocol is designed for reliable collection of data over USB from one or more ADS1271 devices. In this application, it is critical that samples not be lost, but it is not critical that data be delivered to the host in real time. Therefore, we do not use isochronous transfers at all. The firmware uses a two-stage DMA arrangement to retrieve data from the ADC. Data from the ADC is read into a two-way ping-pong buffer in 32 bit format. Data is then packed into 24 bit words and stored in a block FIFO. USB transfers operate on the FIFO. This is done because the DMA cannot copy 24 bit words directly into memory from the ADC, but it can pack 32 bit words into 24 from memory to memory. The board is always in one of the following states. After USB enumeration, the board is in IDLE: - IDLE - the board is doing nothing, and is ready to receive commands. The ADC may be sampling, but data is not being read from it. - ADCSTT - ADC DMA is starting. The board is waiting for the first DMA transfer to occur from the ADC. If the ADC is not connected, or the DMA somehow misses its sync signal, the board will remain in this state until stopped; there is no timeout. - ADCRUN - ADC running. Data is being read from the ADC into the ping-pong buffers, but is not being stored in the FIFO. - ADCSTP - ADC DMA is being stopped. The board is waiting for the current DMA transfer to complete, if any. Once it does, it returns to IDLE state. - RDATA - Data is being copied from the ping-pong buffers into the FIFO, and can be read through USB. - TSTRAM - RAM is being tested. This operation takes some time. Once the operation completes, the board returns to IDLE mode. - TSTFLASH - Flash is being tested. Once the operation completes, the board returns to IDLE. To acquire data from the board, the host must do the following, starting from IDLE mode: - Select which channels to read. Optionally set the sample rate and conversion mode. The channel selection cannot be changed while the ADC is running, but the sample rate and conversion mode can be, at the cost of corrupting data. - Issue ADCSTT, and wait for the board to enter ADCRUN. Optionally time out if the board does not enter ADCRUN in the expected time. If this happens, issue ADCSTP. - Issue RDATA. Specify the number of blocks to collect in this command. - Read the desired number of blocks from IN endpoint 1, as described below. IN endpoint 1 is used to collect data from the FIFO. The endpoint NAKs if no data is available. Data is transmitted block by block; each block ends with a short packet. No zero-length packet is transmitted at the end of a transfer; the host must keep track of how many blocks it has received, and stop retrieving once this reaches the requested count. The board will remain in RDATA until all requested blocks have been retrieved. It may exit RDATA early, since the board cannot tell exactly when the host reads a packet; it can only tell when a USB DMA transfer has completed. An RDATA can be cancelled by issuing RDSTOP, but this does not affect an ongoing packet transmission; these cannot be stopped by the board. Control transfers ----------------- All control transfers are performed with bmRequestType set up for Vendor type transfers with a recipient of Interface. bRequest and wValue depend on the message. wIndex specifies the interface on which this protocol is being run. wLength is set up in the usual fashion. Messages -------- * = not implemented 00: STATE: (r) get board state Returns a byte indicating current board state. If the high bit is set, an error occured. An error status is read only once. After an error status is read, status changes to the status given in parentheses after the error code. 0 = IDLE = idle 1 = ADCSTT = starting ADC 2 = ADCRUN = ADC running 3 = ADCSTP = stopping ADC 4 = RDATA = retrieving data 5 = TSTRAM = testing RAM 8 = TSTFLASH = testing flash 86 = ADSERR = ADC start error (IDLE) 02: ADCSTT: (w) start ADC Starts the conversion process on the given channels. Valid only during IDLE status; ignored other times. Four bytes of data form a 32-bit channel map. A one in a bit means that the corresponding channel should be read. (* not implemented yet) When this command is issued, status moves to ADCSTT. If the ADC starts successfully, status moves to ADCRUN; otherwise status moves to ADSERR. 03: ADCSTP: (w) stop ADC Stops conversion. Valid during ADCRUN and RDATA. When this command is issued, status moves to ADCSTP, then to IDLE once the conversion process is stopped. 04: RDATA: (w) retrieve n blocks Data is 32 bits unsigned indicating number of blocks to convert. Maximum is on board buffer length, which you can retrieve with the BUFLEN command. If data exceeds available buffer length, it is silently clamped. *06: CLEAR: (w) clear sample buffer 07: AVAIL: (r) number of blocks available Returns the number of blocks available to be read as 32 bits unsigned. If a block is actively being read, it is included in the count. 09: BUFLEN: (r) get capacity of buffer in blocks Returns the number of blocks the buffer can hold. Data is passed as 32 bits unsigned. Note that this is affected by the block size and number of active channels. 0A: BLOCKSIZE: (r/w) get/set block size in samples Write: Value is block size in samples. Valid only during IDL Read: Returns number of samples per block as a 16 bit unsigned integer. 0B: CMODE: (r/w) Conversion mode Value is the conversion mode as follows: 0 = high speed 1 = high resolution 2 = low power Valid any time, but setting it during data retrieval will interrupt conversions, since it causes a sync. 10: SRATE: (r/w) sampling rate on all channels Sample rate is a 32-bit unsigned integer passed in the data packet, which is the desired sampling frequency in millihertz. A read of this returns the actual current sample rate (also in millihertz). It may be different from what was written, but should be close, unless it was clamped for some reason. *11: IFACE: (r) interface mode The ADS1271EVM has a switch to select the interface mode. The position of the switch on the first board in the stack is read by the software at conversion start time. This command reports what mode the board is running in. 0 = SPI 1 = FSYNC F0: TSTRAM: (r/w) test SDRAM A write initiates the SDRAM test. If you write TSTRAM while a test is in progress, the test continues and the write is ignored. The RAM test cannot be cancelled. You can test the RAM multiple times. You can only write TSTRAM when the board status is IDLE. If you write TSTRAM when the board is in another status except RAM test, the write stalls. To monitor the progress of the test, issue TSTRAM as a read. The first byte is as follows: 0 = RAM not yet tested 1 = RAM tested and passed 2 = Test in progress - writing 3 = Test failed 4 = Test in progress - reading If the first byte is 2 or 4, the second and third bytes are the number of 128kbyte pages successfully tested so far. The test proceeds in two phases: first the SDRAM is written, and then it is read. While writing, the status is 2; while reading, the status is 4. If the first byte is 3, the RAM test failed. The second and third bytes give the page number that failed. If the first byte is 0 or 1, the second and third bytes are undefined and should be ignored. TSTRAM can be read at any time, whether the test has been started or not. You can read TSTRAM during conversions. F1: LEDSW: (r/w) Set LED, read switches A write sets the LED display to the byte given by Value. Byte format is pabcdefg. A read returns two bytes. The first is the state of the LED. The second byte indicates the state of switches SWA and SWB as follows: Bit 0: 0 = SWA up, 1 = SWA pressed Bit 1: 0 = SWB up, 1 = SWB pressed *F2: TOUTFREQ: (r) Measure the frequency appearing on the TOUT pin *F3: TSTCLK: (r/w) Test the clock synthesiser Runs the clock synthesiser at several frequencies, measuring each to make sure that the synthesiser is working properly. 0 = Not yet tested 1 = Tested and passed 2 = Test in progress 3 = Test failed *F4: WFLASH: (r/w) Write to flash Write data to flash. The first three data bytes form a 24-bit address, which points to a location in the flash memory. Data is written beginning at this location, and is passed through Endpoint 1. Up to 128 kilobytes can be written. The write stops with a short data packet or with EFLASH. Before any data is written, the sector containing the data is erased. This is done as needed. If any data is written to a sector, that sector is erased completely. The write operation takes time. Progress can be monitored by reading WFLASH, which returns a 3-byte code. The first byte is a status code; the second two bytes are the number of 256-byte blocks written so far, where applicable. Codes are: 0 = no write in progress / done 1 = erasing 2 = writing; number of pages in next two bytes This command can only be issued during the IDLE state, and places the board in the WFLASH state temporarily. *F5: RFLASH: (w) Read from flash Read data from flash. Three bytes identify the desired starting address, and Value gives the number of bytes to read, up to 2048. After issuing this, data can be read out over IN endpoint 1. The operation can be cancelled early using EFLASH. This command can only be issued during the IDLE state, and places the board in the RFLASH state while the read is going on. *F6: EFLASH: (w) End flash operation End flash read or write, if any. Returns the board to IDLE. Ignored during any state except RFLASH and WFLASH. F7: TSTFLASH: (r/w) Test flash Tests communication with the flash memory. Reading this returns the result of the last test, which is one of: 0 = not tested 1 = flash OK 2 = flash not detected or not OK While the test is in process, the board is in the TSTFLASH state. After the test, the board returns to IDLE. This command can only be issued during the IDLE state.