//Modified by Jackie Zhang #ifndef CSPI_DEFINES_H__ #define CSPI_DEFINES_H__ /* Prevent multiple inclusions */ // ========================================================================= // // ------------------------ CSPI 1 specific defines ------------------------ // // ========================================================================= // #ifdef SELECT_CSPI1 // // Register layout; inherits addresses and offsets from memory_map_defines.h // #define CSPI_REG_BASE CSPI1_BASE_ADDR #define CSPI_REG_RXDATA CSPI1_RXDATA #define CSPI_REG_TXDATA CSPI1_TXDATA #define CSPI_REG_CON CSPI1_CONREG #define CSPI_REG_INT CSPI1_INTREG #define CSPI_REG_DMA CSPI1_DMAREG #define CSPI_REG_STAT CSPI1_STATREG #define CSPI_REG_PERIOD CSPI1_PERIODREG #define CSPI_REG_TEST CSPI1_TESTREG /* Disables all interrupts related to CSPI1: #14 for Tortola */ #define DISABLE_ALL_CSPI_IRQS \ reg32write(AVIC_INTDISNUM, 14) #define RE_ENABLE_ALL_CSPI_IRQS \ reg32write(AVIC_INTENNUM, 14) #define CSPI_INT_ROUTINE \ CSPI1_INT_ROUTINE #endif /* SELECT_CSPI1 */ // ========================================================================= // // ------------------------ CSPI 2 specific defines ------------------------ // // ========================================================================= // #ifdef SELECT_CSPI2 // // Register layout; inherits addresses and offsets from memory_map_defines.h // #define CSPI_REG_BASE CSPI2_BASE_ADDR #define CSPI_REG_RXDATA CSPI2_RXDATA #define CSPI_REG_TXDATA CSPI2_TXDATA #define CSPI_REG_CON CSPI2_CONREG #define CSPI_REG_INT CSPI2_INTREG #define CSPI_REG_DMA CSPI2_DMAREG #define CSPI_REG_STAT CSPI2_STATREG #define CSPI_REG_PERIOD CSPI2_PERIODREG #define CSPI_REG_TEST CSPI2_TESTREG /* Disables all interrupts related to CSPI2: #13 for Tortola */ #define DISABLE_ALL_CSPI_IRQS \ reg32write(AVIC_INTDISNUM, 13) #define RE_ENABLE_ALL_CSPI_IRQS \ reg32write(AVIC_INTENNUM, 13) #define CSPI_INT_ROUTINE \ CSPI2_INT_ROUTINE #endif /* SELECT_CSPI2 */ // ========================================================================= // // ------------------------ CSPI 3 specific defines ------------------------ // // ========================================================================= // #ifdef SELECT_CSPI3 // Register layout; inherits addresses and offsets from memory_map_defines.h #define CSPI_REG_BASE CSPI3_BASE_ADDR #define CSPI_REG_RXDATA CSPI3_RXDATA #define CSPI_REG_TXDATA CSPI3_TXDATA #define CSPI_REG_CON CSPI3_CONREG #define CSPI_REG_INT CSPI3_INTREG #define CSPI_REG_DMA CSPI3_DMAREG #define CSPI_REG_STAT CSPI3_STATREG #define CSPI_REG_PERIOD CSPI3_PERIODREG #define CSPI_REG_TEST CSPI3_TESTREG /* Disables all interrupts related to CSPI2: #17 for Tortola */ #define DISABLE_ALL_CSPI_IRQS \ reg32write(AVIC_INTDISNUM, 17) #define RE_ENABLE_ALL_CSPI_IRQS \ reg32write(AVIC_INTENNUM, 17) #define CSPI_INT_ROUTINE \ CSPI3_INT_ROUTINE #endif /* SELECT_CSPI3 */ void cspi_setup_iomux( void ) { #ifdef SELECT_CSPI1 reg32write(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI, 0x12120212); reg32write(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1, 0x12121212); // Selects the CSPI2'SS1 | CSPI1'SS3 out of the UART stuff reg32write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x01240101); // Selects the CSPI1'SS3 to be feed back to its input reg32write(SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2, 0x01013801); #endif #ifdef SELECT_CSPI2 // Functional mode, no pad sharing between cspi's reg32write(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1, 0x12120101); // 0x12121212 ??? reg32write(SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2, 0x12121212); reg32write(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI, 0x12121201); reg32write(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1, 0x12121212); #endif #ifdef SELECT_CSPI3 hal_reg32_write(SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD,0x12120200); hal_reg32_write(SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI,0x00000012); config_pad_mode(CSPI1_SS0,alt2_out,alt2_in); hal_reg32_write(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1,0x00003800); config_pad_mode(CSPI1_SS2,alt2_out,alt2_in); hal_reg32_write(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI,0x38000000); config_pad_mode(CSPI2_SS0,alt1_out,alt1_in); config_pad_mode(CSPI2_SS1,alt1_out,alt1_in); hal_reg32_write(SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2,0x00242400); #endif } // ========================================================================= // // -------------------------- CSPI register layout ------------------------- // // ========================================================================= // /*----------------------------------------------------------------------------*\ Bit masks used to describe the registers of the CSPI, there are four masks - ... _RESETVAL - Expected register value after hardware reset - ... _READONLY - A bit set within this mask denotes a read-only bit - ... _FIXED0 - A bit set within this mask denotes a reserved bit ('0') - ... _FIXED1 - A bit set within this mask denotes a reserved bit ('1') - ... _NOTTOUCH - A bit set within this mask denotes that the corresponding bit has side effects and should not be exercised. - ... _DISABLES - Defines the value to be used for bits with side effects \*----------------------------------------------------------------------------*/ /* RXDATA - if disabled set to 0x0000_0000 */ #define CSPI_REG_RXDATA_RESETVAL 0x00000000 #define CSPI_REG_RXDATA_READONLY 0xFFFFFFFF #define CSPI_REG_RXDATA_FIXED0 0x00000000 #define CSPI_REG_RXDATA_FIXED1 0x00000000 #define CSPI_REG_RXDATA_NOTTOUCH 0x00000000 #define CSPI_REG_RXDATA_DISABLES 0x00000000 /* TXDATA - if disabled set to 0x0000_0000 */ #define CSPI_REG_TXDATA_RESETVAL 0x00000000 #define CSPI_REG_TXDATA_READONLY 0xFFFFFFFF #define CSPI_REG_TXDATA_FIXED0 0x00000000 #define CSPI_REG_TXDATA_FIXED1 0x00000000 #define CSPI_REG_TXDATA_NOTTOUCH 0x00000000 #define CSPI_REG_TXDATA_DISABLES 0x00000000 /* CONREG */ #define CSPI_REG_CON_RESETVAL 0x00000000 #define CSPI_REG_CON_READONLY 0x00000005 #define CSPI_REG_CON_FIXED0 0xFCC8E000 #define CSPI_REG_CON_FIXED1 0x00000000 #define CSPI_REG_CON_NOTTOUCH 0x00000005 /* don't touch XCH & EN */ #define CSPI_REG_CON_DISABLES 0x00000001 /* always enable the SPI */ /* INTREG - if disabled set to 0x0000_0000 */ #define CSPI_REG_INT_RESETVAL 0x00000000 #define CSPI_REG_INT_READONLY 0x00000000 #define CSPI_REG_INT_FIXED1 0x00000000 #define CSPI_REG_INT_FIXED0 0xFFFFFE00 #define CSPI_REG_INT_NOTTOUCH 0x00000000 #define CSPI_REG_INT_DISABLES 0x00000000 /* DMAREG - if disabled set to 0x0000_0000 */ #define CSPI_REG_DMA_RESETVAL 0x00000000 #define CSPI_REG_DMA_READONLY 0x00000033 #define CSPI_REG_DMA_FIXED0 0xFFFFFFCC #define CSPI_REG_DMA_FIXED1 0x00000000 #define CSPI_REG_DMA_NOTTOUCH 0x00000033 /* don't touch any DMA request */ //#define CSPI_REG_DMA_NOTTOUCH 0x00000000 #define CSPI_REG_DMA_DISABLES 0x00000000 /* STATREG - if disabled set to 0x0000_0000 */ #define CSPI_REG_STAT_RESETVAL 0x00000003 #define CSPI_REG_STAT_READONLY 0x000001FF #define CSPI_REG_STAT_FIXED0 0xFFFFFE00 #define CSPI_REG_STAT_FIXED1 0x00000000 #define CSPI_REG_STAT_NOTTOUCH 0x00000000 #define CSPI_REG_STAT_DISABLES 0x00000000 /* PERIODREG - if disabled set to 0x0000_0000 */ #define CSPI_REG_PERIOD_RESETVAL 0x00000000 #define CSPI_REG_PERIOD_READONLY 0x00000000 #define CSPI_REG_PERIOD_FIXED1 0x00000000 #define CSPI_REG_PERIOD_FIXED0 0xFFFF0000 #define CSPI_REG_PERIOD_NOTTOUCH 0x00000000 #define CSPI_REG_PERIOD_DISABLES 0x00000000 /* TESTREG - if disabled set to 0x0000_0000 */ #define CSPI_REG_TEST_RESETVAL 0x00000000 #define CSPI_REG_TEST_READONLY 0x00000FFF #define CSPI_REG_TEST_FIXED1 0x00000000 #define CSPI_REG_TEST_FIXED0 0xFFFF3000 #define CSPI_REG_TEST_NOTTOUCH 0x00000000 #define CSPI_REG_TEST_DISABLES 0x00000000 // ========================================================================= // // -------------------------- CSPI register content ------------------------ // // ========================================================================= // /*----------------------------------------------------------------------------*\ CONREG - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define CSPI_CON_CHIP_SEL_BP 24 #define CSPI_CON_CHIP_SEL_SZ 0x3 #define CSPI_CON_DRCTL_BP 20 #define CSPI_CON_DRCTL_SZ 0x3 #define CSPI_CON_DATARATE_BP 16 #define CSPI_CON_DATARATE_SZ 0x7 #define CSPI_CON_BITCOUNT_BP 8 #define CSPI_CON_BITCOUNT_SZ 0x1F #define CSPI_CON_SSPOL_BP 7 #define CSPI_CON_SSCTL_BP 6 #define CSPI_CON_PHA_BP 5 #define CSPI_CON_POL_BP 4 #define CSPI_CON_SMC_BP 3 #define CSPI_CON_XCH_BP 2 #define CSPI_CON_MODE_BP 1 #define CSPI_CON_EN_BP 0 #define CSPI_CON_SSPOL (1 << CSPI_CON_SSPOL_BP) #define CSPI_CON_SSCTL (1 << CSPI_CON_SSCTL_BP) #define CSPI_CON_PHA (1 << CSPI_CON_PHA_BP) #define CSPI_CON_POL (1 << CSPI_CON_POL_BP) #define CSPI_CON_SMC (1 << CSPI_CON_SMC_BP) #define CSPI_CON_XCH (1 << CSPI_CON_XCH_BP) #define CSPI_CON_MODE (1 << CSPI_CON_MODE_BP) #define CSPI_CON_EN (1 << CSPI_CON_EN_BP) /*----------------------------------------------------------------------------*\ INTREG - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define CSPI_INT_TCEN_BP 8 #define CSPI_INT_BOEN_BP 7 #define CSPI_INT_ROEN_BP 6 #define CSPI_INT_RFEN_BP 5 #define CSPI_INT_RHEN_BP 4 #define CSPI_INT_RREN_BP 3 #define CSPI_INT_TFEN_BP 2 #define CSPI_INT_THEN_BP 1 #define CSPI_INT_TEEN_BP 1 #define CSPI_INT_TCEN (1 << CSPI_INT_TCEN_BP) #define CSPI_INT_BOEN (1 << CSPI_INT_BOEN_BP) #define CSPI_INT_ROEN (1 << CSPI_INT_ROEN_BP) #define CSPI_INT_RFEN (1 << CSPI_INT_RFEN_BP) #define CSPI_INT_RHEN (1 << CSPI_INT_RHEN_BP) #define CSPI_INT_RREN (1 << CSPI_INT_RREN_BP) #define CSPI_INT_TFEN (1 << CSPI_INT_TFEN_BP) #define CSPI_INT_THEN (1 << CSPI_INT_THEN_BP) #define CSPI_INT_TEEN (1 << CSPI_INT_TEEN_BP) /*----------------------------------------------------------------------------*\ DMAREG - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define CSPI_DMA_RFDEN_BP 5 #define CSPI_DMA_RHDEN_BP 4 #define CSPI_DMA_THDEN_BP 1 #define CSPI_DMA_TEDEN_BP 0 #define CSPI_DMA_RFDEN (1 << CSPI_DMA_RFDEN_BP) #define CSPI_DMA_RHDEN (1 << CSPI_DMA_RHDEN_BP) #define CSPI_DMA_THDEN (1 << CSPI_DMA_THDEN_BP) #define CSPI_DMA_TEDEN (1 << CSPI_DMA_TEDEN_BP) /*----------------------------------------------------------------------------*\ STATREG - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define CSPI_STAT_TC_BP 8 #define CSPI_STAT_BO_BP 7 #define CSPI_STAT_RO_BP 6 #define CSPI_STAT_RF_BP 5 #define CSPI_STAT_RH_BP 4 #define CSPI_STAT_RR_BP 3 #define CSPI_STAT_TF_BP 2 #define CSPI_STAT_TH_BP 1 #define CSPI_STAT_TE_BP 0 #define CSPI_STAT_TC (1 << CSPI_STAT_TC_BP) #define CSPI_STAT_BO (1 << CSPI_STAT_BO_BP) #define CSPI_STAT_RO (1 << CSPI_STAT_RO_BP) #define CSPI_STAT_RF (1 << CSPI_STAT_RF_BP) #define CSPI_STAT_RH (1 << CSPI_STAT_RH_BP) #define CSPI_STAT_RR (1 << CSPI_STAT_RR_BP) #define CSPI_STAT_TF (1 << CSPI_STAT_TF_BP) #define CSPI_STAT_TH (1 << CSPI_STAT_TH_BP) #define CSPI_STAT_TE (1 << CSPI_STAT_TE_BP) /*----------------------------------------------------------------------------*\ PERIODREG - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define CSPI_PERIOD_SAMPLE_SZ 0x7FFF #define CSPI_PERIOD_SAMPLE_BP 0 #define CSPI_PERIOD_CSRC_BP 15 #define CSPI_PERIOD_CSRC (1 << CSPI_PERIOD_CSRC_BP) /*----------------------------------------------------------------------------*\ TESTREG - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define CSPI_TEST_SMSTATUS_BP 8 #define CSPI_TEST_SMSTATUS_SZ 0xF #define CSPI_TEST_RXCNT_BP 4 #define CSPI_TEST_RXCNT_SZ 0xF #define CSPI_TEST_TXCNT_BP 0 #define CSPI_TEST_TXCNT_SZ 0xF #define CSPI_TEST_LBC_BP 14 #define CSPI_TEST_LBC (1 << CSPI_TEST_LBC_BP) /******************************************************************************/ /* These following defines are done in the same style as the rest of the HAL */ /* to provide compatibility */ /******************************************************************************/ /******************************************************************************/ /** @name CONREG Register. */ /*@{ BEGIN ----------------------------------------------------------------- */ /** */ #define cspi_conreg_bitpos_en bit_pos_0 /** */ #define cspi_conreg_bitpos_mode bit_pos_1 /** */ #define cspi_conreg_bitpos_xch bit_pos_2 /** */ #define cspi_conreg_bitpos_smc bit_pos_3 /** */ #define cspi_conreg_bitpos_pol bit_pos_4 /** */ #define cspi_conreg_bitpos_pha bit_pos_5 /** */ #define cspi_conreg_bitpos_ssctl bit_pos_6 /** */ #define cspi_conreg_bitpos_sspol bit_pos_7 /** */ #define cspi_conreg_bitpos_bitcount bit_pos_8 /** */ #define cspi_conreg_bitpos_datarate bit_pos_16 /** */ #define cspi_conreg_bitpos_drctl bit_pos_20 /** */ #define cspi_conreg_bitpos_chipselect bit_pos_24 /** */ #define cspi_conreg_bitfld_en bit_field_1 /** */ #define cspi_conreg_bitfld_mode bit_field_1 /** */ #define cspi_conreg_bitfld_xch bit_field_1 /** */ #define cspi_conreg_bitfld_smc bit_field_1 /** */ #define cspi_conreg_bitfld_pol bit_field_1 /** */ #define cspi_conreg_bitfld_pha bit_field_1 /** */ #define cspi_conreg_bitfld_ssctl bit_field_1 /** */ #define cspi_conreg_bitfld_sspol bit_field_1 /** */ #define cspi_conreg_bitfld_bitcount bit_field_5 /** */ #define cspi_conreg_bitfld_datarate bit_field_3 /** */ #define cspi_conreg_bitfld_drctl bit_field_2 /** */ #define cspi_conreg_bitfld_chipselect bit_field_2 /*@} END CONREG register -------------------------------------------------------- */ /******************************************************************************/ /** @name INTREG Register. */ /*@{ BEGIN ----------------------------------------------------------------- */ /** */ #define cspi_intreg_bitpos_teen bit_pos_0 /** */ #define cspi_intreg_bitpos_then bit_pos_1 /** */ #define cspi_intreg_bitpos_tfen bit_pos_2 /** */ #define cspi_intreg_bitpos_rren bit_pos_3 /** */ #define cspi_intreg_bitpos_rhen bit_pos_4 /** */ #define cspi_intreg_bitpos_rfen bit_pos_5 /** */ #define cspi_intreg_bitpos_roen bit_pos_6 /** */ #define cspi_intreg_bitpos_boen bit_pos_7 /** */ #define cspi_intreg_bitpos_tcen bit_pos_8 /** */ #define cspi_intreg_bitfld_teen bit_field_1 /** */ #define cspi_intreg_bitfld_then bit_field_1 /** */ #define cspi_intreg_bitfld_tfen bit_field_1 /** */ #define cspi_intreg_bitfld_rren bit_field_1 /** */ #define cspi_intreg_bitfld_rhen bit_field_1 /** */ #define cspi_intreg_bitfld_rfen bit_field_1 /** */ #define cspi_intreg_bitfld_roen bit_field_1 /** */ #define cspi_intreg_bitfld_boen bit_field_1 /** */ #define cspi_intreg_bitfld_tcen bit_field_1 /*@} END INTREG register ----------------------------------------------------- */ /******************************************************************************/ /** @name DMAREG Register. */ /*@{ BEGIN ----------------------------------------------------------------- */ /** */ #define cspi_dmareg_bitpos_teden bit_pos_0 /** */ #define cspi_dmareg_bitpos_thden bit_pos_1 /** */ #define cspi_dmareg_bitpos_rhden bit_pos_4 /** */ #define cspi_dmareg_bitpos_rfden bit_pos_5 /** */ #define cspi_dmareg_bitfld_teden bit_field_1 /** */ #define cspi_dmareg_bitfld_thden bit_field_1 /** */ #define cspi_dmareg_bitfld_rhden bit_field_1 /** */ #define cspi_dmareg_bitfld_rfden bit_field_1 /*@} END DMAREG register ----------------------------------------------------- */ /******************************************************************************/ /** @name STATREG Register. */ /*@{ BEGIN ----------------------------------------------------------------- */ /** */ #define cspi_statreg_bitpos_te bit_pos_0 /** */ #define cspi_statreg_bitpos_th bit_pos_1 /** */ #define cspi_statreg_bitpos_tf bit_pos_2 /** */ #define cspi_statreg_bitpos_rr bit_pos_3 /** */ #define cspi_statreg_bitpos_rh bit_pos_4 /** */ #define cspi_statreg_bitpos_rf bit_pos_5 /** */ #define cspi_statreg_bitpos_ro bit_pos_6 /** */ #define cspi_statreg_bitpos_bo bit_pos_7 /** */ #define cspi_statreg_bitpos_tc bit_pos_8 /** */ #define cspi_statreg_bitfld_te bit_field_1 /** */ #define cspi_statreg_bitfld_th bit_field_1 /** */ #define cspi_statreg_bitfld_tf bit_field_1 /** */ #define cspi_statreg_bitfld_rr bit_field_1 /** */ #define cspi_statreg_bitfld_rh bit_field_1 /** */ #define cspi_statreg_bitfld_rf bit_field_1 /** */ #define cspi_statreg_bitfld_ro bit_field_1 /** */ #define cspi_statreg_bitfld_bo bit_field_1 /** */ #define cspi_statreg_bitfld_tc bit_field_1 /*@} END STATREG register ----------------------------------------------------- */ /******************************************************************************/ /** @name PERIODREG Register. */ /*@{ BEGIN ----------------------------------------------------------------- */ /** */ #define cspi_periodreg_bitpos_sampleperiod bit_pos_0 /** */ #define cspi_periodreg_bitpos_csrc bit_pos_15 /** */ #define cspi_periodreg_bitfld_sampleperiod bit_field_15 /** */ #define cspi_periodreg_bitfld_csrc bit_field_1 /*@} END PERIODREG register ----------------------------------------------------- */ /******************************************************************************/ /** @name TESTREG Register. */ /*@{ BEGIN ----------------------------------------------------------------- */ /** */ #define cspi_testreg_bitpos_txcnt bit_pos_0 /** */ #define cspi_testreg_bitpos_rxcnt bit_pos_4 /** */ #define cspi_testreg_bitpos_smstatus bit_pos_8 /** */ #define cspi_testreg_bitpos_lbc bit_pos_14 /** */ #define cspi_testreg_bitfld_txcnt bit_field_4 /** */ #define cspi_testreg_bitfld_rxcnt bit_field_4 /** */ #define cspi_testreg_bitfld_smstatus bit_field_4 /** */ #define cspi_testreg_bitfld_lbc bit_field_1 /*@} END TESTREG register ----------------------------------------------------- */ /*@} END CSPI register bit layout -------------------------------------------- */ #endif /* #ifndef CSPI_DEFINES_H__ */