//#include "/vobs/vb_tortola/tortola_projectdir/validation/EVB/src/ccm/src/evb_functions.c" //#include "evb_functions.c" // Enable all 3 PLLs #define MPLL 0x01 #define SPLL 0x02 #define UPLL 0x03 #define FPM_SOURCE_CLK 0x04 #define CKIH_SOURCE_CLK 0x05 #define REF 0x06 #define AHB 0x07 #define ARM 0x08 #define EMI 0x09 #define IPU 0x0a #define NFC 0x0b #define HSP 0x0c #define PER 0x0d #define CIR1 0x0e #define CIR2 0x0f #define CIR3 0x10 #define IPG 0x11 void plls_enable (void); // Enable MPLL void mpll_enable (void); // Enable SPLL void spll_enable (void); // Enable UPLL void upll_enable (void); // Enable FPM void fpm_enable (void); // Disable MPLL void mpll_disable (void); // Disable SPLL void spll_disable (void); // Disable UPLL void upll_disable (void); // Disable FPM void fpm_disable (void); // permitted frequencies are: 133, 266, 399 and 532. Deviation of 3% is permitted. int set_mpll_to_freq(WORD freq); // permitted frequencies are: 240, 480, 133, 266, 399 and 532. Deviation of 3% is permitted. int set_upll_to_freq(WORD freq); // permitted frequencies are: 133, 266, 399 and 532. Deviation of 3% is permitted. int set_spll_to_freq(WORD freq); //Writing to MPCTL/SPCTL/UPCTL register (programming PLL) when the frequency parameters are known. int write_to_N_pctl(WORD pd, WORD mfd, WORD mfi, WORD mfn, int pll_source); //Reading from MPCTL/SPCTL/UPCTL register relevant frequency parameter WORD get_pd_from_pll(int pll_source); WORD get_mfd_from_pll(int pll_source); WORD get_mfi_from_pll(int pll_source); WORD get_mfn_from_pll(int pll_source); //Calculating MPLL/SPLL/UPLL frequency relying on freq parameters in MPCTL/SPCTL/UPCTL register. int get_freq_from_pll(int pll_source); //PLL is enabled/disabled int get_pll_status (int pll_source); //Writing suitable set of freq parameters to MPCTL/SPCTL/UPCTL register int set_pll_to_given_freq(int freq, int pll_source); // set MPLL to freq = 133MHz (7.525 nsec). void set_mpll_to_133 (void); // set MPLL to freq = 266MHz (3.77 nsec) void set_mpll_to_266 (void); // set MPLL to freq = 399MHz (2.514 nsec) void set_mpll_to_399 (void); // set MPLL to freq = 532MHz (1.887 nsec) void set_mpll_to_532 (void); // set UPLL to freq = 133MHz (7.525 nsec). void set_upll_to_133 (void); // set UPLL to freq = 266MHz (3.77 nsec) void set_upll_to_266 (void); // set UPLL to freq = 399MHz (2.514 nsec) void set_upll_to_399 (void); // set UPLL to freq = 532MHz (1.887 nsec) void set_upll_to_532 (void); // set UPLL to freq = 480MHz (2.083 nsec) void set_upll_to_480 (void); // set UPLL to freq = 240MHz (4.167 nsec) void set_upll_to_240 (void); // set SPLL to freq = 133MHz (7.525 nsec). void set_spll_to_133 (void); // set SPLL to freq = 266MHz (3.77 nsec) void set_spll_to_266 (void); // set SPLL to freq = 399MHz (2.514 nsec) void set_spll_to_399 (void); // set SPLL to freq = 532MHz (1.887 nsec) void set_spll_to_532 (void); // MPLL = 1, UPLL = 2, SPLL = 3. Default source = SPLL int set_pll_source_for_ssi1_clk(int pll_source); int get_pll_source_for_ssi1_clk(); // MPLL = 1, UPLL = 2, SPLL = 3. Default source = SPLL int set_pll_source_for_ssi2_clk(int pll_source); int get_pll_source_for_ssi2_clk(); // MPLL = 1, UPLL = 2, SPLL = 3. Default source = UPLL int set_pll_source_for_firi_clk(int pll_source); int get_pll_source_for_firi_clk(); // UPLL = 2, SPLL = 3. Default source = SPLL int set_pll_source_for_csi_clk(int pll_source); int get_pll_source_for_csi_clk(); // UPLL = 2, IPG = 17. Default source = IPG int set_source_for_per_clk(int clk_source); int get_source_for_per_clk(); // FPM_SOURCE_CLK = 4, CKIH_SOURCE_CLK = 5. else - FAIL int set_source_for_ref_clk(int clk_source); int get_source_for_ref_clk(); // 1 < divider < 8 int set_mcu_div(WORD divider); int get_mcu_div(); // 1 < divider < 8 int set_hclk_div(WORD divider); int get_hclk_div(); // 1 < divider < 8 int set_hsp_div(WORD divider); int get_hsp_div(); // 1 < divider < 4 - AFTER HCLK_DIV int set_ipg_div(WORD divider); int get_ipg_div(); // 1 < divider < 8 - AFTER HCLK_DIV int set_nfc_div(WORD divider); int get_nfc_div(); // 1 < predivider < 8, 1 < postdivider < 64 int set_ssi1_pre_div(WORD predivider); int set_ssi1_post_div(WORD postdivider); int get_ssi1_pre_div(); int get_ssi1_post_div(); // 1 < predivider < 8, 1 < postdivider < 64 int set_ssi2_pre_div(WORD predivider); int set_ssi2_post_div(WORD postdivider); int get_ssi2_pre_div(); int get_ssi2_post_div(); // 1 < predivider < 8, 1 < postdivider < 64 int set_firi_pre_div(WORD predivider); int set_firi_post_div(WORD postdivider); int get_firi_pre_div(); int get_firi_post_div(); // 1 < predivider < 8, 1 < postdivider < 64 int set_usb_pre_div(WORD predivider); int set_usb_post_div(WORD postdivider); int get_usb_pre_div(); int get_usb_post_div(); // 1 < divider < 64 // UPLL int set_mstick1_div(WORD divider); int get_mstick1_div(); // 1 < divider < 64 // UPLL int set_mstick2_div(WORD divider); int get_mstick1_div(); // 1 < predivider < 8, 1 < postdivider < 64 - UPLL int set_csi_pre_div(WORD predivider); int set_csi_post_div(WORD postdivider); int get_csi_pre_div(); int get_csi_post_div(); // 1 < divider < 32 - AFTER UPLL, before per_clk_sel int set_per_div(WORD divider); int get_per_div(); int get_mcu_clk_freq (); int get_hsp_clk_freq (); int get_hclk_clk_freq(); int get_ipg_clk_freq (); int get_nfc_clk_freq (); int get_ssi1_clk_freq (); int get_ssi2_clk_freq (); int get_firi_clk_freq (); int get_usb_clk_freq (); int get_mstick1_clk_freq (); int get_mstick2_clk_freq (); int get_csi_clk_freq (); int get_per_clk_freq (); // Monitoring one of the clocks via CKO pad int set_cko_source(int source); // Checking which clock is monitored via CKO pad int get_cko_source(); // writing into COSR[CLKOUTDIV] 0 < divider < 4 int set_clkoutdiv (int power_divider); // Reading from COSR[CLKOUTDIV] power of divider for CKO source clock WORD get_clkoutdiv(); // Check COSR[CLKOEN], if 0 - CKO is disabled int check_if_cko_enabled (); // Write "1" into COSR[CLKOEN] (bit 9) void enable_cko (); // Write "0" into COSR[CLKOEN] (bit 9) void disable_cko (); // base freq = 532, configuring post dividers void init_ccm(); // Writing "1" to all the enable bits - AVIC_INTENABLEH and AVIC_INTENABLEL void enable_all_interrupts(); // clear SCC memory and the interrupts void init_scc(); // Presence of the peritherals (0:14) void init_spba_for_arm(); // init_weim and init_sram_stack void init_emi(); //setup task for the chip; base freq = 532 void init_default_1();