#ifndef ZZhang_define_h #define ZZhang_define_h //********************* // DEFINES //********************* #define LITTLE_ENDIAN //#define BIG_ENDIAN // Define the CSPI base address #define SPI_1_BASE 0x00213000 #define SPI_2_BASE 0x00219000 // Define the CSPI address #define SPIRXD1 *(P_U32)(SPI_1_BASE) #define SPITXD1 *(P_U32)(SPI_1_BASE+0x04 ) #define SPICONT1 *(P_U32)(SPI_1_BASE+0x08 ) #define SPIINTCS1 *(P_U32)(SPI_1_BASE+0x0c ) #define SPITEST1 *(P_U32)(SPI_1_BASE+0x10 ) #define SPISPC1 *(P_U32)(SPI_1_BASE+0x14 ) #define SPIDMA1 *(P_U32)(SPI_1_BASE+0x18 ) #define SPIRST1 *(P_U32)(SPI_1_BASE+0x1c ) #define SPIRXD2 *(P_U32)(SPI_2_BASE) #define SPITXD2 *(P_U32)(SPI_2_BASE+0x04 ) #define SPICONT2 *(P_U32)(SPI_2_BASE+0x08 ) #define SPIINTCS2 *(P_U32)(SPI_2_BASE+0x0c ) #define SPITEST2 *(P_U32)(SPI_2_BASE+0x10 ) #define SPISPC2 *(P_U32)(SPI_2_BASE+0x14 ) #define SPIDMA2 *(P_U32)(SPI_2_BASE+0x18 ) #define SPIRST2 *(P_U32)(SPI_2_BASE+0x1c ) // Define GPIO registers #define PORTA_BASE 0x0021C000 #define PORTB_BASE 0x0021C100 #define PORTC_BASE 0x0021C200 #define PORTD_BASE 0x0021C300 //Port A #define PA_DDR *(P_U32)(PORTA_BASE+0x00 ) #define PA_OCR1 *(P_U32)(PORTA_BASE+0x04 ) #define PA_OCR2 *(P_U32)(PORTA_BASE+0x08 ) #define PA_ICONFA1 *(P_U32)(PORTA_BASE+0x0c ) #define PA_ICONFA2 *(P_U32)(PORTA_BASE+0x10 ) #define PA_ICONFB1 *(P_U32)(PORTA_BASE+0x14 ) #define PA_ICONFB2 *(P_U32))(PORTA_BASE+0x18 ) #define PA_DR *(P_U32)(PORTA_BASE+0x1c ) #define PA_GIUS *(P_U32)(PORTA_BASE+0x20 ) #define PA_SSR *(P_U32)(PORTA_BASE+0x24 ) #define PA_ICR1 *(P_U32)(PORTA_BASE+0x28 ) #define PA_ICR2 *(P_U32)(PORTA_BASE+0x2c ) #define PA_IMR *(P_U32)(PORTA_BASE+0x30 ) #define PA_ISR *(P_U32)(PORTA_BASE+0x34 ) #define PA_GPR *(P_U32)(PORTA_BASE+0x38 ) #define PA_SWR *(P_U32)(PORTA_BASE+0x3c ) #define PA_PUEN *(P_U32)(PORTA_BASE+0x40 ) //Port B #define PB_DDR *(P_U32)(PORTB_BASE+0x00 ) #define PB_OCR1 *(P_U32)(PORTB_BASE+0x04 ) #define PB_OCR2 *(P_U32)(PORTB_BASE+0x08 ) #define PB_ICONFA1 *(P_U32)(PORTB_BASE+0x0c ) #define PB_ICONFA2 *(P_U32)(PORTB_BASE+0x10 ) #define PB_ICONFB1 *(P_U32)(PORTB_BASE+0x14 ) #define PB_ICONFB2 *(P_U32)(PORTB_BASE+0x18 ) #define PB_DR *(P_U32)(PORTB_BASE+0x1c ) #define PB_GIUS *(P_U32)(PORTB_BASE+0x20 ) #define PB_SSR *(P_U32)(PORTB_BASE+0x24 ) #define PB_ICR1 *(P_U32)(PORTB_BASE+0x28 ) #define PB_ICR2 *(P_U32)(PORTB_BASE+0x2c ) #define PB_IMR *(P_U32)(PORTB_BASE+0x30 ) #define PB_ISR *(P_U32)(PORTB_BASE+0x34 ) #define PB_GPR *(P_U32)(PORTB_BASE+0x38 ) #define PB_SWR *(P_U32)(PORTB_BASE+0x3c ) #define PB_PUEN *(P_U32)(PORTB_BASE+0x40 ) //Port C #define PC_DDR *(P_U32)(PORTC_BASE+0x00 ) #define PC_OCR1 *(P_U32)(PORTC_BASE+0x04 ) #define PC_OCR2 *(P_U32)(PORTC_BASE+0x08 ) #define PC_ICONFA1 *(P_U32)(PORTC_BASE+0x0c ) #define PC_ICONFA2 *(P_U32)(PORTC_BASE+0x10 ) #define PC_ICONFB1 *(P_U32)(PORTC_BASE+0x14 ) #define PC_ICONFB2 *(P_U32)(PORTC_BASE+0x18 ) #define PC_DR *(P_U32)(PORTC_BASE+0x1c ) #define PC_GIUS *(P_U32)(PORTC_BASE+0x20 ) #define PC_SSR *(P_U32)(PORTC_BASE+0x24 ) #define PC_ICR1 *(P_U32)(PORTC_BASE+0x28 ) #define PC_ICR2 *(P_U32)(PORTC_BASE+0x2c ) #define PC_IMR *(P_U32)(PORTC_BASE+0x30 ) #define PC_ISR *(P_U32)(PORTC_BASE+0x34 ) #define PC_GPR *(P_U32)(PORTC_BASE+0x38 ) #define PC_SWR *(P_U32)(PORTC_BASE+0x3c ) #define PC_PUEN *(P_U32)(PORTC_BASE+0x40 ) // Port D #define PD_DDR *(P_U32)(PORTD_BASE+0x00 ) #define PD_OCR1 *(P_U32)(PORTD_BASE+0x04 ) #define PD_OCR2 *(P_U32)(PORTD_BASE+0x08 ) #define PD_ICONFA1 *(P_U32)(PORTD_BASE+0x0c ) #define PD_ICONFA2 *(P_U32)(PORTD_BASE+0x10 ) #define PD_ICONFB1 *(P_U32)(PORTD_BASE+0x14 ) #define PD_ICONFB2 *(P_U32)(PORTD_BASE+0x18 ) #define PD_DR *(P_U32)(PORTD_BASE+0x1c ) #define PD_GIUS *(P_U32)(PORTD_BASE+0x20 ) #define PD_SSR *(P_U32)(PORTD_BASE+0x24 ) #define PD_ICR1 *(P_U32)(PORTD_BASE+0x28 ) #define PD_ICR2 *(P_U32)(PORTD_BASE+0x2c ) #define PD_ISR *(P_U32)(PORTD_BASE+0x34 ) #define PD_GPR *(P_U32)(PORTD_BASE+0x38 ) #define PD_SWR *(P_U32)(PORTD_BASE+0x3c ) #define PD_PUEN *(P_U32)(PORTD_BASE+0x40 ) //Define DMA registers (for channel 1 and 2) #define DMA_DCR_v *(P_U32)(DMA_SYS_BASE+0x000) #define DMA_ISR_v *(P_U32)(DMA_SYS_BASE+0x004) #define DMA_IMR_v *(P_U32)(DMA_SYS_BASE+0x008) #define DMA_BTOSR_v *(P_U32)(DMA_SYS_BASE+0x00C) #define DMA_RTOSR_v *(P_U32)(DMA_SYS_BASE+0x010) #define DMA_TESR_v *(P_U32)(DMA_SYS_BASE+0x014) #define DMA_BOSR_v *(P_U32)(DMA_SYS_BASE+0x018) #define DMA_BTOCR_v *(P_U32)(DMA_SYS_BASE+0x01C) #define DMA_SAR1_v *(P_U32)(DMA_CH1_BASE+0x000) #define DMA_DAR1_v *(P_U32)(DMA_CH1_BASE+0x004) #define DMA_CNTR1_v *(P_U32)(DMA_CH1_BASE+0x008) #define DMA_CCR1_v *(P_U32)(DMA_CH1_BASE+0x00C) #define DMA_RSSR1_v *(P_U32)(DMA_CH1_BASE+0x010) #define DMA_BLR1_v *(P_U32)(DMA_CH1_BASE+0x014) #define DMA_RTOR1_v *(P_U32)(DMA_CH1_BASE+0x018) #define DMA_BUCR1_v *(P_U32)(DMA_CH1_BASE+0x018) // #define DMA_SAR2_v *(P_U32)(DMA_CH2_BASE+0x000) #define DMA_DAR2_v *(P_U32)(DMA_CH2_BASE+0x004) #define DMA_CNTR2_v *(P_U32)(DMA_CH2_BASE+0x008) #define DMA_CCR2_v *(P_U32)(DMA_CH2_BASE+0x00C) #define DMA_RSSR2_v *(P_U32)(DMA_CH2_BASE+0x010) #define DMA_BLR2_v *(P_U32)(DMA_CH2_BASE+0x014) #define DMA_RTOR2_v *(P_U32)(DMA_CH2_BASE+0x018) #define DMA_BUCR2_v *(P_U32)(DMA_CH2_BASE+0x018) // PLL and Clock Control Module #define PCDR *(P_U32)(0x0021B020) // Peripheral Clock Divider Register #define CSCR *(P_U32)(0x0021B000) // Peripheral Clock Divider Register // System Control #define GPCR *(P_U32)(0x0021B80C) // Global Peripheral Control Register #define FMCR *(P_U32)(0x0021B808) // spi2 mux reg // set the base address of the AITC module #define AITC_BASE_ADDRESS 0x223000 #define I_INTENABLEH *(P_U32)(AITC_INTENABLEH) #define I_INTTYPEH *(P_U32)(AITC_INTTYPEH) #define I_INTSRCH *(P_U32)(AITC_INTSRCH) #define I_NIPNDH *(P_U32)(AITC_NIPNDH) #define Table0 0x12300000 #define Table1 0x12300100 // interrupt subroutines extern void SetIntType(U32 IntNum, U8 type); extern void EnableIntSource(U32 IntNum); extern int EnableIRQ(void); extern void CSPI1_ISR(void); // CSPI1_ISR (41) extern void CSPI2_ISR(void); // CSPI2_ISR (40) // normal subroutines //#define Monitor 1; int CSPI_reg_test(void); int CSPI_reg_rw(U32 addr, U16 data, U16 expect); void CSPI_Tx_Fill(int spi, U16 size, U16 data_seed); int CSPI_Rx_Comp(int spi, U16 size, U16 data_seed, U16 bit_count); void CSPI_DMA_configure (int channel, U32 Source, U32 Destination, U8 Port, U16 Busrt, U16 Size, U32 Control); void CSPI_FILL_RAM(U32 address, U16 size, U16 data_seed); int CSPI_CMP_RAM(U32 address, U16 size, U16 data_seed, U16 bit_count); int CSPI_DMA_TEST(void); int CSPI_INT_TEST(void); int CSPI_RxFIFO_Overflow(void); int CSPI_TwoBoard_SPI1_to_SPI1_Master(void); int CSPI_TwoBoard_SPI1_to_SPI1_Master_1(void); int CSPI_TwoBoard_SPI1_to_SPI1_Master_2(void); int CSPI_TwoBoard_SPI2_to_SPI1_Master (void); int CSPI_TwoBoard_SPI1_to_SPI1_Slave (void); int CSPI_TwoBoard_SPI1_to_SPI1_Slave_1 (void); int CSPI_TwoBoard_SPI1_to_SPI1_Slave_2 (void); int CSPI_TwoBoard_SPI2_to_SPI1_Slave(void); int CSPI_reg_reset(U32 addr, U16 expect); int CSPI_Oneboard_SPI2_to_SPI1(void); void CSPI_GPIO_configure(int mode); #endif