/*******************************************************
//
//	Silicon Validation testing Program for Tahiti-Lite
//		PULSE-WIDTH MODULATOR (CSPI)
//
//	Written by Shark Wu
//
//	8 May,2003
//
********************************************************/

// ------------
// 	header
// ------------
#include "cspi_related.h"

/********************************* Constants *********************************/
#define DEFAULT_PRESCALAR		0x03
#define DEFAULT_SAMPLE			0x0040
#define DEFAULT_PERIOD			0x00FE
#define MIN_TEST_PERIOD			0x0000
#define MAX_TEST_PERIOD			0xFFFF

/******************************* Global Data *********************************/
uint32_t cspi_swap_test_data[]	=	{0x00010203,0x04050607,0x08090A0B,0x0C0D0E0F};

uint32_t cspi_sample_test_data[]	=	{0x000F000F,0x001E001E,0x002D002D,0x003C003C,
									 0x004B004B,0x005A005A,0x00690069,0x00780078,
									 0x00870087,0x00960096,0x00A500A5,0x00B400B4,
									 0x00C300C3,0x00D200D2,0x00E100E1,0x00F000F0};

uint32_t cspi_period_test_data[] =	{0x0000,0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,
									 0x007F,0x00C0,0x0102,0x0214,0x0384,0x0668,0x0800,0x0A04,
									 0x1234,0x2538,0x2898,0x3672,0x3895,0x4792,0x5678,0x7254,
									 0x8135,0x9347,0xA2B3,0xC4D5,0xD6B7,0xE2F1,0xFFFE,0xFFFF};

uint32_t cspi_prescalar_test_data[0x10]	=	{0x00,0x01,0x02,0x04,0x08,0x13,0x25,0x36,
									 		 0x47,0x59,0x6a,0x7B,0x7c,0x7d,0x7E,0x7f};

uint16_t cspi_repeat_test_data[]   =	{0x00010001,0x00020002,0x00030003,0x00040004};

int32_t gSampleTestDataCount;

//extern int32_t gNormInt23flag;
int32_t gNormInt23flag;

// ***********************************************
// ****	Main test Program for CSPI module test ****
// ***********************************************

void cspi_test_main(void)
{
	uint32_t i,result;

	// init port
	cspi_port_init();

	for (i=0; i<0x1; i++)	{

		// Power on reset status test
		result = cspi_reset_status_test();
		debugprintf("cspi_reset_status_test result:\t\t\t%x errors", result);
		
		// Register read/write test
		result = cspi_register_read_write_test();
		debugprintf("cspi_register_read_write_test result:\t\t\t%x errors", result);

		// CSPIEN (enable) test
		result = cspi_enable_test();
		debugprintf("cspi_enable_test result:\t\t\t%x errors", result);

		// software reset test
		result = cspi_soft_reset_test();
		debugprintf("cspi_soft_reset_test result:\t\t\t%x errors", result);
			
	    // Swaping bits test
	    result = cspi_swap_test();
		debugprintf("cspi_swap_test result:\t\t\t%x errors", result);

		// FIFO AVAIL test
		result = cspi_fifoav_test();
		debugprintf("cspi_fifoav_test result:\t\t\t%x errors", result);
		
		// REPEAT bit test
		result = cspi_repeat_bit_test();
		debugprintf("cspi_repeat_bit_test result:\t\t\t%x errors", result);

		// CLKSEL test
		result = cspi_clksel_test();
		debugprintf("cspi_clksel_test result:\t\t\t%x errors", result);

		// PRESCALER test
		result = cspi_prescalar_test();
		debugprintf("cspi_prescalar_test result:\t\t\t%x errors", result);
		
		// CLKSRC test
		result = cspi_clksrc_test();
		debugprintf("cspi_clksrc_test result:\t\t\t%x errors", result);
		
		// COUNT test
		result = cspi_count_test();
		debugprintf("cspi_count_test result:\t\t\t%x errors", result);
/*
		// CSPI IRQ test
		result = cspi_irq_test();
		debugprintf("cspi_irq_test result:\t\t\t%x errors", result);
*/
		}

}


// ********************************************************************
// ********************************************************************
// ** Some basic function and routine **
// ********************************************************************
// ********************************************************************

// ********************************************************************
// read register value for input address
// ********************************************************************
uint32_t _register_read(p_uint32_t addr)
{
	return( * ((p_uint32_t) addr) );
}

// ********************************************************************
// write register value into a specified address
// ********************************************************************
void _register_write(p_uint32_t addr, uint32_t value)
{
	 *((p_uint32_t) addr) = value;
}

// ********************************************************************
// set a specified register bit value for a input address
// ********************************************************************
void _set_register_bit(p_uint32_t addr, uint32_t Nbit)
{
	uint32_t temp;
	temp = * (p_uint32_t) addr;
	temp = temp | (0x00000001 << Nbit);
	_register_write( (p_uint32_t) addr, (uint32_t) temp);
}

// ********************************************************************
// clear a specified register bit value for a input address
// ********************************************************************
void _clear_register_bit(p_uint32_t addr, uint32_t Nbit)
{
	uint32_t temp;
	temp = * (p_uint32_t) addr;
	temp = temp & ( ~(0x00000001 << Nbit));
	_register_write( (p_uint32_t) addr, temp);
}

// ********************************************************************
// delay for a while
// ********************************************************************
void delay(uint32_t delay_time)
{
	uint32_t i=0;
	for (i=0; i<delay_time; i++);
}

// ********************************************************************
// Port enable for CSPIO signals
// ********************************************************************
void cspi_port_init(void)
{

	//	PE5 is for CSPIO
	* (uint32_t *) GPIOE_DDIR |=  0x00000020;
	* (uint32_t *) GPIOE_GIUS &= ~0x00000020;

}

// ********************************************************************
// CSPI software reset
// ********************************************************************
void cspi_soft_reset(void)
{
	uint32_t	tmp_value;
	
	// Enable CSPI
	cspi_enable();

	// set SWR bit to 1
	_set_register_bit((p_uint32_t)CSPI_CSPIC, 16);

	//wait for the SWR bit of CSPIC to be 0, means CSPI out of reset
	tmp_value=*(p_uint32_t)CSPI_CSPIC;
	while (tmp_value & 0x00010000)	
		tmp_value=*(p_uint32_t)CSPI_CSPIC;

}

// ********************************************************************
// cspi_enable: enable CSPI counter 
// ********************************************************************
void cspi_enable(void)
{
	// enable CSPI counter by set enable bit (EN =1)
	_set_register_bit((p_uint32_t)CSPI_CSPIC, 4);	
	
}

// ********************************************************************
// cspi_disable: disable CSPI counter 
// ********************************************************************
void cspi_disable(void)
{
	// disable CSPI counter by clear enable bit (EN =0)
	_clear_register_bit((p_uint32_t)CSPI_CSPIC, 4);	
	
}

// ********************************************************************
// cspi_default_setting: set PRESCALAR/CSPIP/CSPIS to default test value
// ********************************************************************
void cspi_default_setting(void)
{
	// set CSPI_CSPIC PRESCALAR to default test value
	*((p_uint32_t)CSPI_CSPIC) |= DEFAULT_PRESCALAR<<8;	

	// set period to default test value
	_register_write((p_uint32_t)CSPI_CSPIP,DEFAULT_PERIOD);

	// set sample to default test value 	
	_register_write((p_uint32_t)CSPI_CSPIS,DEFAULT_SAMPLE);
		
}

// ********************************************************************
// CSPI_init: reset CSPI, and set PRESCALAR/CSPIP to default test value, then enable CSPI
// ********************************************************************
void cspi_init(void)
{

	//CSPI software reset
	cspi_soft_reset();
	
	// set CSPI_CSPIC PRESCALAR to default test value
	*((p_uint32_t)CSPI_CSPIC) |= DEFAULT_PRESCALAR<<8;	

	// set period to default test value
	_register_write((uint32_t*)CSPI_CSPIP,DEFAULT_PERIOD);

	// enable CSPI counter by setting enable bit (EN =1)
	_set_register_bit((uint32_t*)CSPI_CSPIC, 4);
	
}


// ***************************************************************************
//	FUNCTION NAME : cspi_register_read_test (void)
// ***************************************************************************
//	Register Tested:
//	Register Name 		Register Address	Default value/Reset value
// -------------------------------------------------------------------
//  CSPI_CSPIC				0x10006000			0x000000A0
//  CSPI_CSPIS 				0x10006004			0x00000000
//  CSPI_CSPIP  				0x10006008			0x0000FFFE
//  CSPI_CSPICNT				0x1000600c			0x00000000
// ***************************************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***************************************************************************
//  How to test:
//  - execute the program / function after cold/warm/soft reswet
//  - error will remain 0 if no error occurs
// ***************************************************************************
//  Description:
//  Read register value and verify with the expected value
// ***************************************************************************

uint32_t cspi_reset_status_test()
{
	// error is the number of errors occuried in this function 
	// if the read value is not equal to the expected/reset value
	// error will increment by 1uint32_t

	uint32_t value, error = 0;

	value = _register_read((p_uint32_t)CSPI_CSPIC);
	if (value != 0x00000020)
	error ++;

	value = _register_read((p_uint32_t)CSPI_CSPIS);
	if (value != 0x00000000)
		error++;		


	value = _register_read((p_uint32_t)CSPI_CSPIP);
	if (value != 0x0000FFFE)
		error++;

	value = _register_read((p_uint32_t)CSPI_CSPICNT);
	if (value != 0x00000000)
		error++;
	
	return(error);
}


// ********************************************************************
// FUNCTION NAME : cspi_register_read_write_test(void)
// ********************************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// -------------------------------------------------------------------
//  CSPI_CSPIC				0x10006000		PRESCALAR	8~14
//  CSPI_CSPIS 				0x10006004					all
//  CSPI_CSPIP  				0x10006008					all
// ********************************************************************
// Hardware Setup:
// -  Tahiti-Lite EVB
// ********************************************************************
// How to test:
// - execute the program / function
// - error will remain 0 if no error occurs
// ********************************************************************
// Description:
// -  Write all the test data to the registers
// -  Read the data from the registers and verify
// -  Other bits R/W test is included in seperate bit function test	
// ********************************************************************

uint32_t cspi_register_read_write_test(void)
{
	uint32_t index,temp_value,error = 0 ;

	//CSPI software reset
	cspi_soft_reset();

	// -----------------------
	// CSPI_CSPIC PRESCALAR read/ write test
	// -----------------------

	// bit set test
	for (index = 0; index < 7; index++)	{
		_set_register_bit((p_uint32_t)CSPI_CSPIC, (index+8));
		if ( ( *(p_uint32_t)CSPI_CSPIC  & 0x7f00) != ( 0x0001 << (index+8) ) ) 
			error ++;
		_clear_register_bit((p_uint32_t)CSPI_CSPIC, (index+8));
		}

	// all value r/w test
	for (index = 0; index <= 0x7f; index++)	{
		temp_value=*((p_uint32_t)CSPI_CSPIC) & 0xFFFF80FF;		// clear PRESCALAR bits to 0;
		*((p_uint32_t)CSPI_CSPIC) = temp_value | (index<<8);		// set PRESCALAR bits to index;
		if ( (*((p_uint32_t)CSPI_CSPIC) & 0x7f00) != (index<<8)) 
			error ++;
		}
	
	// -----------------------
	// CSPI_CSPIS read/ write test
	// -----------------------
	// bit set test
	for (index = 0; index < 16; index++)	{				// set CSPI_CSPIS index bit to 1;
		_set_register_bit((p_uint32_t)CSPI_CSPIS, index);
		if ( (*(p_uint32_t)CSPI_CSPIS) != ( 0x0001 << index) ) 
			error ++;
		_clear_register_bit((p_uint32_t)CSPI_CSPIS, index);
		}
	
	// all value r/w test
	for (index = 0; index <= 0xffff; index++)	{
		*((p_uint32_t)CSPI_CSPIS) = index;					
		if ( ( *(p_uint32_t)CSPI_CSPIS) != index) 
			error ++;
		}

	
	// -----------------------
	// CSPI_CSPIP read/ write test
	// -----------------------
	
	// bit set test
	*((p_uint32_t)CSPI_CSPIP) = 0;					// set CSPI_CSPIP index bit to 1;
	for (index = 0; index < 16; index++)	{
		_set_register_bit((p_uint32_t)CSPI_CSPIP, index);
		if ( (*(p_uint32_t)CSPI_CSPIP) != ( 0x0001 << index) ) 
			error ++;
		_clear_register_bit((p_uint32_t)CSPI_CSPIP, index);
		}
	
	// all value r/w test
	for (index = 0; index <= 0xffff; index++)	{
		*((p_uint32_t)CSPI_CSPIP) = index;					
		if ( ( *(p_uint32_t)CSPI_CSPIP) != index) 
			error ++;
		}

	return(error);
}

// *********************************************************
// FUNCTION NAME : cspi_enable_test(void)
// *********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// ---------------------------------------------------------
//  CSPI_CSPIC				0x10006000		EN			4
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***********************************************************
// How to test :
//  - execute the program / function
//  - error will remain 0 if no error occurs
// *********************************************************************************************
// Description:
// 1. software reset 
// 2. write a sample to the CSPI_CSPIS
// 3. check whether th counter value remain 0, and CSPIO remain low
// 4. set EN, the counter value should begin to change, and CSPIO have ecpected waveform
// 5. clear the EN bit, check whether th counter value remain 0, and CSPIO remain low
// *********************************************************************************************

uint32_t cspi_enable_test(void)
{
	uint32_t cspip_value,prescalar_value;
	uint32_t i,error = 0;

	//CSPI software reset
	cspi_soft_reset();

	//cspi_default_setting: set PRESCALAR/CSPIP/CSPIS to default test value
	cspi_default_setting();
	
	// ##################################################################################
	//	CSPI has not enabled
	//	Use Oscilloscope to watch the waveform of CSPIO, it should remain low 
	// ##################################################################################
	for	(i=0; i<0x1000; i++)	{
		 delay(0x100);
		 if (*(p_uint32_t)CSPI_CSPICNT) 	error++;	// CSPI_CSPICNT should remain 0
		 }	

	// enable CSPI counter by setting enable bit (EN =1)
	cspi_enable();
	//cspi_default_setting: set PRESCALAR/CSPIP/CSPIS to default test value
	cspi_default_setting();
	// check whether the EN bit is set
	if ( (_register_read((p_uint32_t)CSPI_CSPIC) & 0x00000010 ) != 0x00000010)
		error++;

	for	(i=0; i<=(DEFAULT_PERIOD+1); i++)
		while ( *(p_uint32_t)CSPI_CSPICNT != i ) ;
	// The value of CSPI_CSPIPCNT should repeatly count from 0 to DEFAULT_PERIOD+1 	

	// ##################################################################################
	//	Now use Oscilloscope to watch the waveform of CSPIO, it should have a waveform
	//  with 1/(2*(DEFAULT_PRESCALAR+1)*(DEFAULT_PERIOD+2)) frequency of ipg-clk-perclk,
	//  and its duty cycle is DEFAULT_SAMPLE/(DEFAULT_PERIOD+2). 
	// ##################################################################################

	// disable by clear enable bit (EN =0)
	cspi_disable();
	// check whether the EN bit is clear
	if ( (_register_read((p_uint32_t)CSPI_CSPIC) & 0x00000010 ) != 0x00000000)
		error++;

	for	(i=0; i<0x1000; i++)	{
		 delay(0x100);
		 if (*(p_uint32_t)CSPI_CSPICNT) 	error++;	// CSPI_CSPICNT should remain 0
		 }	

	// ##################################################################################
	//	After CSPI is disabled
	//	Use Oscilloscope to watch the waveform of CSPIO, it should remain low 
	// ##################################################################################
 
	return(error);
}

// ***********************************************************
// FUNCTION : cspi_soft_reset_test
// ***********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// ---------------------------------------------------------
//  CSPI_CSPIC				0x10006000		SWR			16
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***********************************************************
// How to test :
//  - execute the program / function
//  - error will remain 0 if no error occurs
// ***********************************************************
// Description:
//	1. initalize CSPI, put it to work
//  2. soft reset CSPI, verify the reset procedure 
//  3. then check whether all status have been reset
// ***********************************************************

uint32_t cspi_soft_reset_test(void)
{
	uint32_t i,error = 0;

	// CSPI_init: reset CSPI, and set PRESCALAR/CSPIP to default test value, then enable CSPI
	cspi_init();
	
	// set sample to default test value	
	_register_write((p_uint32_t)CSPI_CSPIS,DEFAULT_SAMPLE);

	// Just to read back the value of CSPI_CSPIPCNT, it should repeatly change in [0,(DEFAULT_PERIOD+1] 	
	for	(i=0; i<(DEFAULT_PERIOD+1); i++) 
		while( _register_read((p_uint32_t)CSPI_CSPICNT)  != i );

	//	############################################################################################
	//	Now if we use a oscilloscope to watch the waveform of CSPIO, its frequency
	//  should equal to 1/(DEFAULT_PERIOD+2) of ipg_clk-perclk, and its duty cycle
	// 	should be DEFAULT_SAMPLE/(2*(DEFAULT_PRESCALAR+1)(DEFAULT_PERIOD+2)). 
	//	############################################################################################

	// set SWR bit to 1 to soft reset CSPI
	_set_register_bit((p_uint32_t)CSPI_CSPIC, 16);

/*
	// immediately read back SWR bit, it should be 1 for a while
	if ( (_register_read((p_uint32_t)CSPI_CSPIC) & 0x00010000 ) != 0x00010000)
		error++;
*/	
	// delay enough time for CSPI to out of reset 
	delay(0x10000);
	
	// now SWR bit should be 0, means CSPI out of reset
	if ( (_register_read((p_uint32_t)CSPI_CSPIC) & 0x00010000 ) == 0x00010000)
		error++;

	//	############################################################################################
	//	Now if we use a oscilloscope to watch the waveform of CSPIO, it should remain low 
	//	############################################################################################

	// To check whether CSPI is in after-reset status
	error += cspi_reset_status_test ();
	
	return (error);
}

// *********************************************************
// FUNCTION NAME : cspi_swap_test(void)
// *********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// ---------------------------------------------------------
//  CSPI_CSPIC				0x10006000		HCTR,BCTR	18,17
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***********************************************************
// How to test :
//  - execute the program / function
//  - error will remain 0 if no error occurs
// ***********************************************************
// Description:
// 1. software reset 
// 2. set 00, 01, 10, 11 for different case 
// 3. write some sample data to CSPI_CSPIS, read back the CSPI_CSPIS, 
//	  compare it with the expected value.	
// 4. then enable CSPI and watch the CSPIO,
//    its duty cycle should be expected_value/0x10000  
// ***********************************************************

uint32_t cspi_swap_test(void)
{
    uint32_t i,j,temp_value,expected_CSPIS_value,expected_FIFO_value,error=0;
	uint8_t	index,TestDataNum;	
     
	TestDataNum = sizeof(cspi_swap_test_data) / sizeof(uint32_t);

 	for (i=0; i<=3; i++)	{ // 00,01,10,11 -> HCTR,BCTR 	
	  			
		//CSPI software reset
    	cspi_soft_reset();

		// set CSPI_CSPIP to max test value, not necessary due to soft reset value is 0xFFFE
		// *((p_uint32_t)CSPI_CSPIP) =0xFFFE;	

		// make sure that HCTR/BCTR bits are reset
		if ( _register_read((p_uint32_t)CSPI_CSPIC) & 0x00060000 )
			error ++;

		// set HCTR/BCTR = i
		temp_value=( _register_read((p_uint32_t)CSPI_CSPIC) & ~0x00060000) | (i<<17);
		_register_write((p_uint32_t)CSPI_CSPIC, temp_value);

		// test the write result
		temp_value=( _register_read((p_uint32_t)CSPI_CSPIC) & 0x00060000) >> 17;
		if ( temp_value != i )
			error ++;

		for (index=0; index<TestDataNum; index++)	{
	
	   		cspi_enable();
			// set sample to test value 	
		    _register_write((p_uint32_t)CSPI_CSPIS, cspi_swap_test_data[index]);

			switch (i)	{

				case 0:
						expected_CSPIS_value = cspi_swap_test_data[index] & 0xffff;
						expected_FIFO_value = expected_CSPIS_value;
						break;
				case 1:
						expected_CSPIS_value = cspi_swap_test_data[index] & 0xffff;
						expected_FIFO_value = ((expected_CSPIS_value & 0x00ff) << 8 ) | ( (expected_CSPIS_value & 0xff00) >> 8);
						break;
				case 2:
						expected_CSPIS_value = (cspi_swap_test_data[index] & 0xffff0000) >> 16;
						expected_FIFO_value = expected_CSPIS_value;
						break;
				case 3:
						expected_CSPIS_value = (cspi_swap_test_data[index] & 0xffff0000) >> 16;
						expected_FIFO_value = ((expected_CSPIS_value & 0x00ff) << 8 ) | ( (expected_CSPIS_value & 0xff00) >> 8);
						break;
				}
					
			temp_value= _register_read((p_uint32_t)CSPI_CSPIS);
			if ( temp_value !=expected_CSPIS_value )
				error ++;

			delay(0x1000);			
/*
			// Just to read back the value of CSPI_CSPIPCNT, it should repeatly change in [0,0xffff] 	
			for	(j=0; j<0x10000; j++) 
				while( _register_read((p_uint32_t)CSPI_CSPICNT)  != j );
*/
    		// ###########################################################################
			// Now use Oscilloscope to watch the waveform of CSPIO, 
			// it should have a waveform with 1/(2*0x10000) frequency of ipg_clk_perclk,
			// and its duty cycle should be expected_FIFO_value/0x10000  
			// ###########################################################################
			cspi_disable();

			}

		//CSPI software reset
    	cspi_soft_reset();

		// make sure that HCTR/BCTR bits are reset
		if ( _register_read((p_uint32_t)CSPI_CSPIC) & 0x00060000 )
			error ++;

		}
	
	return (error);

}
    

// *********************************************************
// FUNCTION NAME : cspi_fifo_available_test(void)
// *********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// ---------------------------------------------------------
//  CSPI_CSPIC				0x10006000		FIFOAV		5
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***********************************************************************************************************
// Description:
//	To test FIFOAV when EN=0
// 1. software reset
// 2. write no less than 4 data CSPI_CSPIS, check the FIFOAV value, 
//    then reset CSPI and check whether FIFOAV is reset 
// 3. write 4 data to CSPI_CSPIS, check the FIFOAV value after each write, 
// 4. then write one mor edata to CSPI_CSPIS, to check whether it is ignored
// 5. enable CSPI, continously write more sample data to CSPI_CSPIS, and 
//	  check the FIFOAV value after each write. 
// 6. watch the waveform of CSPIO
//
//	To test FIFOAV when EN=1
// 1. software reset, enable CSPI
// 2. write no less than 4 data CSPI_CSPIS, check the FIFOAV value, 
//    then reset CSPI and check whether FIFOAV is reset 
// 3. software reset, enable CSPI
// 4. write 4 data to CSPI_CSPIS, check the FIFOAV value after each write, 
// 5. then write one mor edata to CSPI_CSPIS, to check whether it is ignored
// 6. continously write more sample data to CSPI_CSPIS, and 
//	  check the FIFOAV value after each write. 
// 7. watch the waveform of CSPIO
// ***********************************************************************************************************

uint32_t cspi_fifoav_test(void)
{
	uint32_t  error = 0;	
	uint8_t	 index,TestDataNum,cspi_fifo_available;	
	   
	TestDataNum = sizeof(cspi_sample_test_data) / sizeof(uint32_t);

	// ********************************************************************
	// ** At first, test whether FIFOAV is always set when EN is not set **	
	// ********************************************************************
	// CSPI software reset
	cspi_soft_reset ();	
	//write four data into FIFO to make FIFOAV is clear
	for (index=0; index<4; index++ ){	
		* (p_uint32_t)CSPI_CSPIS = cspi_sample_test_data[index];
		}

	// After the fourth data is written into CSPI_CSPIS, FIFIAV should still be 1
	cspi_fifo_available = _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020;
	if ( !cspi_fifo_available )	error++;

	// **********************************************************
	// ** Then test whether FIFOAV can be reset when EN is set **
	// **********************************************************
	cspi_enable();
	
	//write four data into FIFO to make FIFOAV is clear
	for (index=0; index<4; index++ ){	
		* (p_uint32_t)CSPI_CSPIS = cspi_sample_test_data[index];
		}

	// After the fourth data is written into CSPI_CSPIS, FIFIAV should be zero
	cspi_fifo_available = _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020;
	if ( cspi_fifo_available )	error++;

	// CSPI software reset
	cspi_soft_reset ();	

	// After reset, FIFIAV should be 1
	cspi_fifo_available = _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020;
	if ( !cspi_fifo_available )	error++;

	// ************************************
	// ** Test the FIFOAV when EN is set **
	// ************************************

	cspi_enable();

	// set CSPI_CSPIC PRESCALAR to default test value
	*((p_uint32_t)CSPI_CSPIC) |= DEFAULT_PRESCALAR<<8;	

	// set CSPI_CSPIP to default test value
	*((p_uint32_t)CSPI_CSPIP) |= DEFAULT_PERIOD;			

	// #################################################################
	// ## Now set a breakpoint and use a LA to start capture the CSPIO ##
	// #################################################################

	for (index=0; index<4; index++ ){	//write four data into FIFO when EN is not set
		// check if FIFOAV bit (bit 4) is set before write
		cspi_fifo_available = _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020;
		if ( !cspi_fifo_available )	error++;
		// Continuously write sample data into CSPI_CSPIS
		* (p_uint32_t)CSPI_CSPIS = cspi_sample_test_data[index];
		}

	// After the fourth data are written into CSPI_CSPIS, FIFIAV should be zero
	cspi_fifo_available = _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020;
	if ( cspi_fifo_available )	error++;

	// write one more sample 
	// to test whether write to FIFO is ignored if FIFOAV bit is cleared
	*(p_uint32_t)CSPI_CSPIS = cspi_sample_test_data[index++];

	// check to see if the FIFOAV is still cleared
	cspi_fifo_available = _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020;
	if ( cspi_fifo_available )	error++;

	//write more data into FIFO to test
	for ( ; index<TestDataNum; index++ ){	
			// wait untill FIFOAV is set
			while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
			_register_write ((uint32_t*)CSPI_CSPIS, cspi_sample_test_data[index]);
			// check to see if the FIFOAV is cleared by the write
			cspi_fifo_available = _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020;
			if ( cspi_fifo_available )	error++;
		}

	// ###########################################################################
	// Now use Oscilloscope to watch the waveform of CSPIO, 
	// each data cspi_repeat_test_data[index] should have a waveform with 
	// 1/(2*(DEFAULT_PRESCALAR+1)(DEFAULT_PERIOD+2)) frequency of ipg_clk_perclk,
	// and its duty cycle is cspi_sample_test_data/(DEFAULT_PERIOD+2), 
	// engineer should noticed taht cspi_sample_test_data[4] is ignored.
	// ###########################################################################
			
	// ######################################################################
	// Delay enough time to let all the data written into FIFO have been used
	// Set a breakpoint here and use a LA to finished capture all the CSPIO
	// ######################################################################
	delay(0x10000);

	return (error);
}


// *********************************************************
// FUNCTION NAME : cspi_repeat_bit_test(void)
// *********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// ---------------------------------------------------------
//  CSPI_CSPIC				0x10006000		REPEAT		2,3
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***********************************************************
// Description:
// 1. software reset 
// 2. set 00, 01, 10, 11 for different case 
// 3. write some sample data to CSPI_CSPIS,
// 4. Use a oscilloscope to watch CSPIO, each sample data will 
//	  be used REPEAT times to generate the CSPIO waveform
// ***********************************************************

uint32_t cspi_repeat_bit_test(void)
{
    uint32_t temp_value,error = 0;
	uint8_t	i,index,TestDataNum;	
    
	TestDataNum = sizeof(cspi_repeat_test_data) / sizeof(uint32_t);

	// soft reset CSPI
    cspi_soft_reset();
  
 	for (i=0; i<=3; i++)	{ // 00,01,10,11 -> REPEAT 	
	  			
		temp_value= (*(p_uint32_t)CSPI_CSPIC) & ~0x00000000C | (i<<0x2);
		_register_write((p_uint32_t)CSPI_CSPIC,temp_value);
		if ( (_register_read((p_uint32_t)CSPI_CSPIC) & 0x00000000C) != (i<<0x2) )
			error++;

		// set CSPI_CSPIC PRESCALAR to default test value
		*((p_uint32_t)CSPI_CSPIC) |= DEFAULT_PRESCALAR<<8;	// set PRESCALAR bits to pre-defined value;

		// set CSPI_CSPIP to default test value
		*((p_uint32_t)CSPI_CSPIP) = DEFAULT_PERIOD;			// set PRESCALAR bits to pre-defined value;

	   	cspi_enable();

		// continously write data of cspi_repeat_test_data to CSPI_CSPIS FIFO	
		for (index=0; index<TestDataNum; index++)	{
			// wait untill FIFOAV is set
			while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
			_register_write ((uint32_t*)CSPI_CSPIS, cspi_repeat_test_data[index]);
			}
		// ###########################################################################
		// Now use Oscilloscope to watch the waveform of CSPIO, 
		// each data cspi_repeat_test_data[index] should have i waveform with 
		// 1/(2*(DEFAULT_PRESCALAR+1)(DEFAULT_PERIOD+2)) frequency of ipg_clk_perclk,
		// and its duty cycle is cspi_repeat_test_data/(DEFAULT_PERIOD+2)
		// ###########################################################################
			
		//delay enough time to let all the data written into FIFO have been used
		delay(0x10000);

    	// the REPEAT bits should be cleared after soft reset
    	cspi_soft_reset();
		if ( _register_read((p_uint32_t)CSPI_CSPIC) & 0x00000000C )
			error++;
		}
	
	return (error);

}


// *********************************************************
// FUNCTION NAME : cspi_clksel_test(void)
// *********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// ---------------------------------------------------------
//  CSPI_CSPIC				0x10006000		CLKSEL		0,1
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***********************************************************
// Description:
// 1. software reset, set CSPIP PRESCALAR to default test value 
// 2. set 00, 01, 10, 11 for different case 
// 3. write some sample data to CSPI_CSPIS,
// 4. Use a oscilloscope to watch CSPIO, the frequency should be 
//	  1/((2^i)*(DEFAULT_PERIOD+2)*DEFAULT_PRESCALAR) frequency of ipg_clk_perclk

// 5. repeat step 1~3 with CLKSRC is set to 1
// 6. Use a oscilloscope to watch CSPIO, the frequency should be 
//	  1/((2^j)*(DEFAULT_PERIOD+2)*DEFAULT_PRESCALAR) frequency of ipg_clk32
// ***********************************************************
uint32_t cspi_clksel_test(void)
{
    uint32_t temp_value,error=0;
	uint8_t	i,j,index,TestDataNum;	
    
	TestDataNum = sizeof(cspi_sample_test_data) / sizeof(uint32_t);

	// *************************************************
	// ** Test the CLKSEL when CLKSRC is clear or set **
	// *************************************************
    cspi_soft_reset();
  
	for (i=0; i<=1; i++)	{ 		// test include CLKSRC is set or clear 	
		for (j=0; j<=3; j++)	{ 	// 00,01,10,11 -> CLKSEL 	
			temp_value= ( (*(p_uint32_t)CSPI_CSPIC) & ~0x000000003) | j;
			_register_write((p_uint32_t)CSPI_CSPIC,temp_value);		
			// check the value has been written into CLKSEL bits
			temp_value= ( (*(p_uint32_t)CSPI_CSPIC) & 0x000000003) ;
			if ( temp_value !=j ) error++;

			// set CSPI_CSPIC PRESCALAR to default test value
			*((p_uint32_t)CSPI_CSPIC) |= DEFAULT_PRESCALAR<<8;	// set PRESCALAR bits to pre-defined value;

			// set CSPI_CSPIP to default test value
			*((p_uint32_t)CSPI_CSPIP) = DEFAULT_PERIOD;			// set PRESCALAR bits to pre-defined value;

			// select ipg_clk_perclk by clear CLKSRC bit (CLKSRC =1)
			// select ipg_clk32 by set CLKSRC bit (CLKSRC =1)
			if (i) _set_register_bit((p_uint32_t)CSPI_CSPIC, 15);	
	    	cspi_enable();

			for (index=0; index<TestDataNum; index++)	{
				// wait untill FIFOAV is set
				while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
				// set sample to test value 	
			    _register_write ((uint32_t*)CSPI_CSPIS, cspi_sample_test_data[index]);
				}

			// #####################################################################################
			// To test CLKSRC, set a breakpoint here and capture the CSPIO,the waveform should at  
			// 1/((2^j)*(DEFAULT_PRESCALAR=1)*(DEFAULT_PERIOD+2)) frequency of ipg_clk_perclk or  
			// ipg_clk32, and its duty cycle is cspi_sample_test_data/(DEFAULT_PERIOD+2). 
			// #####################################################################################
				
			//delay enough time to let all the data written into FIFO have been used
			delay(0x10000);

	    	// the CLKSEL bits should be cleared after soft reset
	    	cspi_soft_reset();
			if ( _register_read((p_uint32_t)CSPI_CSPIC) & 0x000000003 )
				error++;
			}

		} 
	return (error);

}


// ***********************************************************
// FUNCTION NAME : cspi_prescaler_test(void)
// ***********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// -----------------------------------------------------------
//  CSPI_CSPIC				0x10006000		PRESCALER	8-14
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// *********************************************************************************************
// Description:
//
// To test PRESCALAR bits in CSPI_CSPIC register: 
// 1. Perform software reset,set CSPI_CSPIP to default test value;
// 2. Set a value to PRESCALAR, then enable CSPI and load some sample test data tp CSPI_CSPIS
// 3. Capture the waveform of CSPIO, it should with 1/(2*(prescalar_value+1)*(DEFAULT_PERIOD+2))
//    frequency of ipg_clk_perclk
// *********************************************************************************************

uint32_t cspi_prescalar_test(void)
{
	uint8_t	sample_index,prescalar_index,SampleDataNum,PrescalarDataNum;	
	uint32_t prescalar_value,temp_value,error =0;
  
	SampleDataNum = sizeof(cspi_sample_test_data) / sizeof(uint32_t);
	PrescalarDataNum = sizeof(cspi_prescalar_test_data) / sizeof(uint32_t);

	// soft reset CSPI
	cspi_soft_reset();

	// all value of PRESCALAR should be test
	// engineer can only use some sample value to do the test	
	for (prescalar_index=0; prescalar_value<PrescalarDataNum; prescalar_index++)	{

		prescalar_value=cspi_prescalar_test_data[prescalar_index];
		temp_value=*((p_uint32_t)CSPI_CSPIC) & 0xFFFF80FF;				// clear PRESCALAR bits to 0;
		*((p_uint32_t)CSPI_CSPIC) = temp_value | (prescalar_value<<8);	// set PRESCALAR bits to i;
	
		// then enable CSPI
		cspi_enable();	

		// set CSPI_CSPIP to default test value
		_register_write((p_uint32_t)CSPI_CSPIP,DEFAULT_PERIOD);

		// to make the test exhausetive, load more data to CSPI_CSPIS 
		for (sample_index=0; sample_index<SampleDataNum; sample_index++)	{
			// wait untill FIFOAV is set
			while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
			// set sample to test value 	
		    _register_write ((p_uint32_t)CSPI_CSPIS, cspi_sample_test_data[sample_index]);

			}

		//delay enough time to let all the data written into FIFO have been used
		 delay(0x10000);	
		// ##########################################################################
		// To test PRESCALAR, set a breakpoint here and capture the CSPIO, it should with 
		// 1/(2*(prescalar_value+1)*(DEFAULT_PERIOD+2)) frequency of ipg_clk_perclk, 
		// and its duty cycle is cspi_sample_test_data/(DEFAULT_PERIOD+2). 
		// ##########################################################################

		}

	return (error);

}


// ***********************************************************
// FUNCTION NAME : cspi_clksrc_test(void)
// ***********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// -----------------------------------------------------------
//  CSPI_CSPIC				0x10006000		CLKSRC		15
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// **********************************************************************
// How to test :
//  1. Soft reset CSPI , and set PRESCALAR/CSPIP/CSPIS to default test value 
//  2. clear CLKSRC, load some sample test data to CSPI_CSPIS,
//	3. Capture the CSPIO,  its waveform should with a frequency equal to 
//     1/(2*(DEFAULT_PRESCALAR+1)*(DEFAULT_PERIOD+2)) of ipg_clk_perclk, 
//     and its duty cycle is cspi_sample_test_data/(DEFAULT_PERIOD+2). 
//
//  4. Soft reset CSPI , and set PRESCALAR/CSPIP/CSPIS to default test value 
//  5. Set CLKSRC, load some sample test data to CSPI_CSPIS,
//	6. Capture the CSPIO,  its waveform should with a frequency equal to 
//     1/(2*(DEFAULT_PRESCALAR+1)*(DEFAULT_PERIOD+2)) of ipg_clk32, 
//     and its duty cycle is cspi_sample_test_data/(DEFAULT_PERIOD+2). 
// ***********************************************************************
uint32_t cspi_clksrc_test(void)
{
	uint8_t	index,TestDataNum;	
	uint32_t error =0;
   
	TestDataNum = sizeof(cspi_sample_test_data) / sizeof(uint32_t);

	// ******************************
	// ** First test the CLKSRC=0  **
	// ******************************
	//CSPI software reset
	cspi_soft_reset();

	// set CSPI_CSPIC PRESCALAR to default test value
	*((p_uint32_t)CSPI_CSPIC) |= DEFAULT_PRESCALAR<<8;	

	// set period to default test value
	_register_write((p_uint32_t)CSPI_CSPIP,DEFAULT_PERIOD);

	// Set CLKSRC to 0, means system clock: ipg_clk_perclk
	_clear_register_bit ((p_uint32_t)CSPI_CSPIC, 15);
	
	// then enable CSPI
	cspi_enable();	

	// to make the test exhausetive, load more data to CSPI_CSPIS 
	for (index=0; index<TestDataNum; index++)	{
		// wait untill FIFOAV is set
		while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
		// set sample to test value 	
	    _register_write ((p_uint32_t)CSPI_CSPIS, cspi_sample_test_data[index]);
		}

	//delay enough time to let all the data written into FIFO have been used
	delay(0x100000);
	// ##########################################################################
	// To test CLKSRC, set a breakpoint here and capture the CSPIO, it should with 
	// 1/(2*(DEFAULT_PRESCALAR+1)*(DEFAULT_PERIOD+2)) frequency of ipg_clk_perclk, 
	// and its duty cycle is cspi_sample_test_data/(DEFAULT_PERIOD+2). 
	// ##########################################################################

	// *****************************
	// ** Then test the CLKSRC=1  **
	// *****************************
	//CSPI software reset
	cspi_soft_reset();

	// set CSPI_CSPIC PRESCALAR to default test value
	*((p_uint32_t)CSPI_CSPIC) |= DEFAULT_PRESCALAR<<8;	

	// set period to default test value
	_register_write((p_uint32_t)CSPI_CSPIP,DEFAULT_PERIOD);

	// Set CLKSRC to 1, means ipg_clk32
	_set_register_bit ((p_uint32_t)CSPI_CSPIC, 15);
	
	// then enable CSPI
	cspi_enable();	
	
	// to make the test exhausetive, load more data to CSPI_CSPIS 
	for (index=0; index<TestDataNum; index++)	{
		// wait untill FIFOAV is set
		while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
		// set sample to test value 	
	    _register_write ((p_uint32_t)CSPI_CSPIS, cspi_sample_test_data[index]);
		}

	//delay enough time to let all the data written into FIFO have been used
	delay(0x1000);
	// ###########################################################################
	// To test CLKSRC, set a breakpoint here and capture the CSPIO, it should with 
	// 1/(2*(DEFAULT_PRESCALAR+1)*(DEFAULT_PERIOD+2)) frequency of ipg_clk32, 
	// and its duty cycle is cspi_sample_test_data/(DEFAULT_PERIOD+2). 
	// ###########################################################################

   	// the CLKSRC bits should be cleared after soft reset
   	cspi_soft_reset();
	if ( _register_read((p_uint32_t)CSPI_CSPIC) & 0x00008000 )
		error++;

	return (error);
		
}


// ***********************************************************
// FUNCTION NAME : cspi_count_test(void)
// ***********************************************************
//	Register Tested:
//	Register Name 		Register Address	
// -----------------------------------------------------------
//  CSPI_CSPIS				0x10006004			
//  CSPI_CSPIP				0x10006008			
//  CSPI_CSPICNT				0x1000600C			
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***********************************************************
// How to test :
//  - execute the program / function
//  - error will remain 0 if no error occurs
// ***********************************************************
// Description:
//
// To test CSPI_CSPIC register: 
// 1. Perform software reset, set EN bit in CSPIC register;
// 2. Set value to CSPIS/CSPIP, repeat check the value in CSPICNT,
//    it should repeat count from 0 count up to (period_value+1).
// 3. Change the value set to CSPIS/CSPIP, repeat the above test.
//
// To test CSPIS/CSPIP register: 
// 1. Perform software reset, set EN bit in CSPIC register;
// 2. Set value to CSPIS/CSPIP, then capture the waveform of CSPIO,
//	  it should with a 1/(period_value+2) frequency of ipg_clk_perclk,
//    and its duty cycle is sample_value/(period_value+2).  
// 3. Change the value set to CSPIS/CSPIP, repeat the above test.
// ***********************************************************
uint32_t cspi_count_test(void)
{
	uint32_t period_value,sample_value,count_value;
	uint32_t error =0;
	uint8_t TestDataNum,index;
	
	TestDataNum = sizeof(cspi_period_test_data) / sizeof(uint32_t);

	// soft reset CSPI
	cspi_soft_reset();

	//########################################################################################
	// Test Engineer need pay attention that
	// To do all the test of period_value/sample_value, it need a very very long time.
	// So he only need to select some value to do the test
	//########################################################################################
	
	for (index=0; index<TestDataNum; index++)	{
		// write  period_value to CSPI_CSPIP	
		period_value=cspi_period_test_data[index];
		_register_write ((p_uint32_t)CSPI_CSPIP, period_value);

		// set CSPI_CSPIC PRESCALAR to default test value
		*((p_uint32_t)CSPI_CSPIC) |= DEFAULT_PRESCALAR<<8;	

		// enable CSPI
		cspi_enable();

		for (sample_value=0; sample_value<=(period_value+2); sample_value++)	{
			// wait untill FIFOAV is set
			while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
			_register_write ((p_uint32_t)CSPI_CSPIS, sample_value);

			// #######################################################################################			
			// To test CSPI_CSPIS and CSPI_CSPIP register, set a breakpoint here and capture the CSPIO, 
			// then check the waveform, it should with 1/(2*(DEFAULT_PRESCALAR+1)*(period_value+2))
			// frequency of ipg_clk_perclk, its duty cycle is sample_value/(period_value+2). 
			// #######################################################################################			

			// Just delay enough time for waveform capture
			delay(0x100);
			
			}

		// #######################################################################################			
		// To test CSPI_CSPICNT register, check whether the value in CSPI_CSPICNT repeatly
		// steps in [0,period_value+1]. 
		// #######################################################################################			
		for (count_value=0; count_value<(period_value+2); count_value++)	
			while ( _register_read ((p_uint32_t)CSPI_CSPICNT) != count_value );

		// Before change the value period, disable the CSPI
		cspi_disable();

		}

	return (error);
}

// *********************************************************
// FUNCTION NAME : cspi_irq_test(void)
// *********************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// ---------------------------------------------------------
//  CSPI_CSPIC				0x10006000		IRQEN,IRQ	6,7
// ***********************************************************
//  Hardware Setup:
//  - Tahiti-Lite EVB
// ***********************************************************

uint32_t cspi_irq_test(void)
{
	uint32_t error = 0;
	uint8_t	i,index=0;

	// enable ARM AITC INTERUPT
	EnableIRQ();
	DisableIntSource(23);	// Disable CSPI int

// ###########################################################################
//	Test IRQEN = 0
// ###########################################################################
	for (i=0; i<2; i++)	{ 

		// First test when CSPI int (23) disabled
		// Then test when CSPI int (23) is enabled
		if (i) EnableIntSource(23);

		gNormInt23flag=0;
		gSampleTestDataCount=0;

		cspi_init();
		// clear IRQEN to 0
		_clear_register_bit((uint32_t*)CSPI_CSPIC, 6);

		// AT first, IRQ bit should be set
		if (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0080))
			error ++;			

		// Write 1st data to FIFO, IRQ bit still be set
	    _register_write((uint32_t*)CSPI_CSPIS, cspi_sample_test_data[gSampleTestDataCount++]);
		if (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0080))
			error ++;			

		// Only after the 4th data write to FIFO, IRQ bit be clear
		while ( _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020 )	{
		    _register_write((uint32_t*)CSPI_CSPIS, cspi_sample_test_data[gSampleTestDataCount++]);
			}

		if ( _register_read((p_uint32_t)CSPI_CSPIC) & 0x0080)
			error ++;			

		// wait untill FIFOAV bit to be set again
		while (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0020) );
		if (gNormInt23flag != 0) error++;

		// wait untill IRQ bit to be set again
		while (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0080) );
		if (gNormInt23flag !=0 ) error++;
		
		}
	
// ###########################################################################
//	Test IRQEN = 1
// ###########################################################################

// ---------------------------------------------------------------------------
//	AT first , CSPI int on AITC is not enabled, just to test the IRQ status and 
// ---------------------------------------------------------------------------
	DisableIntSource(23);	// enable CSPI int
	gNormInt23flag=0;
	gSampleTestDataCount=0;

	cspi_init();
	// set IRQEN to 1
	_set_register_bit((p_uint32_t)CSPI_CSPIC, 6);

	// AT first, IRQ bit should be set
	if (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0080))
		error ++;			
	// Bit 2 in AITC_INTSRCH should also be set 
	if (!(_register_read((p_uint32_t)AITC_INTSRCH) & 0x00000004))
		error ++;			

	// Write 1st data to FIFO, IRQ bit still be set
    _register_write((uint32_t*)CSPI_CSPIS, cspi_sample_test_data[gSampleTestDataCount++]);
	if (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0080))
		error ++;			
	// Bit 2 in AITC_INTSRCH should also be set 
	if (!(_register_read((p_uint32_t)AITC_INTSRCH) & 0x00000004))
		error ++;			

	// Only after the 4th data write to FIFO, IRQ bit be clear
	while ( _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020 )	{
	    _register_write((uint32_t*)CSPI_CSPIS, cspi_sample_test_data[gSampleTestDataCount++]);
		}

	if ( _register_read((p_uint32_t)CSPI_CSPIC) & 0x0080)
		error ++;			
	// Bit 2 in AITC_INTSRCH should also be clear 
	if ( _register_read((p_uint32_t)AITC_INTSRCH) & 0x00000004 )
		error ++;			

	// wait untill FIFOAV bit to be set again
	while (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0020) );
	if (gNormInt23flag != 0) error++;

	// wait untill IRQ bit to be set again
	while (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0080) );
	if (gNormInt23flag !=0 ) error++;

	// Bit 2 in AITC_INTSRCH should also be set 
	if (!(_register_read((p_uint32_t)AITC_INTSRCH) & 0x00000004))
		error ++;			
	
// --------------------------------------------------------------------------------
//	Then CSPI int on AITC is enabled, to test whether the ISR is properly involved
// --------------------------------------------------------------------------------
	cspi_init();
	// enable CSPI int again, and reset the flag and count
	gNormInt23flag=0;
	gSampleTestDataCount=0;
	EnableIntSource(23);	// enable CSPI int

	// set IRQEN to 1
	_set_register_bit((p_uint32_t)CSPI_CSPIC, 6);

	// delay some time, wait for the ISR of CSPI IRQ to involved 
	delay(0x100000);			// delay enough time for all the cspi_sample_test_data to be loaded into FIFO 
	if (gNormInt23flag <= 0) error++;		
	// The value of gNormInt23flag means the time of ISR involved

	// CSPI int (23) is disabled in ISR
	gNormInt23flag=0;
	// wait untill FIFOAV bit to be set
	while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
	if (gNormInt23flag != 0) error++;	

	// wait untill IRQ bit to be set
	while (!(_register_read((p_uint32_t)CSPI_CSPIC) & 0x0080) );
	if (gNormInt23flag != 0) error++;	

	// enable CSPI int again, and reset the flag and count
	gNormInt23flag=0;
	gSampleTestDataCount=0;
	EnableIntSource(23);	

	// delay some time, wait for the ISR of CSPI IRQ to involved 
	delay(0x10000);			// delay enough time for all the cspi_sample_test_data to be loaded into FIFO 
	if (gNormInt23flag <= 0) error++;		
	// The value of gNormInt23flag means the time of ISR involved	

	// CSPI int (23) is disabled in ISR
	gNormInt23flag=0;
	// wait untill FIFOAV bit to be set
	while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020) );
	if (gNormInt23flag != 0) error++;	

	// wait untill IRQ bit to be set
	while (!(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0080) );
	if (gNormInt23flag != 0) error++;	
		
	return(error);
}

// 	###########################################################################
//	# The ISR for CSPI interrupt
// 	###########################################################################

void   cspi_irq_test_isr(void)	// norm_scr23_isr (23)
{
	uint8_t	TestDataNum;	
    
	TestDataNum = sizeof(cspi_sample_test_data) / sizeof(uint32_t);

	// if the isr is not caused by FIFO empty interrupt, set igNormInt23flag=-1 
	if ( !(_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0080 ))
		gNormInt23flag=-1;
	else // set gNormInt23flag to 1 to means cspi irq involved
		gNormInt23flag++;

	// Write all sample test data to FIFO, each time stopped by FIFOAV is cleared, 	
	while ( (_register_read ((p_uint32_t)CSPI_CSPIC) & 0x0020 ) && (gSampleTestDataCount < TestDataNum) )
	    _register_write ((p_uint32_t)CSPI_CSPIS, cspi_sample_test_data[gSampleTestDataCount++]);
	
	// if the IRQ is not clear by writting to FIFO, set igNormInt23flag=-1 
	if ( _register_read ((p_uint32_t)CSPI_CSPIC) & 0x0080 )
		gNormInt23flag=-1;

	// if all cspi_sample_test_data is written, disable CSPI int (23)
	if ( gSampleTestDataCount >= TestDataNum )
	DisableIntSource(23);
}