/*******************************************************
//
//	Silicon Validation testing Program for Tahiti-Lite
//		PULSE-WIDTH MODULATOR (CSPI)
//
//	Written by Shark Wu
//
//	8 May,2003
//
********************************************************/

// ------------
// 	header
// ------------
#include "cspi_related.h"


#define MAX_TEST_DATA_NUM	128
uint32_t master_tx_data[MAX_TEST_DATA_NUM]	=	{
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,

												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,

												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,

												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,

												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,

												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,

												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,

												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4
												};


uint32_t slave_tx_data[MAX_TEST_DATA_NUM]	=	{
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,

												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,

												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,

												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,

												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,

												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,

												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4,

												0xc3c3c3c3,0xd2d2d2d2,0xe1e1e1e1,0xf0f0f0f0,
												0x0f0f0f0f,0x1e1e1e1e,0x2d2d2d2d,0x3c3c3c3c,
												0x4b4b4b4b,0x5a5a5a5a,0x69696969,0x78787878,
												0x87878787,0x96969696,0xa5a5a5a5,0xb4b4b4b4
												};

uint32_t master_rx_data[MAX_TEST_DATA_NUM],slave_rx_data[MAX_TEST_DATA_NUM];

int32_t gIntTestItem;
int32_t gMasterTxDataIndex;
int32_t gMasterRxDataIndex;
int32_t gSlaveTxDataIndex;
int32_t gSlaveRxDataIndex;

// ***********************************************
// ****	Main test Program for CSPI module test ****
// ***********************************************

void cspi_test_main(void)
{
	uint32_t i,result;

	// init port
	cspi_port_init();

	// Enable ipg_clk_perclk for CSPI 1
	_set_register_bit((p_uint32_t)CRM_PCCR0, 4);
	// Enable ipg_clk_perclk for CSPI 2
	_set_register_bit((p_uint32_t)CRM_PCCR0, 5);

	for (i=0; i<0x1; i++)	{

		// Power on reset status test
		result = cspi_reset_status_test();
		debugprintf("\n cspi_reset_status_test result:\t\t\t%x errors", result);
		
		// Register read/write test
		result = cspi_register_read_write_test();
		debugprintf("\n cspi_register_read_write_test result:\t\t%x errors", result);

		// software reset test
		result = cspi_soft_reset_test();
		debugprintf("\n cspi_soft_reset_test result:\t\t\t%x errors", result);

		// FIFO status bit test
		result = cspi_fifo_status_test();
		debugprintf("\n cspi_fifo_status_test result:\t\t%x errors", result);

		// Period Register test
		result = cspi_period_register_test();
		debugprintf("\n cspi_period_register_test result:\t\t%x errors", result);

		// Test Register test
		result = cspi_test_register_test();
		debugprintf("\n cspi_test_register_test result:\t\t%x errors", result);

		// CSPI1 FIFO interrupt test
		result = cspi1_fifo_int_test();
		debugprintf("\n cspi1_fifo_int_test result:\t\t%x errors", result);

		// CSPI2 FIFO interrupt test
		result = cspi2_fifo_int_test();
		debugprintf("\n cspi2_fifo_int_test result:\t\t%x errors", result);

		// Control Register test
		result = cspi_control_register_test();
		debugprintf("\n cspi_control_register_test result:\t\t%x errors", result);
		// DMA test
		result = cspi_DMA_test();
		debugprintf("\n cspi_DMA_test result:\t\t%x errors", result);

		// two CSPIs test
		result = two_cspi_test();
		debugprintf("\n two_cspi_test result:\t\t%x errors", result);

		// two boards test
		result = two_boards_test();
		debugprintf("\n two_boards_test result:\t\t%x errors", result);

	}

}


// ********************************************************************
// ********************************************************************
// ** Some basic function and routine **
// ********************************************************************
// ********************************************************************

// ********************************************************************
// read register value for input address
// ********************************************************************
uint32_t _register_read(p_uint32_t addr)
{
	return( * ((p_uint32_t) addr) );
}

// ********************************************************************
// write register value into a specified address
// ********************************************************************
void _register_write(p_uint32_t addr, uint32_t value)
{
	 *((p_uint32_t) addr) = value;
}

// ********************************************************************
// set a specified register bit value for a input address
// ********************************************************************
void _set_register_bit(p_uint32_t addr, uint32_t Nbit)
{
	uint32_t temp;
	temp = * (p_uint32_t) addr;
	temp = temp | (0x00000001 << Nbit);
	_register_write( (p_uint32_t) addr, (uint32_t) temp);
}

// ********************************************************************
// clear a specified register bit value for a input address
// ********************************************************************
void _clear_register_bit(p_uint32_t addr, uint32_t Nbit)
{
	uint32_t temp;
	temp = * (p_uint32_t) addr;
	temp = temp & ( ~(0x00000001 << Nbit));
	_register_write( (p_uint32_t) addr, temp);
}

// ********************************************************************
// delay for a while
// ********************************************************************
void delay(uint32_t delay_time)
{
	uint32_t i=0;
	for (i=0; i<delay_time; i++);
}


void cspi_port_init(void)
{

	//	PE5 is for PWMO
	* (uint32_t *) GPIOD_GIUS &= ~0xfff80000;

//????	* (uint32_t *) GPIOE_DDIR |=  0x00000000;

//???	* (uint32_t *) GPIOD_GPR &= ~0x00000000;

}

void cspi_enable(void)
{
	// enable CSPI by set enable bit (SPIEN =1)
	_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 10);	
	_set_register_bit((p_uint32_t)SLAVE_CONTROLREG, 10);	

}

void cspi_disable(void)
{
	// disable CSPI by clear enable bit (SPIEN =0)
	_clear_register_bit((p_uint32_t)MASTER_CONTROLREG, 10);	
	_clear_register_bit((p_uint32_t)SLAVE_CONTROLREG, 10);	
}

void cspi_default_setting(void)
{

	_register_write((p_uint32_t)MASTER_CONTROLREG,0x0c1f);
	_register_write((p_uint32_t)SLAVE_CONTROLREG,0x041f);

}

void cspi_init(void)
{
}

// ********************************************************************
// CSPI software reset
// ********************************************************************
void cspi_soft_reset(void)
{
	uint32_t	tmp_value;
	
	// Enable CSPI
	cspi_enable();

	// set SWR bit to 1
	_set_register_bit((p_uint32_t)MASTER_RESETREG, 0);
	_set_register_bit((p_uint32_t)SLAVE_RESETREG, 0);

	//wait for the START bit of MASTER_RESETREG to be 0, means CSPI out of reset
	tmp_value=*(p_uint32_t)MASTER_RESETREG;
	while (tmp_value & 0x00000001)	
		tmp_value=*(p_uint32_t)MASTER_RESETREG;

	//wait for the START bit of SLAVE_RESETREG to be 0, means CSPI out of reset
	tmp_value=*(p_uint32_t)SLAVE_RESETREG;
	while (tmp_value & 0x00000001)	
		tmp_value=*(p_uint32_t)SLAVE_RESETREG;
}



uint32_t cspi_reset_status_test()
{
	// error is the number of errors occuried in this function 
	// if the read value is not equal to the expected/reset value
	// error will increment by 1uint32_t

	uint32_t value, error = 0;

	value = _register_read((p_uint32_t)MASTER_RXDATAREG);
	if (value != 0x00000000)
	error ++;

/*
	value = _register_read((p_uint32_t)MASTER_TXDATAREG);
	if (value != 0x00000000)
	error ++;
*/
	value = _register_read((p_uint32_t)MASTER_CONTROLREG);
	if (value != 0x00000000)
	error ++;

	value = _register_read((p_uint32_t)MASTER_INTREG);
	if (value != 0x00000000)
		error++;		

	value = _register_read((p_uint32_t)MASTER_TESTREG);
	if (value != 0x00000000)
		error++;

	value = _register_read((p_uint32_t)MASTER_PERIODREG);
	if (value != 0x00000000)
		error++;
	value = _register_read((p_uint32_t)MASTER_DMAREG);

	if (value != 0x00000000)
		error++;
	value = _register_read((p_uint32_t)MASTER_RESETREG);
	if (value != 0x00000000)
		error++;
	
	return(error);
}


// ********************************************************************
// FUNCTION NAME : pwm_register_read_write_test(void)
// ********************************************************************
//	Register Tested:
//	Register Name 		Register Address	Bit Name	Bit#
// -------------------------------------------------------------------
//  PWM_PWMC				0x10006000		PRESCALAR	8~14
//  PWM_PWMS 				0x10006004					all
//  PWM_PWMP  				0x10006008					all
// ********************************************************************
// Hardware Setup:
// -  Tahiti-Lite EVB
// ********************************************************************
// How to test:
// - execute the program / function
// - error will remain 0 if no error occurs
// ********************************************************************
// Description:
// -  Write all the test data to the registers
// -  Read the data from the registers and verify
// -  Other bits R/W test is included in seperate bit function test	
// ********************************************************************

uint32_t cspi_register_read_write_test(void)
{
	uint32_t index,error = 0 ;

	//CSPI software reset
	cspi_soft_reset();

	// ---------------------------------
	// MASTER_CONTROLREG read/write test
	// ---------------------------------
	// bit set/clear test
	for (index =0; index <= 8; index++)	{
		_set_register_bit((p_uint32_t)MASTER_CONTROLREG, index);
		if ( ( *(p_uint32_t)MASTER_CONTROLREG  & ( 0x0001 << index )) != ( 0x0001 << index ) ) 
			error ++;

		_clear_register_bit((p_uint32_t)MASTER_CONTROLREG, index);
		if ( ( *(p_uint32_t)MASTER_CONTROLREG  & ( 0x0001 << index )) != 0x00000000  ) 
			error ++;
		}

	// bit set/clear test
	for (index =10; index <= 19; index++)	{
		_set_register_bit((p_uint32_t)MASTER_CONTROLREG, index);
		if ( ( *(p_uint32_t)MASTER_CONTROLREG  & ( 0x0001 << index )) != ( 0x0001 << index ) ) 
			error ++;

		_clear_register_bit((p_uint32_t)MASTER_CONTROLREG, index);
		if ( ( *(p_uint32_t)MASTER_CONTROLREG  & ( 0x0001 << index )) != 0x00000000  ) 
			error ++;
		}

	// ---------------------------------
	// MASTER_INTREG read/write test
	// ---------------------------------

	// bit set/clear test
	for (index =9; index <= 17; index++)	{
		_set_register_bit((p_uint32_t)MASTER_INTREG, index);
		if ( ( *(p_uint32_t)MASTER_INTREG  & ( 0x0001 << index )) != ( 0x0001 << index ) ) 
			error ++;

		_clear_register_bit((p_uint32_t)MASTER_INTREG, index);
		if ( ( *(p_uint32_t)MASTER_INTREG  & ( 0x0001 << index )) != 0x00000000  ) 
			error ++;
		}

	// -----------------------------------
	// MASTER_TESTREG read/write test
	// -----------------------------------

	// bit set/clear test
	for (index = 12; index <= 16; index++)	{
		_set_register_bit((p_uint32_t)MASTER_TESTREG, index);
		if ( ( *(p_uint32_t)MASTER_TESTREG  & ( 0x0001 << index )) != ( 0x0001 << index ) ) 
			error ++;

		_clear_register_bit((p_uint32_t)MASTER_TESTREG, index);
		if ( ( *(p_uint32_t)MASTER_TESTREG  & ( 0x0001 << index )) != 0x00000000  ) 
			error ++;
		}

	// -----------------------------------
	// MASTER_PERIODREG read/write test
	// -----------------------------------

	// bit set/clear test
	for (index = 0; index <= 15; index++)	{
		_set_register_bit((p_uint32_t)MASTER_PERIODREG, index);
		if ( ( *(p_uint32_t)MASTER_PERIODREG  & ( 0x0001 << index )) != ( 0x0001 << index ) ) 
			error ++;

		_clear_register_bit((p_uint32_t)MASTER_PERIODREG, index);
		if ( ( *(p_uint32_t)MASTER_PERIODREG  & ( 0x0001 << index )) != 0x00000000  ) 
			error ++;
		}

	// -----------------------------------
	// MASTER_DMAREG read/write test
	// -----------------------------------

	// bit set/clear test
	for (index = 12; index <= 15; index++)	{
		_set_register_bit((p_uint32_t)MASTER_DMAREG, index);
		if ( ( *(p_uint32_t)MASTER_DMAREG  & ( 0x0001 << index )) != ( 0x0001 << index ) ) 
			error ++;

		_clear_register_bit((p_uint32_t)MASTER_DMAREG, index);
		if ( ( *(p_uint32_t)MASTER_DMAREG  & ( 0x0001 << index )) != 0x00000000  ) 
			error ++;
		}

	
	return(error);
}

uint32_t cspi_soft_reset_test(void)
{
	uint32_t i,error = 0;

	// set SWR bit to 1 to soft reset CSPI
	cspi_soft_reset();

	// To check whether CSPI is in after-reset status
	error += cspi_reset_status_test ();
	
	return (error);
}


uint32_t cspi_control_register_test(void)
{
	uint32_t 	i,j,error = 0, tmpValue,maskValue,TestDataIndex;


	// enable ARM AITC INTERUPT
	EnableIRQ();

	EnableIntSource(16);	// Enable CSPI1 int
	EnableIntSource(15);	// Enable CSPI2 int

	gIntTestItem=10;

	// CS[1:0] test	
	for (i=0; i<=2; i++) {	


		cspi_soft_reset();
		cspi_default_setting();

		tmpValue=(_register_read((p_uint32_t)MASTER_INTREG) & 0x3ffff ) | (i<<18);

		// set LBC bit
		_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

		tmpValue=(_register_read((p_uint32_t)MASTER_INTREG) & 0x3ffff ) | (i<<18);

		// set CS[1:0] to i, using SSi
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0x3ffff ) | (i<<18);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);


		tmpValue=(_register_read((p_uint32_t)MASTER_INTREG) & 0x3ffff ) | (i<<18);

		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set THEN bit and RHEN bit 
		_set_register_bit((p_uint32_t)MASTER_INTREG, 10);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 14);

		//wait for data rx/tx finished
		while ((gMasterTxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}



	// DATA RATE test	
//	for (i=0; i<=0xf; i++) {	
	for (i=0; i<=0x2; i++) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set LBC bit
		_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

		// set DATA RATE bits to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xc3fff ) | (i<<14);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);

		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set THEN bit and RHEN bit 
		_set_register_bit((p_uint32_t)MASTER_INTREG, 10);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 14);

		//wait for data rx/tx finished
		while ((gMasterTxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// DRCTL test
	// AT present , only DRCTL = 0 can be test	
	for (i=0; i<=0; i++) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set LBC bit
		_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

		// set DRCTL to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfcfff ) | (i<<12);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);

		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set THEN bit and RHEN bit 
		_set_register_bit((p_uint32_t)MASTER_INTREG, 10);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 14);

		//wait for data rx/tx finished
		while ((gMasterTxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// SSPOL test	
	for (i=0; i<=1; i++) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set LBC bit
		_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

		// set SSPOL to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xffeff ) | (i<<8);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);

		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set THEN bit and RHEN bit 
		_set_register_bit((p_uint32_t)MASTER_INTREG, 10);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 14);

		//wait for data rx/tx finished
		while ((gMasterTxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// SSCTL test	
	for (i=0; i<=1; i++) {	
		cspi_soft_reset();
		cspi_default_setting();

		// set LBC bit
		_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

		// set SSCTL to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfff7f ) | (i<<7);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);

		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set THEN bit and RHEN bit 
		_set_register_bit((p_uint32_t)MASTER_INTREG, 10);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 14);

		//wait for data rx/tx finished
		while ((gMasterTxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// PHA test	
	for (i=0; i<=1; i++) {	
		cspi_soft_reset();
		cspi_default_setting();

		// set LBC bit
		_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

		// set PHA to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfffbf ) | (i<<6);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);

		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set THEN bit and RHEN bit 
		_set_register_bit((p_uint32_t)MASTER_INTREG, 10);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 14);

		//wait for data rx/tx finished
		while ((gMasterTxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// POL test	
	for (i=0; i<=1; i++) {	
		cspi_soft_reset();
		cspi_default_setting();

		// set LBC bit
		_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

		// set POL to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfffdf ) | (i<<5);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);

		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set THEN bit and RHEN bit 
		_set_register_bit((p_uint32_t)MASTER_INTREG, 10);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 14);

		//wait for data rx/tx finished
		while ((gMasterTxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// BIT COUNT test	
	for (i=0; i<=0x1f; i++) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set LBC bit
		_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

		// set  BIT COUNT to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfffe0 ) | i ;
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
		
		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set THEN bit and RHEN bit 
		_set_register_bit((p_uint32_t)MASTER_INTREG, 10);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 14);

		//wait for data rx/tx finished
		while ((gMasterTxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				maskValue= (0x1 << (i+1) ) - 1 ;
				if ((slave_rx_data[TestDataIndex] & maskValue )!= (master_tx_data[TestDataIndex] & maskValue))
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	DisableIntSource(16);	// Disable CSPI1 int
	DisableIntSource(15);	// Disable CSPI2 int
	return(error);

}


uint32_t cspi_period_register_test(void)
{
	uint32_t 	i,j,error = 0, tmpValue;
	uint8_t		TestDataIndex=0;

	cspi_soft_reset();
	cspi_default_setting();
	// set LBC bit
	_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

	for (i=0; i<=1; i++) {	

		//i=1, set CSRC to 1, using 32,768K clock
//		if (i) 	_set_register_bit((p_uint32_t)MASTER_PERIODREG,15);
		
		for (j=0; j<=0x7fff; j += 0x7fff/20) {	
			_register_write((p_uint32_t)MASTER_PERIODREG,((i<<0x15)|j) );

			// write datas to FIFO
			for (TestDataIndex=0; TestDataIndex<=7; TestDataIndex++) {
				_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
				}

			_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
			// wait for eight data to finished
			while (!(_register_read((p_uint32_t)MASTER_INTREG) & 0x0040 )) ;
			
			for (TestDataIndex=0; TestDataIndex<=7; TestDataIndex++) {
				slave_rx_data[TestDataIndex] = _register_read((p_uint32_t)MASTER_RXDATAREG);
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
			}
		}	

	return(error);

}



uint32_t cspi_test_register_test(void)
{
	uint32_t 	i,j,error = 0, expected_value,expected_value0,expected_value1,expected_value2,expected_value3;
	uint8_t		TestDataIndex=0;

	cspi_soft_reset();
	cspi_default_setting();
	// set LBC bit
	_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);


	for (i=0; i<=1; i++) {	

		//i=1, set BURST to 1
		if (i) 	_set_register_bit((p_uint32_t)MASTER_TESTREG,16);
		

		// write datas to FIFO
		for (TestDataIndex=0; TestDataIndex<=7; TestDataIndex++) {
			_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
			}

		_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
		// wait for eight data to finished
		while (!(_register_read((p_uint32_t)MASTER_INTREG) & 0x0040 )) ;
			
		for (TestDataIndex=0; TestDataIndex<=7; TestDataIndex++) {
			slave_rx_data[TestDataIndex] = _register_read((p_uint32_t)MASTER_RXDATAREG);
			if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
				error ++;
			}
		}	



	cspi_soft_reset();
	cspi_default_setting();
	// set LBC bit
	_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);


		//i=1, set SWAP to 1
		_set_register_bit((p_uint32_t)MASTER_TESTREG,15);
		
		// write datas to FIFO
		for (TestDataIndex=0; TestDataIndex<=7; TestDataIndex++) {
			_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
			}

		_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
		// wait for eight data to finished
		while (!(_register_read((p_uint32_t)MASTER_INTREG) & 0x0040 )) ;
			
		for (TestDataIndex=0; TestDataIndex<=7; TestDataIndex++) {
			slave_rx_data[TestDataIndex] = _register_read((p_uint32_t)MASTER_RXDATAREG);
			expected_value0= (master_tx_data[TestDataIndex] & 0xff000000)>>24;
			expected_value1= (master_tx_data[TestDataIndex] & 0x00ff0000)>>8;
			expected_value2= (master_tx_data[TestDataIndex] & 0x0000ff00)<<8;
			expected_value3= (master_tx_data[TestDataIndex] & 0x000000ff)<<24;
			expected_value = expected_value3|expected_value2|expected_value1|expected_value0;
			if (slave_rx_data[TestDataIndex] != expected_value)
				error ++;
			}

	return(error);

}

uint32_t cspi_fifo_status_test(void)
{
	uint32_t error = 0, tmpValue;
	uint8_t	TestDataIndex=0;

	cspi_soft_reset();
	cspi_default_setting();

	// Only TE/TH bit should be set
	tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
	if ((tmpValue & 0x00ff)!= 0x0003 ) error ++;			

	_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
	tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
	if ((tmpValue & 0x00ff)!= 0x0003 ) error ++;			

	// TE test	
	// write datas to FIFO
	for (TestDataIndex=1; TestDataIndex<=4; TestDataIndex++) {
		_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		if ((tmpValue & 0x00ff)!= 0x0002 ) error ++;			
		}

	// TH test
	for (TestDataIndex=5; TestDataIndex<8; TestDataIndex++) {
		_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		if ((tmpValue & 0x00ff)!= 0x0000 ) error ++;			
		}

	// TF test
	_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
	tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
	if ((tmpValue & 0x00ff)!= 0x0004 ) error ++;			
	

	cspi_soft_reset();
	cspi_default_setting();
	// set LBC bit
	_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

	// Only TE/TH bit should be set
	tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
	if ((tmpValue & 0x00ff)!= 0x0003 ) error ++;			

	// RR test
	// write datas to FIFO
	for (TestDataIndex=0; TestDataIndex<3; TestDataIndex++) {
		_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
		_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
		delay(0x10000);
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		if ((tmpValue & 0x00ff)!= 0x001b ) error ++;			
		}

	//RH test
	// write datas to FIFO
	for (TestDataIndex=3; TestDataIndex<7; TestDataIndex++) {
		_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
		_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
		delay(0x10000);
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		if ((tmpValue & 0x00ff)!= 0x003b ) error ++;			
		}

	//RF test
	_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex++]);
	_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
	delay(0x100000);
	tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
	if ((tmpValue & 0x00ff)!= 0x007b ) error ++;			

	//RO test	
	_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex++]);
	_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
	delay(0x10000);
	tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
	if ((tmpValue & 0x00ff)!= 0x00fb ) error ++;			

	for (TestDataIndex=0; TestDataIndex<4; TestDataIndex++) {
		slave_rx_data[TestDataIndex] = _register_read((p_uint32_t)MASTER_RXDATAREG);
		if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
			error ++;
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		if ((tmpValue & 0x00ff)!= 0x003b ) error ++;			
		}

	for (TestDataIndex=4; TestDataIndex<7; TestDataIndex++) {
		slave_rx_data[TestDataIndex] = _register_read((p_uint32_t)MASTER_RXDATAREG);
		if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
			error ++;
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		if ((tmpValue & 0x00ff)!= 0x001b ) error ++;			
		}

	for (TestDataIndex=7; TestDataIndex<8; TestDataIndex++) {
		slave_rx_data[TestDataIndex] = _register_read((p_uint32_t)MASTER_RXDATAREG);
		if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
			error ++;
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		if ((tmpValue & 0x00ff)!= 0x000b ) error ++;			
		}


	return(error);
}



uint32_t cspi_DMA_test()
{
	uint32_t error = 0, tmpValue;
	uint8_t	TestDataIndex=0;

	// Enable HCLK for DMA
	_set_register_bit((p_uint32_t)CRM_PCCR0, 30);
	// Enable ipg_clk_perclk for DMA
	_set_register_bit((p_uint32_t)CRM_PCCR0, 13);


	//********************************************************
	//********************************************************
	//********************************************************

	cspi_soft_reset();
	cspi_default_setting();

	// Only TEDMA/THDMA bit should be set
	tmpValue=_register_read((p_uint32_t)MASTER_DMAREG) ;
	if ((tmpValue & 0x00f0)!= 0x00c0 ) error ++;			

	_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
	tmpValue=_register_read((p_uint32_t)MASTER_DMAREG) ;
	if ((tmpValue & 0x00f0)!= 0x00c0 ) error ++;			

	// write four datas to FIFO
	// ONLY THDMA	
	for (TestDataIndex=1; TestDataIndex<5; TestDataIndex++) {
		_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
		tmpValue=_register_read((p_uint32_t)MASTER_DMAREG) ;
		if ((tmpValue & 0x00f0)!= 0x0080 ) error ++;			
		}

	// write another four datas to FIFO
	// TEDMA/THDMA are all cleared
	for (TestDataIndex=5; TestDataIndex<8; TestDataIndex++) {
		_register_write((p_uint32_t)MASTER_TXDATAREG,master_tx_data[TestDataIndex]);
		tmpValue=_register_read((p_uint32_t)MASTER_DMAREG) ;
		if ((tmpValue & 0x00f0)!= 0x0000 ) error ++;			
		}

	// set LBC bit
	_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);
	_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);

	// wait for all data send to Rx FIFO
	while ( (_register_read((p_uint32_t)MASTER_DMAREG) & 0x00f0) != 0x00f0 )  ;

	// read four data form RX FIFO
	// RFDMA should be cleared
	for (TestDataIndex=0; TestDataIndex<4; TestDataIndex++) {
		tmpValue=_register_read((p_uint32_t)MASTER_RXDATAREG) ;
		tmpValue=_register_read((p_uint32_t)MASTER_DMAREG) ;
		if ((tmpValue & 0x00f0)!= 0x00d0 ) error ++;			
		}

	// read another four data form RX FIFO
	// RHDMA should be cleared
	for (TestDataIndex=4; TestDataIndex<7; TestDataIndex++) {
		tmpValue=_register_read((p_uint32_t)MASTER_RXDATAREG) ;
		tmpValue=_register_read((p_uint32_t)MASTER_DMAREG) ;
		if ((tmpValue & 0x00f0)!= 0x00c0 ) error ++;			
		}

	//********************************************************
	//********************************************************
	//********************************************************
	cspi_soft_reset();
	cspi_default_setting();

	// set LBC bit
	_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

	// enable DMA MODULE 
	_register_write((p_uint32_t)DMA_DCR,0x0003);
	delay(0x10000);
	_register_write((p_uint32_t)DMA_DCR,0x0001);

	_register_write((p_uint32_t)DMA_RSSR7,MASTER_TX_DMAREQ);
	_register_write((p_uint32_t)DMA_SAR7,(uint32_t)master_tx_data);
	_register_write((p_uint32_t)DMA_DAR7,MASTER_TXDATAREG);
	_register_write((p_uint32_t)DMA_CNTR7,MAX_TEST_DATA_NUM*4);
	_register_write((p_uint32_t)DMA_BLR7,16);

	_register_write((p_uint32_t)DMA_RSSR6,MASTER_RX_DMAREQ);
	_register_write((p_uint32_t)DMA_SAR6,MASTER_RXDATAREG);
	_register_write((p_uint32_t)DMA_DAR6,(uint32_t)slave_rx_data);
	_register_write((p_uint32_t)DMA_CNTR6,MAX_TEST_DATA_NUM*4);
	_register_write((p_uint32_t)DMA_BLR6,16);

	_register_write((p_uint32_t)DMA_CCR7,0x2009);
	_register_write((p_uint32_t)DMA_CCR6,0x0809);

	// Enable TH/RH DMA
	_register_write((p_uint32_t)MASTER_DMAREG,0x9000);

	while ( _register_read((p_uint32_t)DMA_CCNR7) != MAX_TEST_DATA_NUM*4 ) {
		delay(0x10000);
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		tmpValue=_register_read((p_uint32_t)MASTER_CONTROLREG) ;
		if ((tmpValue & 0x0200) != 0x0200)
			_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
		}
	while ( _register_read((p_uint32_t)DMA_CCNR6) != MAX_TEST_DATA_NUM*4 ); 

	for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
			if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
				error ++;
			}
	_register_write((p_uint32_t)DMA_CCR7,0x0000);
	_register_write((p_uint32_t)DMA_CCR6,0x0000);


	//********************************************************
	//********************************************************
	//********************************************************
	cspi_soft_reset();
	cspi_default_setting();

	// set LBC bit
	_set_register_bit((p_uint32_t)MASTER_TESTREG, 14);

	// enable DMA MODULE 
	_register_write((p_uint32_t)DMA_DCR,0x0003);
	delay(0x10000);
	_register_write((p_uint32_t)DMA_DCR,0x0001);

	_register_write((p_uint32_t)DMA_RSSR9,MASTER_TX_DMAREQ);
	_register_write((p_uint32_t)DMA_SAR9,(uint32_t)master_tx_data);
	_register_write((p_uint32_t)DMA_DAR9, MASTER_TXDATAREG);
	_register_write((p_uint32_t)DMA_CNTR9,MAX_TEST_DATA_NUM*4);
	_register_write((p_uint32_t)DMA_BLR9,32);

	_register_write((p_uint32_t)DMA_RSSR8,MASTER_RX_DMAREQ);
	_register_write((p_uint32_t)DMA_SAR8,MASTER_RXDATAREG);
	_register_write((p_uint32_t)DMA_DAR8,(uint32_t)slave_rx_data);
	_register_write((p_uint32_t)DMA_CNTR8,MAX_TEST_DATA_NUM*4);
	_register_write((p_uint32_t)DMA_BLR8,32);

	_register_write((p_uint32_t)DMA_CCR9,0x2009);
	_register_write((p_uint32_t)DMA_CCR8,0x0809);

	// Enable TE/RF DMA
	_register_write((p_uint32_t)MASTER_DMAREG,0x6000);

	while ( _register_read((p_uint32_t)DMA_CCNR9) != MAX_TEST_DATA_NUM*4 ) {
		delay(0x10000);
		tmpValue=_register_read((p_uint32_t)MASTER_INTREG) ;
		tmpValue=_register_read((p_uint32_t)MASTER_CONTROLREG) ;
		if ((tmpValue & 0x0200) != 0x0200)
			_set_register_bit((p_uint32_t)MASTER_CONTROLREG, 9);
		}
	while ( _register_read((p_uint32_t)DMA_CCNR8) != MAX_TEST_DATA_NUM*4 ); 

	for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
			if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
				error ++;
			}
	_register_write((p_uint32_t)DMA_CCR9,0x0000);
	_register_write((p_uint32_t)DMA_CCR8,0x0000);

	// Disable DMA MODULE 
	_register_write((p_uint32_t)DMA_DCR,0x0003);
	delay(0x10000);
	_register_write((p_uint32_t)DMA_DCR,0x0000);
	
	return(error);
}


uint32_t cspi1_fifo_int_test(void)
{
	uint32_t error = 0, tmpValue;
	uint8_t	TestDataIndex=0;

	// enable ARM AITC INTERUPT
	EnableIRQ();

	cspi_soft_reset();
	cspi_default_setting();

	EnableIntSource(16);	// Enable CSPI1 int

	// set LBC bit
	_set_register_bit((p_uint32_t)CSPI1_TESTREG, 14);
	
	// Only set TEEN bit
	gNormInt16flag=0;
	gIntTestItem=1;
	_set_register_bit((p_uint32_t)CSPI1_INTREG, 9);
	while (gNormInt16flag==0);

	if (gNormInt16flag<0) error++;
	
	gIntTestItem=2;
	_set_register_bit((p_uint32_t)CSPI1_INTREG, 10);
	while (gNormInt16flag==0);	
	if (gNormInt16flag<0) error++;

	gIntTestItem=3;
	_set_register_bit((p_uint32_t)CSPI1_INTREG, 11);
	while (gNormInt16flag==0);	
	if (gNormInt16flag<0) error++;
	
	gIntTestItem=4;
	_set_register_bit((p_uint32_t)CSPI1_INTREG, 16);
	while (gNormInt16flag==0);	
	if (gNormInt16flag<0) error++;
	
	gIntTestItem=5;
	_set_register_bit((p_uint32_t)CSPI1_INTREG, 15);
	while (gNormInt16flag==0);	
	if (gNormInt16flag<0) error++;
	
	gIntTestItem=6;
	_set_register_bit((p_uint32_t)CSPI1_INTREG, 14);
	while (gNormInt16flag==0);	
	if (gNormInt16flag<0) error++;
	
	gIntTestItem=7;
	_set_register_bit((p_uint32_t)CSPI1_INTREG, 13);
	while (gNormInt16flag==0);	
	if (gNormInt16flag<0) error++;
	
	gIntTestItem=8;
	_set_register_bit((p_uint32_t)CSPI1_INTREG, 12);
	while (gNormInt16flag==0);	
	if (gNormInt16flag<0) error++;
	
	DisableIntSource(16);	// Disable CSPI1 int
	return(error);
}

uint32_t cspi2_fifo_int_test(void)
{
	uint32_t error = 0, tmpValue;
	uint8_t	TestDataIndex=0;

	// enable ARM AITC INTERUPT
	EnableIRQ();

	cspi_soft_reset();
	cspi_default_setting();

	// set LBC bit
	_set_register_bit((p_uint32_t)CSPI2_TESTREG, 14);

	EnableIntSource(15);	// Enable CSPI2 int
	
	// Only set TEEN bit
	gNormInt15flag=0;
	gIntTestItem=1;
	_set_register_bit((p_uint32_t)CSPI2_INTREG, 9);
	while (gNormInt15flag==0);	
	if (gNormInt15flag<0) error++;
	
	gIntTestItem=2;
	_set_register_bit((p_uint32_t)CSPI2_INTREG, 10);
	while (gNormInt15flag==0);	
	if (gNormInt15flag<0) error++;

	gIntTestItem=3;
	_set_register_bit((p_uint32_t)CSPI2_INTREG, 11);
	while (gNormInt15flag==0);	
	if (gNormInt15flag<0) error++;
	
	gIntTestItem=4;
	_set_register_bit((p_uint32_t)CSPI2_INTREG, 16);
	while (gNormInt15flag==0);	
	if (gNormInt15flag<0) error++;
	
	gIntTestItem=5;
	_set_register_bit((p_uint32_t)CSPI2_INTREG, 15);
	while (gNormInt15flag==0);	
	if (gNormInt15flag<0) error++;
	
	gIntTestItem=6;
	_set_register_bit((p_uint32_t)CSPI2_INTREG, 14);
	while (gNormInt15flag==0);	
	if (gNormInt15flag<0) error++;
	
	gIntTestItem=7;
	_set_register_bit((p_uint32_t)CSPI2_INTREG, 13);
	while (gNormInt15flag==0);	
	if (gNormInt15flag<0) error++;
	
	gIntTestItem=8;
	_set_register_bit((p_uint32_t)CSPI2_INTREG, 12);
	while (gNormInt15flag==0);	
	if (gNormInt15flag<0) error++;
	
	DisableIntSource(15);	// Disable CSPI2 int
	return(error);
}



// interrupt subroutines
void cspi1_irq_test_isr(void)
{

	uint32_t	i,tmpValue;
	
	gNormInt16flag=1;
	tmpValue=_register_read((p_uint32_t)CSPI1_INTREG);

	if (gIntTestItem<10) {
		if (gIntTestItem==1) {
			if (tmpValue & 0x0001) {
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 9);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[0]);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[1]);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[2]);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[3]);
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		if (gIntTestItem==2) {
			if (tmpValue & 0x0002) {
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 10);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[4]);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[5]);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[6]);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[7]);
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		if (gIntTestItem==3) {
			if (tmpValue & 0x0004) {
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 11);
				//trigger the exchange
				_set_register_bit((p_uint32_t)CSPI1_CONTROLREG, 9);
				// wait for TX FIFI available and send one more data to test RO interrupt
				while (_register_read((p_uint32_t)CSPI1_INTREG) & 0x0004);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[8]);
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		if (gIntTestItem==4) {
			if (tmpValue & 0x0080) {
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 16);
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		if (gIntTestItem==5) {
			if (tmpValue & 0x0040) {
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 15);
				slave_rx_data[0] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
				slave_rx_data[1] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
				slave_rx_data[2] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
				slave_rx_data[3] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		if (gIntTestItem==6) {
			if (tmpValue & 0x0020) {
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 14);
				slave_rx_data[4] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
				slave_rx_data[5] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
				slave_rx_data[6] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		if (gIntTestItem==7) {
			if (tmpValue & 0x0010) {
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 13);
				slave_rx_data[7] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		if (gIntTestItem==8) {
			if (tmpValue & 0x0008) {
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 12);
				_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[8]);
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		}

	else  {

		if (gIntTestItem==10) {	
			// if RH and RHEN is set
			if ((tmpValue & 0x0020) && (tmpValue & 0x4000)) {

				for (i=0;i<4;i++)	
					slave_rx_data[gSlaveRxDataIndex++] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
	
				// if data transmit not finished, enable TH interrupt to init another transmit
				if (gMasterTxDataIndex < MAX_TEST_DATA_NUM)
					_set_register_bit((p_uint32_t)CSPI1_INTREG, 10);

				// if data receive finished, disable RH interrupt
				if (gSlaveRxDataIndex >= MAX_TEST_DATA_NUM)
					_clear_register_bit((p_uint32_t)CSPI1_INTREG, 14);				
				
				}
			// if TH and THEN is set
			else if ((tmpValue & 0x0002) && (tmpValue & 0x0400)) {
				for (i=0;i<4;i++)	
					_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[gMasterTxDataIndex++]);

				// Trigger a exchange
				_set_register_bit((p_uint32_t)CSPI1_CONTROLREG, 9);

				// Disable TH interrupt
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 10);
				
				}
			else	{
				gNormInt16flag=-1;
				}

			}

		else if (gIntTestItem==11) {	

			// if RF and RFEN is set
			if ((tmpValue & 0x0040) && (tmpValue & 0x8000)) {

				for (i=0;i<8;i++)	{
					master_rx_data[gMasterRxDataIndex++] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
					slave_rx_data[gSlaveRxDataIndex++] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
					}
		
				// if data transmit not finished, enable TE interrupt to init another transmit
				if (gMasterTxDataIndex < MAX_TEST_DATA_NUM)
					_set_register_bit((p_uint32_t)CSPI1_INTREG, 9);

				// if data receive finished, disable RF interrupt
				if (gMasterRxDataIndex >= MAX_TEST_DATA_NUM)
					_clear_register_bit((p_uint32_t)CSPI1_INTREG, 15);				
				}
			// if TE and TEEN is set
			else if ((tmpValue & 0x0001) && (tmpValue & 0x0200)) {
				for (i=0;i<8;i++)	{	
					_register_write((p_uint32_t)CSPI1_TXDATAREG,master_tx_data[gMasterTxDataIndex++]);
					_register_write((p_uint32_t)CSPI2_TXDATAREG,slave_tx_data[gSlaveTxDataIndex++]);
					}

				// Trigger a exchange
				_set_register_bit((p_uint32_t)CSPI1_CONTROLREG, 9);

				// Disable TE interrupt
				_clear_register_bit((p_uint32_t)CSPI1_INTREG, 9);
					
				}
			else	{
				gNormInt16flag=-1;
				}
			}
		}
}

// interrupt subroutines
void cspi2_irq_test_isr(void)
{
	uint32_t	i,tmpValue;
	
	gNormInt15flag=1;
	
	tmpValue=_register_read((p_uint32_t)CSPI2_INTREG);
	
	if (gIntTestItem<10) {

		if (gIntTestItem==1) {
			if (tmpValue & 0x0001) {
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 9);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[0]);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[1]);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[2]);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[3]);
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		if (gIntTestItem==2) {
			if (tmpValue & 0x0002) {
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 10);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[4]);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[5]);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[6]);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[7]);
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		if (gIntTestItem==3) {
			if (tmpValue & 0x0004) {
			_clear_register_bit((p_uint32_t)CSPI2_INTREG, 11);
			//trigger the exchange
			_set_register_bit((p_uint32_t)CSPI2_CONTROLREG, 9);
			// wait for TX FIFI available and send one more data to test RO interrupt
			while (_register_read((p_uint32_t)CSPI2_INTREG) & 0x0004);
			_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[8]);
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		if (gIntTestItem==4) {
			if (tmpValue & 0x0080) {
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 16);
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		if (gIntTestItem==5) {
			if (tmpValue & 0x0040) {
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 15);
				slave_rx_data[0] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
				slave_rx_data[1] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
				slave_rx_data[2] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
				slave_rx_data[3] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		if (gIntTestItem==6) {
			if (tmpValue & 0x0020) {
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 14);
				slave_rx_data[4] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
				slave_rx_data[5] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
				slave_rx_data[6] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		if (gIntTestItem==7) {
			if (tmpValue & 0x0010) {
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 13);
				slave_rx_data[7] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		if (gIntTestItem==8) {
			if (tmpValue & 0x0008) {
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 12);
				_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[8]);
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		}

	else  {

		if (gIntTestItem==10) {	
			// if RH and RHEN is set
			if ((tmpValue & 0x0020) && (tmpValue & 0x4000)) {

				for (i=0;i<4;i++)	
					slave_rx_data[gSlaveRxDataIndex++] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
	
				// if data transmit not finished, enable TH interrupt to init another transmit
				if (gMasterTxDataIndex < MAX_TEST_DATA_NUM)
					_set_register_bit((p_uint32_t)CSPI2_INTREG, 10);

				// if data receive finished, disable RH interrupt
				if (gSlaveRxDataIndex >= MAX_TEST_DATA_NUM)
					_clear_register_bit((p_uint32_t)CSPI2_INTREG, 14);				
				
				}
			// if TH and THEN is set
			else if ((tmpValue & 0x0002) && (tmpValue & 0x0400)) {
				for (i=0;i<4;i++)	
					_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[gMasterTxDataIndex++]);

				// Trigger a exchange
				_set_register_bit((p_uint32_t)CSPI2_CONTROLREG, 9);

				// Disable TH interrupt
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 10);
				
				}
			else	{
				gNormInt15flag=-1;
				}

			}

		else if (gIntTestItem==11) {	

			// if RF and RFEN is set
			if ((tmpValue & 0x0040) && (tmpValue & 0x8000)) {

				for (i=0;i<8;i++)	{
					master_rx_data[gMasterRxDataIndex++] = _register_read((p_uint32_t)CSPI2_RXDATAREG);
					slave_rx_data[gSlaveRxDataIndex++] = _register_read((p_uint32_t)CSPI1_RXDATAREG);
					}
		
				// if data transmit not finished, enable TE interrupt to init another transmit
				if (gMasterTxDataIndex < MAX_TEST_DATA_NUM)
					_set_register_bit((p_uint32_t)CSPI2_INTREG, 9);

				// if data receive finished, disable RF interrupt
				if (gMasterRxDataIndex >= MAX_TEST_DATA_NUM)
					_clear_register_bit((p_uint32_t)CSPI2_INTREG, 15);				
				}
			// if TE and TEEN is set
			else if ((tmpValue & 0x0001) && (tmpValue & 0x0200)) {
				for (i=0;i<8;i++)	{	
					_register_write((p_uint32_t)CSPI2_TXDATAREG,master_tx_data[gMasterTxDataIndex++]);
					_register_write((p_uint32_t)CSPI1_TXDATAREG,slave_tx_data[gSlaveTxDataIndex++]);
					}

				// Trigger a exchange
				_set_register_bit((p_uint32_t)CSPI2_CONTROLREG, 9);

				// Disable TE interrupt
				_clear_register_bit((p_uint32_t)CSPI2_INTREG, 9);
					
				}
			else	{
				gNormInt15flag=-1;
				}
			}
		}
}



uint32_t two_cspi_test(void)
{

	uint32_t 	i,j,error = 0, tmpValue,maskValue,TestDataIndex;
	p_uint32_t	tmpAddr;


	// enable ARM AITC INTERUPT
	EnableIRQ();

	EnableIntSource(16);	// Enable CSPI1 int
	EnableIntSource(15);	// Enable CSPI2 int

	gIntTestItem=11;

	// CS[1:0] test	
	for (i=0; i<3; i++ ) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set CS[1:0] to i, using SSi
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0x3ffff ) | (i<<18);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
//		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0x3ffff ) | (i<<18);
		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0x3ffff ) | (0<<18);
		_register_write((p_uint32_t)SLAVE_CONTROLREG,tmpValue);

		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gMasterRxDataIndex=0;
		gSlaveTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set TEEN and RFEN bit of Master CSPI
		_set_register_bit((p_uint32_t)MASTER_INTREG, 9);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 15);

		//wait for data rx/tx finished
		while ((gMasterRxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (master_rx_data[TestDataIndex] != slave_tx_data[TestDataIndex])
					error ++;
				}
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;
		
		}

/*/
	// DATA RATE test	
	for (i=1; i<7; i++) {	

		cspi_soft_reset();
		cspi_default_setting();


		// set DATA RATE bits to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xc3fff ) | (i<<14);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0xc3fff ) | (i<<14);
		_register_write((p_uint32_t)SLAVE_CONTROLREG,tmpValue);


		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gMasterRxDataIndex=0;
		gSlaveTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set TEEN and RFEN bit of Master CSPI
		_set_register_bit((p_uint32_t)MASTER_INTREG, 9);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 15);

		//wait for data rx/tx finished
		while ((gMasterRxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (master_rx_data[TestDataIndex] != slave_tx_data[TestDataIndex])
					error ++;
				}
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// DRCTL test
	// AT present , only DRCTL = 0 can be test	
	for (i=0; i<=0; i++) {	

		cspi_soft_reset();
		cspi_default_setting();


		// set DRCTL to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfcfff ) | (i<<12);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0xfcfff ) | (i<<12);
		_register_write((p_uint32_t)SLAVE_CONTROLREG,tmpValue);


		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gMasterRxDataIndex=0;
		gSlaveTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set TEEN and RFEN bit of Master CSPI
		_set_register_bit((p_uint32_t)MASTER_INTREG, 9);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 15);

		//wait for data rx/tx finished
		while ((gMasterRxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (master_rx_data[TestDataIndex] != slave_tx_data[TestDataIndex])
					error ++;
				}
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// SSPOL test	
	for (i=0; i<=1; i++) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set SSPOL to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xffeff ) | (i<<8);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0xffeff ) | (i<<8);
		_register_write((p_uint32_t)SLAVE_CONTROLREG,tmpValue);


		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gMasterRxDataIndex=0;
		gSlaveTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set TEEN and RFEN bit of Master CSPI
		_set_register_bit((p_uint32_t)MASTER_INTREG, 9);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 15);

		//wait for data rx/tx finished
		while ((gMasterRxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (master_rx_data[TestDataIndex] != slave_tx_data[TestDataIndex])
					error ++;
				}
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// SSCTL test	
	for (i=0; i<=1; i++) {	

		cspi_soft_reset();
		cspi_default_setting();


		// set SSCTL to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfff7f ) | (i<<7);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0xfff7f ) | (i<<7);
		_register_write((p_uint32_t)SLAVE_CONTROLREG,tmpValue);


		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gMasterRxDataIndex=0;
		gSlaveTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set TEEN and RFEN bit of Master CSPI
		_set_register_bit((p_uint32_t)MASTER_INTREG, 9);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 15);

		//wait for data rx/tx finished
		while ((gMasterRxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (master_rx_data[TestDataIndex] != slave_tx_data[TestDataIndex])
					error ++;
				}
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// PHA test	
	for (i=0; i<=1; i++) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set PHA to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfffbf ) | (i<<6);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0xfffbf ) | (i<<6);
		_register_write((p_uint32_t)SLAVE_CONTROLREG,tmpValue);


		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gMasterRxDataIndex=0;
		gSlaveTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set TEEN and RFEN bit of Master CSPI
		_set_register_bit((p_uint32_t)MASTER_INTREG, 9);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 15);

		//wait for data rx/tx finished
		while ((gMasterRxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (master_rx_data[TestDataIndex] != slave_tx_data[TestDataIndex])
					error ++;
				}
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// POL test	
	for (i=0; i<=1; i++) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set POL to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfffdf ) | (i<<5);
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0xfffdf ) | (i<<5);
		_register_write((p_uint32_t)SLAVE_CONTROLREG,tmpValue);


		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gMasterRxDataIndex=0;
		gSlaveTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set TEEN and RFEN bit of Master CSPI
		_set_register_bit((p_uint32_t)MASTER_INTREG, 9);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 15);

		//wait for data rx/tx finished
		while ((gMasterRxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (master_rx_data[TestDataIndex] != slave_tx_data[TestDataIndex])
					error ++;
				}
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if (slave_rx_data[TestDataIndex] != master_tx_data[TestDataIndex])
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}

	// BIT COUNT test	
	for (i=0; i<=0x1f; i++) {	

		cspi_soft_reset();
		cspi_default_setting();

		// set  BIT COUNT to i
		tmpValue=(_register_read((p_uint32_t)MASTER_CONTROLREG) & 0xfffe0 ) |  i;
		_register_write((p_uint32_t)MASTER_CONTROLREG,tmpValue);
		tmpValue=(_register_read((p_uint32_t)SLAVE_CONTROLREG) & 0xfffe0 ) | i;
		_register_write((p_uint32_t)SLAVE_CONTROLREG,tmpValue);


		//initalization
		gNormInt16flag=0;
		gNormInt15flag=0;
		gMasterTxDataIndex=0;
		gMasterRxDataIndex=0;
		gSlaveTxDataIndex=0;
		gSlaveRxDataIndex=0;

		// Set TEEN and RFEN bit of Master CSPI
		_set_register_bit((p_uint32_t)MASTER_INTREG, 9);
		_set_register_bit((p_uint32_t)MASTER_INTREG, 15);

		//wait for data rx/tx finished
		while ((gMasterRxDataIndex<MAX_TEST_DATA_NUM) || (gSlaveRxDataIndex<MAX_TEST_DATA_NUM));
		
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				maskValue= (0x1 << (i+1) ) - 1 ;
				if ((master_rx_data[TestDataIndex] & maskValue )!= (slave_tx_data[TestDataIndex] & maskValue))
					error ++;
				}
		for (TestDataIndex=0; TestDataIndex<MAX_TEST_DATA_NUM; TestDataIndex++) {
				if ((slave_rx_data[TestDataIndex] & maskValue )!= (master_tx_data[TestDataIndex] & maskValue))
					error ++;
				}
		if ((gNormInt16flag<0)||(gNormInt15flag<0)) error++;

		}
/*/
	DisableIntSource(16);	// Disable CSPI1 int
	DisableIntSource(15);	// Disable CSPI2 int
	
	return(error);

}

uint32_t two_boards_test(void)
{
	uint32_t 	i,j,error = 0, tmpValue,maskValue;
	uint8_t		TestDataIndex=0;

//	#ifdef M2S1_TEST 
//	#ifdef MASTER_MODE_TEST 
//	#ifdef SLEVE_MODE_TEST 

// M1S2_TEST

	return(error);

}