/******************************************************************************

 C   H E A D E R   F I L E

 (c) Copyright Motorola Semiconductors Hong Kong Limited 2001-2003
 ALL RIGHTS RESERVED

*******************************************************************************

 Project Name : i.MX System Test Program
 Project No.  : 
 Title        : 
 File Name    : testcase.h
 Last Modified: 04/27/2003
 (MM/DD/YYYY)

 Description  : This file contains all the test case specific data types

 Assumptions  : 
 
 Dependency Comments :

 Project Specific Data :
 
 History (MM/DD/YYYY) :
 04/27/2003 - Initial Proposal

******************************************************************************/


/*************************** Header File Includes ****************************/
#include 	"Common.h"
#include 	"tht_memory_map_defines.h"


//#define M1S2_TEST
#define M2S1_TEST


/*
#define MASTER_MODE_TEST
#define SLAVE_MODE_TEST
*/

/********************************* Constants *********************************/

/********************************** Macros ***********************************/

/******************************* Global Data *********************************/

/*************************** Function prototype (S) **************************/
#ifdef EXTERN
    #undef EXTERN
#endif


#ifdef CSPI_PROTYPE_DECLARE
	#define EXTERN extern
#else
	#define EXTERN
#endif

#ifdef M2S1_TEST

	#define MASTER_BASE_ADDR 		CSPI2_BASE_ADDR
	#define MASTER_RXDATAREG 		CSPI2_RXDATAREG
	#define MASTER_TXDATAREG 		CSPI2_TXDATAREG
	#define MASTER_CONTROLREG 		CSPI2_CONTROLREG
	#define MASTER_INTREG 			CSPI2_INTREG
	#define MASTER_TESTREG 			CSPI2_TESTREG
	#define MASTER_PERIODREG 		CSPI2_PERIODREG
	#define MASTER_DMAREG 			CSPI2_DMAREG
	#define MASTER_RESETREG 		CSPI2_RESETREG

	#define SLAVE_BASE_ADDR 		CSPI1_BASE_ADDR
	#define SLAVE_RXDATAREG 		CSPI1_RXDATAREG
	#define SLAVE_TXDATAREG 		CSPI1_TXDATAREG
	#define SLAVE_CONTROLREG 		CSPI1_CONTROLREG
	#define SLAVE_INTREG 			CSPI1_INTREG
	#define SLAVE_TESTREG 			CSPI1_TESTREG
	#define SLAVE_PERIODREG 		CSPI1_PERIODREG
	#define SLAVE_DMAREG 			CSPI1_DMAREG
	#define SLAVE_RESETREG 			CSPI1_RESETREG

	#define MASTER_TX_DMAREQ 		17
	#define MASTER_RX_DMAREQ 		16
	#define SLAVE_TX_DMAREQ 		19
	#define SLAVE_RX_DMAREQ 		18

#else

	#define MASTER_BASE_ADDR 		CSPI1_BASE_ADDR
	#define MASTER_RXDATAREG 		CSPI1_RXDATAREG
	#define MASTER_TXDATAREG 		CSPI1_TXDATAREG
	#define MASTER_CONTROLREG 		CSPI1_CONTROLREG
	#define MASTER_INTREG 			CSPI1_INTREG
	#define MASTER_TESTREG 			CSPI1_TESTREG
	#define MASTER_PERIODREG 		CSPI1_PERIODREG
	#define MASTER_DMAREG 			CSPI1_DMAREG
	#define MASTER_RESETREG 		CSPI1_RESETREG

	#define SLAVE_BASE_ADDR 		CSPI2_BASE_ADDR
	#define SLAVE_RXDATAREG 		CSPI2_RXDATAREG
	#define SLAVE_TXDATAREG 		CSPI2_TXDATAREG
	#define SLAVE_CONTROLREG 		CSPI2_CONTROLREG
	#define SLAVE_INTREG 			CSPI2_INTREG
	#define SLAVE_TESTREG 			CSPI2_TESTREG
	#define SLAVE_PERIODREG 		CSPI2_PERIODREG
	#define SLAVE_DMAREG 			CSPI2_DMAREG
	#define SLAVE_RESETREG 			CSPI2_RESETREG

	#define MASTER_TX_DMAREQ 		19
	#define MASTER_RX_DMAREQ 		18
	#define SLAVE_TX_DMAREQ 		17
	#define SLAVE_RX_DMAREQ 		16

#endif


// main program for cspi test
EXTERN void cspi_test_main (void);

EXTERN uint32_t _register_read(p_uint32_t addr);
EXTERN void _register_write(p_uint32_t addr, uint32_t value);
EXTERN void _set_register_bit(p_uint32_t addr, uint32_t Nbit);
EXTERN void _clear_register_bit(p_uint32_t addr, uint32_t Nbit);
EXTERN void delay(uint32_t);

EXTERN void cspi_port_init(void);
EXTERN void cspi_soft_reset(void);
EXTERN void cspi_enable(void);
EXTERN void cspi_disable(void);
EXTERN void cspi_default_setting(void);
EXTERN void cspi_init(void);

EXTERN uint32_t cspi_reset_status_test(void);
EXTERN uint32_t cspi_register_read_write_test(void);
EXTERN uint32_t cspi_soft_reset_test(void);
EXTERN uint32_t cspi_control_register_test(void);
EXTERN uint32_t cspi_period_register_test(void);
EXTERN uint32_t cspi_test_register_test(void);
EXTERN uint32_t cspi_fifo_status_test(void);
EXTERN uint32_t cspi1_fifo_int_test(void);
EXTERN uint32_t cspi2_fifo_int_test(void);
EXTERN uint32_t cspi_DMA_test(void);
EXTERN uint32_t two_cspi_test(void);
EXTERN uint32_t two_boards_test(void);

EXTERN void	cspi1_irq_test_isr(void);
EXTERN void	cspi2_irq_test_isr(void);


extern int32_t gNormInt15flag;
extern int32_t gNormInt16flag;