#ifndef CONFIG_PAD_MODE_H #define CONFIG_PAD_MODE_H #include "functions.h" // SW_MUX_CTL and SW_PAD_CTL configuration for pads // ************************************************** // These defines are generated automatically from the tortola_pins Excel table // Please do not edit it manually. // For questions please contact Avi Levi : rm96456@motorola.com #define CAPTURE 1 #define COMPARE 2 #define WATCHDOG_RST 3 #define PWMO 4 #define GPIO1_0 5 #define GPIO1_1 6 #define GPIO1_2 7 #define GPIO1_3 8 #define GPIO1_4 9 #define GPIO1_5 10 #define GPIO1_6 11 #define GPIO3_0 12 #define GPIO3_1 13 #define SCLK0 14 #define SRST0 15 #define SVEN0 16 #define STX0 17 #define SRX0 18 #define SIMPD0 19 #define CKIH 20 #define RESET_IN_B 21 #define POR_B 22 #define CLKO 23 #define BOOT_MODE0 24 #define BOOT_MODE1 25 #define BOOT_MODE2 26 #define BOOT_MODE3 27 #define BOOT_MODE4 28 #define CKIL 29 #define POWER_FAIL 30 #define VSTBY 31 #define DVFS0 32 #define DVFS1 33 #define VPG0 34 #define VPG1 35 #define A0 36 #define A1 37 #define A2 38 #define A3 39 #define A4 40 #define A5 41 #define A6 42 #define A7 43 #define A8 44 #define A9 45 #define A10 46 #define MA10 47 #define A11 48 #define A12 49 #define A13 50 #define A14 51 #define A15 52 #define A16 53 #define A17 54 #define A18 55 #define A19 56 #define A20 57 #define A21 58 #define A22 59 #define A23 60 #define A24 61 #define A25 62 #define SDBA1 63 #define SDBA0 64 #define SD0 65 #define SD1 66 #define SD2 67 #define SD3 68 #define SD4 69 #define SD5 70 #define SD6 71 #define SD7 72 #define SD8 73 #define SD9 74 #define SD10 75 #define SD11 76 #define SD12 77 #define SD13 78 #define SD14 79 #define SD15 80 #define SD16 81 #define SD17 82 #define SD18 83 #define SD19 84 #define SD20 85 #define SD21 86 #define SD22 87 #define SD23 88 #define SD24 89 #define SD25 90 #define SD26 91 #define SD27 92 #define SD28 93 #define SD29 94 #define SD30 95 #define SD31 96 #define DQM0 97 #define DQM1 98 #define DQM2 99 #define DQM3 100 #define EB0 101 #define EB1 102 #define OE 103 #define CS0 104 #define CS1 105 #define CS2 106 #define CS3 107 #define CS4 108 #define CS5 109 #define ECB 110 #define LBA 111 #define BCLK 112 #define RW 113 #define RAS 114 #define CAS 115 #define SDWE 116 #define SDCKE0 117 #define SDCKE1 118 #define SDCLK 119 #define SDCLK_B 120 #define SDQS0 121 #define SDQS1 122 #define SDQS2 123 #define SDQS3 124 #define NFWE_B 125 #define NFRE_B 126 #define NFALE 127 #define NFCLE 128 #define NFWP_B 129 #define NFCE_B 130 #define NFRB 131 #define D15 132 #define D14 133 #define D13 134 #define D12 135 #define D11 136 #define D10 137 #define D9 138 #define D8 139 #define D7 140 #define D6 141 #define D5 142 #define D4 143 #define D3 144 #define D2 145 #define D1 146 #define D0 147 #define PC_CD1_B 148 #define PC_CD2_B 149 #define PC_WAIT_B 150 #define PC_READY 151 #define PC_PWRON 152 #define PC_VS1 153 #define PC_VS2 154 #define PC_BVD1 155 #define PC_BVD2 156 #define PC_RST 157 #define IOIS16 158 #define PC_RW_B 159 #define PC_POE 160 #define M_REQUEST 161 #define M_GRANT 162 #define CSI_D4 163 #define CSI_D5 164 #define CSI_D6 165 #define CSI_D7 166 #define CSI_D8 167 #define CSI_D9 168 #define CSI_D10 169 #define CSI_D11 170 #define CSI_D12 171 #define CSI_D13 172 #define CSI_D14 173 #define CSI_D15 174 #define CSI_MCLK 175 #define CSI_VSYNC 176 #define CSI_HSYNC 177 #define CSI_PIXCLK 178 #define I2C_CLK 179 #define I2C_DAT 180 #define STXD3 181 #define SRXD3 182 #define SCK3 183 #define SFS3 184 #define STXD4 185 #define SRXD4 186 #define SCK4 187 #define SFS4 188 #define STXD5 189 #define SRXD5 190 #define SCK5 191 #define SFS5 192 #define STXD6 193 #define SRXD6 194 #define SCK6 195 #define SFS6 196 #define CSPI1_MOSI 197 #define CSPI1_MISO 198 #define CSPI1_SS0 199 #define CSPI1_SS1 200 #define CSPI1_SS2 201 #define CSPI1_SCLK 202 #define CSPI1_SPI_RDY 203 #define CSPI2_MOSI 204 #define CSPI2_MISO 205 #define CSPI2_SS0 206 #define CSPI2_SS1 207 #define CSPI2_SS2 208 #define CSPI2_SCLK 209 #define CSPI2_SPI_RDY 210 #define RXD1 211 #define TXD1 212 #define RTS1 213 #define CTS1 214 #define DTR_DCE1 215 #define DSR_DCE1 216 #define RI_DCE1 217 #define DCD_DCE1 218 #define DTR_DTE1 219 #define DSR_DTE1 220 #define RI_DTE1 221 #define DCD_DTE1 222 #define DTR_DCE2 223 #define RXD2 224 #define TXD2 225 #define RTS2 226 #define CTS2 227 #define BATT_LINE 228 #define KEY_ROW0 229 #define KEY_ROW1 230 #define KEY_ROW2 231 #define KEY_ROW3 232 #define KEY_ROW4 233 #define KEY_ROW5 234 #define KEY_ROW6 235 #define KEY_ROW7 236 #define KEY_COL0 237 #define KEY_COL1 238 #define KEY_COL2 239 #define KEY_COL3 240 #define KEY_COL4 241 #define KEY_COL5 242 #define KEY_COL6 243 #define KEY_COL7 244 #define RTCK 245 #define TCK 246 #define TMS 247 #define TDI 248 #define TDO 249 #define TRSTB 250 #define DE_B 251 #define SJC_MOD 252 #define USB_PWR 253 #define USB_OC 254 #define USB_BYP 255 #define USBOTG_CLK 256 #define USBOTG_DIR 257 #define USBOTG_STP 258 #define USBOTG_NXT 259 #define USBOTG_DATA0 260 #define USBOTG_DATA1 261 #define USBOTG_DATA2 262 #define USBOTG_DATA3 263 #define USBOTG_DATA4 264 #define USBOTG_DATA5 265 #define USBOTG_DATA6 266 #define USBOTG_DATA7 267 #define USBH2_CLK 268 #define USBH2_DIR 269 #define USBH2_STP 270 #define USBH2_NXT 271 #define USBH2_DATA0 272 #define USBH2_DATA1 273 #define LD0 274 #define LD1 275 #define LD2 276 #define LD3 277 #define LD4 278 #define LD5 279 #define LD6 280 #define LD7 281 #define LD8 282 #define LD9 283 #define LD10 284 #define LD11 285 #define LD12 286 #define LD13 287 #define LD14 288 #define LD15 289 #define LD16 290 #define LD17 291 #define VSYNC0 292 #define HSYNC 293 #define FPSHIFT 294 #define DRDY0 295 #define SD_D_I 296 #define SD_D_IO 297 #define SD_D_CLK 298 #define LCS0 299 #define LCS1 300 #define SER_RS 301 #define PAR_RS 302 #define WRITE 303 #define READ 304 #define VSYNC3 305 #define CONTRAST 306 #define D3_REV 307 #define D3_CLS 308 #define D3_SPL 309 #define SD1_CMD 310 #define SD1_CLK 311 #define SD1_DATA0 312 #define SD1_DATA1 313 #define SD1_DATA2 314 #define SD1_DATA3 315 #define ATA_CS0 316 #define ATA_CS1 317 #define ATA_DIOR 318 #define ATA_DIOW 319 #define ATA_DMACK 320 #define ATA_RESET_B 321 #define CE_CONTROL 322 #define CLKSS 323 #define CSPI3_MOSI 324 #define CSPI3_MISO 325 #define CSPI3_SCLK 326 #define CSPI3_SPI_RDY 327 #define TTM_PAD 328 // SW_MUX_CTL defines : //###################### #define CAPTURE_SW_MUX_REG SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO #define CAPTURE_BYTE_IN_SW_MUX 3 #define COMPARE_SW_MUX_REG SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO #define COMPARE_BYTE_IN_SW_MUX 2 #define WATCHDOG_RST_SW_MUX_REG SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO #define WATCHDOG_RST_BYTE_IN_SW_MUX 1 #define PWMO_SW_MUX_REG SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO #define PWMO_BYTE_IN_SW_MUX 0 #define GPIO1_0_SW_MUX_REG SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 #define GPIO1_0_BYTE_IN_SW_MUX 3 #define GPIO1_1_SW_MUX_REG SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 #define GPIO1_1_BYTE_IN_SW_MUX 2 #define GPIO1_2_SW_MUX_REG SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 #define GPIO1_2_BYTE_IN_SW_MUX 1 #define GPIO1_3_SW_MUX_REG SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 #define GPIO1_3_BYTE_IN_SW_MUX 0 #define GPIO1_4_SW_MUX_REG SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 #define GPIO1_4_BYTE_IN_SW_MUX 3 #define GPIO1_5_SW_MUX_REG SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 #define GPIO1_5_BYTE_IN_SW_MUX 2 #define GPIO1_6_SW_MUX_REG SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 #define GPIO1_6_BYTE_IN_SW_MUX 1 #define GPIO3_0_SW_MUX_REG SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 #define GPIO3_0_BYTE_IN_SW_MUX 0 #define GPIO3_1_SW_MUX_REG SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 #define GPIO3_1_BYTE_IN_SW_MUX 3 #define SCLK0_SW_MUX_REG SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 #define SCLK0_BYTE_IN_SW_MUX 2 #define SRST0_SW_MUX_REG SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 #define SRST0_BYTE_IN_SW_MUX 1 #define SVEN0_SW_MUX_REG SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 #define SVEN0_BYTE_IN_SW_MUX 0 #define STX0_SW_MUX_REG SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH #define STX0_BYTE_IN_SW_MUX 3 #define SRX0_SW_MUX_REG SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH #define SRX0_BYTE_IN_SW_MUX 2 #define SIMPD0_SW_MUX_REG SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH #define SIMPD0_BYTE_IN_SW_MUX 1 #define CKIH_SW_MUX_REG SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH #define CKIH_BYTE_IN_SW_MUX 0 #define RESET_IN_B_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 #define RESET_IN_B_BYTE_IN_SW_MUX 3 #define POR_B_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 #define POR_B_BYTE_IN_SW_MUX 2 #define CLKO_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 #define CLKO_BYTE_IN_SW_MUX 1 #define BOOT_MODE0_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 #define BOOT_MODE0_BYTE_IN_SW_MUX 0 #define BOOT_MODE1_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 #define BOOT_MODE1_BYTE_IN_SW_MUX 3 #define BOOT_MODE2_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 #define BOOT_MODE2_BYTE_IN_SW_MUX 2 #define BOOT_MODE3_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 #define BOOT_MODE3_BYTE_IN_SW_MUX 1 #define BOOT_MODE4_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 #define BOOT_MODE4_BYTE_IN_SW_MUX 0 #define CKIL_SW_MUX_REG SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 #define CKIL_BYTE_IN_SW_MUX 3 #define POWER_FAIL_SW_MUX_REG SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 #define POWER_FAIL_BYTE_IN_SW_MUX 2 #define VSTBY_SW_MUX_REG SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 #define VSTBY_BYTE_IN_SW_MUX 1 #define DVFS0_SW_MUX_REG SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 #define DVFS0_BYTE_IN_SW_MUX 0 #define DVFS1_SW_MUX_REG SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 #define DVFS1_BYTE_IN_SW_MUX 3 #define VPG0_SW_MUX_REG SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 #define VPG0_BYTE_IN_SW_MUX 2 #define VPG1_SW_MUX_REG SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 #define VPG1_BYTE_IN_SW_MUX 1 #define A0_SW_MUX_REG SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 #define A0_BYTE_IN_SW_MUX 0 #define A1_SW_MUX_REG SW_MUX_CTL_A1_A2_A3_A4 #define A1_BYTE_IN_SW_MUX 3 #define A2_SW_MUX_REG SW_MUX_CTL_A1_A2_A3_A4 #define A2_BYTE_IN_SW_MUX 2 #define A3_SW_MUX_REG SW_MUX_CTL_A1_A2_A3_A4 #define A3_BYTE_IN_SW_MUX 1 #define A4_SW_MUX_REG SW_MUX_CTL_A1_A2_A3_A4 #define A4_BYTE_IN_SW_MUX 0 #define A5_SW_MUX_REG SW_MUX_CTL_A5_A6_A7_A8 #define A5_BYTE_IN_SW_MUX 3 #define A6_SW_MUX_REG SW_MUX_CTL_A5_A6_A7_A8 #define A6_BYTE_IN_SW_MUX 2 #define A7_SW_MUX_REG SW_MUX_CTL_A5_A6_A7_A8 #define A7_BYTE_IN_SW_MUX 1 #define A8_SW_MUX_REG SW_MUX_CTL_A5_A6_A7_A8 #define A8_BYTE_IN_SW_MUX 0 #define A9_SW_MUX_REG SW_MUX_CTL_A9_A10_MA10_A11 #define A9_BYTE_IN_SW_MUX 3 #define A10_SW_MUX_REG SW_MUX_CTL_A9_A10_MA10_A11 #define A10_BYTE_IN_SW_MUX 2 #define MA10_SW_MUX_REG SW_MUX_CTL_A9_A10_MA10_A11 #define MA10_BYTE_IN_SW_MUX 1 #define A11_SW_MUX_REG SW_MUX_CTL_A9_A10_MA10_A11 #define A11_BYTE_IN_SW_MUX 0 #define A12_SW_MUX_REG SW_MUX_CTL_A12_A13_A14_A15 #define A12_BYTE_IN_SW_MUX 3 #define A13_SW_MUX_REG SW_MUX_CTL_A12_A13_A14_A15 #define A13_BYTE_IN_SW_MUX 2 #define A14_SW_MUX_REG SW_MUX_CTL_A12_A13_A14_A15 #define A14_BYTE_IN_SW_MUX 1 #define A15_SW_MUX_REG SW_MUX_CTL_A12_A13_A14_A15 #define A15_BYTE_IN_SW_MUX 0 #define A16_SW_MUX_REG SW_MUX_CTL_A16_A17_A18_A19 #define A16_BYTE_IN_SW_MUX 3 #define A17_SW_MUX_REG SW_MUX_CTL_A16_A17_A18_A19 #define A17_BYTE_IN_SW_MUX 2 #define A18_SW_MUX_REG SW_MUX_CTL_A16_A17_A18_A19 #define A18_BYTE_IN_SW_MUX 1 #define A19_SW_MUX_REG SW_MUX_CTL_A16_A17_A18_A19 #define A19_BYTE_IN_SW_MUX 0 #define A20_SW_MUX_REG SW_MUX_CTL_A20_A21_A22_A23 #define A20_BYTE_IN_SW_MUX 3 #define A21_SW_MUX_REG SW_MUX_CTL_A20_A21_A22_A23 #define A21_BYTE_IN_SW_MUX 2 #define A22_SW_MUX_REG SW_MUX_CTL_A20_A21_A22_A23 #define A22_BYTE_IN_SW_MUX 1 #define A23_SW_MUX_REG SW_MUX_CTL_A20_A21_A22_A23 #define A23_BYTE_IN_SW_MUX 0 #define A24_SW_MUX_REG SW_MUX_CTL_A24_A25_SDBA1_SDBA0 #define A24_BYTE_IN_SW_MUX 3 #define A25_SW_MUX_REG SW_MUX_CTL_A24_A25_SDBA1_SDBA0 #define A25_BYTE_IN_SW_MUX 2 #define SDBA1_SW_MUX_REG SW_MUX_CTL_A24_A25_SDBA1_SDBA0 #define SDBA1_BYTE_IN_SW_MUX 1 #define SDBA0_SW_MUX_REG SW_MUX_CTL_A24_A25_SDBA1_SDBA0 #define SDBA0_BYTE_IN_SW_MUX 0 #define SD0_SW_MUX_REG SW_MUX_CTL_SD0_SD1_SD2_SD3 #define SD0_BYTE_IN_SW_MUX 3 #define SD1_SW_MUX_REG SW_MUX_CTL_SD0_SD1_SD2_SD3 #define SD1_BYTE_IN_SW_MUX 2 #define SD2_SW_MUX_REG SW_MUX_CTL_SD0_SD1_SD2_SD3 #define SD2_BYTE_IN_SW_MUX 1 #define SD3_SW_MUX_REG SW_MUX_CTL_SD0_SD1_SD2_SD3 #define SD3_BYTE_IN_SW_MUX 0 #define SD4_SW_MUX_REG SW_MUX_CTL_SD4_SD5_SD6_SD7 #define SD4_BYTE_IN_SW_MUX 3 #define SD5_SW_MUX_REG SW_MUX_CTL_SD4_SD5_SD6_SD7 #define SD5_BYTE_IN_SW_MUX 2 #define SD6_SW_MUX_REG SW_MUX_CTL_SD4_SD5_SD6_SD7 #define SD6_BYTE_IN_SW_MUX 1 #define SD7_SW_MUX_REG SW_MUX_CTL_SD4_SD5_SD6_SD7 #define SD7_BYTE_IN_SW_MUX 0 #define SD8_SW_MUX_REG SW_MUX_CTL_SD8_SD9_SD10_SD11 #define SD8_BYTE_IN_SW_MUX 3 #define SD9_SW_MUX_REG SW_MUX_CTL_SD8_SD9_SD10_SD11 #define SD9_BYTE_IN_SW_MUX 2 #define SD10_SW_MUX_REG SW_MUX_CTL_SD8_SD9_SD10_SD11 #define SD10_BYTE_IN_SW_MUX 1 #define SD11_SW_MUX_REG SW_MUX_CTL_SD8_SD9_SD10_SD11 #define SD11_BYTE_IN_SW_MUX 0 #define SD12_SW_MUX_REG SW_MUX_CTL_SD12_SD13_SD14_SD15 #define SD12_BYTE_IN_SW_MUX 3 #define SD13_SW_MUX_REG SW_MUX_CTL_SD12_SD13_SD14_SD15 #define SD13_BYTE_IN_SW_MUX 2 #define SD14_SW_MUX_REG SW_MUX_CTL_SD12_SD13_SD14_SD15 #define SD14_BYTE_IN_SW_MUX 1 #define SD15_SW_MUX_REG SW_MUX_CTL_SD12_SD13_SD14_SD15 #define SD15_BYTE_IN_SW_MUX 0 #define SD16_SW_MUX_REG SW_MUX_CTL_SD16_SD17_SD18_SD19 #define SD16_BYTE_IN_SW_MUX 3 #define SD17_SW_MUX_REG SW_MUX_CTL_SD16_SD17_SD18_SD19 #define SD17_BYTE_IN_SW_MUX 2 #define SD18_SW_MUX_REG SW_MUX_CTL_SD16_SD17_SD18_SD19 #define SD18_BYTE_IN_SW_MUX 1 #define SD19_SW_MUX_REG SW_MUX_CTL_SD16_SD17_SD18_SD19 #define SD19_BYTE_IN_SW_MUX 0 #define SD20_SW_MUX_REG SW_MUX_CTL_SD20_SD21_SD22_SD23 #define SD20_BYTE_IN_SW_MUX 3 #define SD21_SW_MUX_REG SW_MUX_CTL_SD20_SD21_SD22_SD23 #define SD21_BYTE_IN_SW_MUX 2 #define SD22_SW_MUX_REG SW_MUX_CTL_SD20_SD21_SD22_SD23 #define SD22_BYTE_IN_SW_MUX 1 #define SD23_SW_MUX_REG SW_MUX_CTL_SD20_SD21_SD22_SD23 #define SD23_BYTE_IN_SW_MUX 0 #define SD24_SW_MUX_REG SW_MUX_CTL_SD24_SD25_SD26_SD27 #define SD24_BYTE_IN_SW_MUX 3 #define SD25_SW_MUX_REG SW_MUX_CTL_SD24_SD25_SD26_SD27 #define SD25_BYTE_IN_SW_MUX 2 #define SD26_SW_MUX_REG SW_MUX_CTL_SD24_SD25_SD26_SD27 #define SD26_BYTE_IN_SW_MUX 1 #define SD27_SW_MUX_REG SW_MUX_CTL_SD24_SD25_SD26_SD27 #define SD27_BYTE_IN_SW_MUX 0 #define SD28_SW_MUX_REG SW_MUX_CTL_SD28_SD29_SD30_SD31 #define SD28_BYTE_IN_SW_MUX 3 #define SD29_SW_MUX_REG SW_MUX_CTL_SD28_SD29_SD30_SD31 #define SD29_BYTE_IN_SW_MUX 2 #define SD30_SW_MUX_REG SW_MUX_CTL_SD28_SD29_SD30_SD31 #define SD30_BYTE_IN_SW_MUX 1 #define SD31_SW_MUX_REG SW_MUX_CTL_SD28_SD29_SD30_SD31 #define SD31_BYTE_IN_SW_MUX 0 #define DQM0_SW_MUX_REG SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 #define DQM0_BYTE_IN_SW_MUX 3 #define DQM1_SW_MUX_REG SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 #define DQM1_BYTE_IN_SW_MUX 2 #define DQM2_SW_MUX_REG SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 #define DQM2_BYTE_IN_SW_MUX 1 #define DQM3_SW_MUX_REG SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 #define DQM3_BYTE_IN_SW_MUX 0 #define EB0_SW_MUX_REG SW_MUX_CTL_EB0_EB1_OE_CS0 #define EB0_BYTE_IN_SW_MUX 3 #define EB1_SW_MUX_REG SW_MUX_CTL_EB0_EB1_OE_CS0 #define EB1_BYTE_IN_SW_MUX 2 #define OE_SW_MUX_REG SW_MUX_CTL_EB0_EB1_OE_CS0 #define OE_BYTE_IN_SW_MUX 1 #define CS0_SW_MUX_REG SW_MUX_CTL_EB0_EB1_OE_CS0 #define CS0_BYTE_IN_SW_MUX 0 #define CS1_SW_MUX_REG SW_MUX_CTL_CS1_CS2_CS3_CS4 #define CS1_BYTE_IN_SW_MUX 3 #define CS2_SW_MUX_REG SW_MUX_CTL_CS1_CS2_CS3_CS4 #define CS2_BYTE_IN_SW_MUX 2 #define CS3_SW_MUX_REG SW_MUX_CTL_CS1_CS2_CS3_CS4 #define CS3_BYTE_IN_SW_MUX 1 #define CS4_SW_MUX_REG SW_MUX_CTL_CS1_CS2_CS3_CS4 #define CS4_BYTE_IN_SW_MUX 0 #define CS5_SW_MUX_REG SW_MUX_CTL_CS5_ECB_LBA_BCLK #define CS5_BYTE_IN_SW_MUX 3 #define ECB_SW_MUX_REG SW_MUX_CTL_CS5_ECB_LBA_BCLK #define ECB_BYTE_IN_SW_MUX 2 #define LBA_SW_MUX_REG SW_MUX_CTL_CS5_ECB_LBA_BCLK #define LBA_BYTE_IN_SW_MUX 1 #define BCLK_SW_MUX_REG SW_MUX_CTL_CS5_ECB_LBA_BCLK #define BCLK_BYTE_IN_SW_MUX 0 #define RW_SW_MUX_REG SW_MUX_CTL_RW_RAS_CAS_SDWE #define RW_BYTE_IN_SW_MUX 3 #define RAS_SW_MUX_REG SW_MUX_CTL_RW_RAS_CAS_SDWE #define RAS_BYTE_IN_SW_MUX 2 #define CAS_SW_MUX_REG SW_MUX_CTL_RW_RAS_CAS_SDWE #define CAS_BYTE_IN_SW_MUX 1 #define SDWE_SW_MUX_REG SW_MUX_CTL_RW_RAS_CAS_SDWE #define SDWE_BYTE_IN_SW_MUX 0 #define SDCKE0_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B #define SDCKE0_BYTE_IN_SW_MUX 3 #define SDCKE1_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B #define SDCKE1_BYTE_IN_SW_MUX 2 #define SDCLK_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B #define SDCLK_BYTE_IN_SW_MUX 1 #define SDCLK_B_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B #define SDCLK_B_BYTE_IN_SW_MUX 0 #define SDQS0_SW_MUX_REG SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 #define SDQS0_BYTE_IN_SW_MUX 3 #define SDQS1_SW_MUX_REG SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 #define SDQS1_BYTE_IN_SW_MUX 2 #define SDQS2_SW_MUX_REG SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 #define SDQS2_BYTE_IN_SW_MUX 1 #define SDQS3_SW_MUX_REG SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 #define SDQS3_BYTE_IN_SW_MUX 0 #define NFWE_B_SW_MUX_REG SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE #define NFWE_B_BYTE_IN_SW_MUX 3 #define NFRE_B_SW_MUX_REG SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE #define NFRE_B_BYTE_IN_SW_MUX 2 #define NFALE_SW_MUX_REG SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE #define NFALE_BYTE_IN_SW_MUX 1 #define NFCLE_SW_MUX_REG SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE #define NFCLE_BYTE_IN_SW_MUX 0 #define NFWP_B_SW_MUX_REG SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 #define NFWP_B_BYTE_IN_SW_MUX 3 #define NFCE_B_SW_MUX_REG SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 #define NFCE_B_BYTE_IN_SW_MUX 2 #define NFRB_SW_MUX_REG SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 #define NFRB_BYTE_IN_SW_MUX 1 #define D15_SW_MUX_REG SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 #define D15_BYTE_IN_SW_MUX 0 #define D14_SW_MUX_REG SW_MUX_CTL_D14_D13_D12_D11 #define D14_BYTE_IN_SW_MUX 3 #define D13_SW_MUX_REG SW_MUX_CTL_D14_D13_D12_D11 #define D13_BYTE_IN_SW_MUX 2 #define D12_SW_MUX_REG SW_MUX_CTL_D14_D13_D12_D11 #define D12_BYTE_IN_SW_MUX 1 #define D11_SW_MUX_REG SW_MUX_CTL_D14_D13_D12_D11 #define D11_BYTE_IN_SW_MUX 0 #define D10_SW_MUX_REG SW_MUX_CTL_D10_D9_D8_D7 #define D10_BYTE_IN_SW_MUX 3 #define D9_SW_MUX_REG SW_MUX_CTL_D10_D9_D8_D7 #define D9_BYTE_IN_SW_MUX 2 #define D8_SW_MUX_REG SW_MUX_CTL_D10_D9_D8_D7 #define D8_BYTE_IN_SW_MUX 1 #define D7_SW_MUX_REG SW_MUX_CTL_D10_D9_D8_D7 #define D7_BYTE_IN_SW_MUX 0 #define D6_SW_MUX_REG SW_MUX_CTL_D6_D5_D4_D3 #define D6_BYTE_IN_SW_MUX 3 #define D5_SW_MUX_REG SW_MUX_CTL_D6_D5_D4_D3 #define D5_BYTE_IN_SW_MUX 2 #define D4_SW_MUX_REG SW_MUX_CTL_D6_D5_D4_D3 #define D4_BYTE_IN_SW_MUX 1 #define D3_SW_MUX_REG SW_MUX_CTL_D6_D5_D4_D3 #define D3_BYTE_IN_SW_MUX 0 #define D2_SW_MUX_REG SW_MUX_CTL_D2_D1_D0_PC_CD1_B #define D2_BYTE_IN_SW_MUX 3 #define D1_SW_MUX_REG SW_MUX_CTL_D2_D1_D0_PC_CD1_B #define D1_BYTE_IN_SW_MUX 2 #define D0_SW_MUX_REG SW_MUX_CTL_D2_D1_D0_PC_CD1_B #define D0_BYTE_IN_SW_MUX 1 #define PC_CD1_B_SW_MUX_REG SW_MUX_CTL_D2_D1_D0_PC_CD1_B #define PC_CD1_B_BYTE_IN_SW_MUX 0 #define PC_CD2_B_SW_MUX_REG SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON #define PC_CD2_B_BYTE_IN_SW_MUX 3 #define PC_WAIT_B_SW_MUX_REG SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON #define PC_WAIT_B_BYTE_IN_SW_MUX 2 #define PC_READY_SW_MUX_REG SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON #define PC_READY_BYTE_IN_SW_MUX 1 #define PC_PWRON_SW_MUX_REG SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON #define PC_PWRON_BYTE_IN_SW_MUX 0 #define PC_VS1_SW_MUX_REG SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 #define PC_VS1_BYTE_IN_SW_MUX 3 #define PC_VS2_SW_MUX_REG SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 #define PC_VS2_BYTE_IN_SW_MUX 2 #define PC_BVD1_SW_MUX_REG SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 #define PC_BVD1_BYTE_IN_SW_MUX 1 #define PC_BVD2_SW_MUX_REG SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 #define PC_BVD2_BYTE_IN_SW_MUX 0 #define PC_RST_SW_MUX_REG SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE #define PC_RST_BYTE_IN_SW_MUX 3 #define IOIS16_SW_MUX_REG SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE #define IOIS16_BYTE_IN_SW_MUX 2 #define PC_RW_B_SW_MUX_REG SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE #define PC_RW_B_BYTE_IN_SW_MUX 1 #define PC_POE_SW_MUX_REG SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE #define PC_POE_BYTE_IN_SW_MUX 0 #define M_REQUEST_SW_MUX_REG SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 #define M_REQUEST_BYTE_IN_SW_MUX 3 #define M_GRANT_SW_MUX_REG SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 #define M_GRANT_BYTE_IN_SW_MUX 2 #define CSI_D4_SW_MUX_REG SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 #define CSI_D4_BYTE_IN_SW_MUX 1 #define CSI_D5_SW_MUX_REG SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 #define CSI_D5_BYTE_IN_SW_MUX 0 #define CSI_D6_SW_MUX_REG SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 #define CSI_D6_BYTE_IN_SW_MUX 3 #define CSI_D7_SW_MUX_REG SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 #define CSI_D7_BYTE_IN_SW_MUX 2 #define CSI_D8_SW_MUX_REG SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 #define CSI_D8_BYTE_IN_SW_MUX 1 #define CSI_D9_SW_MUX_REG SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 #define CSI_D9_BYTE_IN_SW_MUX 0 #define CSI_D10_SW_MUX_REG SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 #define CSI_D10_BYTE_IN_SW_MUX 3 #define CSI_D11_SW_MUX_REG SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 #define CSI_D11_BYTE_IN_SW_MUX 2 #define CSI_D12_SW_MUX_REG SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 #define CSI_D12_BYTE_IN_SW_MUX 1 #define CSI_D13_SW_MUX_REG SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 #define CSI_D13_BYTE_IN_SW_MUX 0 #define CSI_D14_SW_MUX_REG SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC #define CSI_D14_BYTE_IN_SW_MUX 3 #define CSI_D15_SW_MUX_REG SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC #define CSI_D15_BYTE_IN_SW_MUX 2 #define CSI_MCLK_SW_MUX_REG SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC #define CSI_MCLK_BYTE_IN_SW_MUX 1 #define CSI_VSYNC_SW_MUX_REG SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC #define CSI_VSYNC_BYTE_IN_SW_MUX 0 #define CSI_HSYNC_SW_MUX_REG SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT #define CSI_HSYNC_BYTE_IN_SW_MUX 3 #define CSI_PIXCLK_SW_MUX_REG SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT #define CSI_PIXCLK_BYTE_IN_SW_MUX 2 #define I2C_CLK_SW_MUX_REG SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT #define I2C_CLK_BYTE_IN_SW_MUX 1 #define I2C_DAT_SW_MUX_REG SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT #define I2C_DAT_BYTE_IN_SW_MUX 0 #define STXD3_SW_MUX_REG SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 #define STXD3_BYTE_IN_SW_MUX 3 #define SRXD3_SW_MUX_REG SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 #define SRXD3_BYTE_IN_SW_MUX 2 #define SCK3_SW_MUX_REG SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 #define SCK3_BYTE_IN_SW_MUX 1 #define SFS3_SW_MUX_REG SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 #define SFS3_BYTE_IN_SW_MUX 0 #define STXD4_SW_MUX_REG SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 #define STXD4_BYTE_IN_SW_MUX 3 #define SRXD4_SW_MUX_REG SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 #define SRXD4_BYTE_IN_SW_MUX 2 #define SCK4_SW_MUX_REG SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 #define SCK4_BYTE_IN_SW_MUX 1 #define SFS4_SW_MUX_REG SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 #define SFS4_BYTE_IN_SW_MUX 0 #define STXD5_SW_MUX_REG SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 #define STXD5_BYTE_IN_SW_MUX 3 #define SRXD5_SW_MUX_REG SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 #define SRXD5_BYTE_IN_SW_MUX 2 #define SCK5_SW_MUX_REG SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 #define SCK5_BYTE_IN_SW_MUX 1 #define SFS5_SW_MUX_REG SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 #define SFS5_BYTE_IN_SW_MUX 0 #define STXD6_SW_MUX_REG SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 #define STXD6_BYTE_IN_SW_MUX 3 #define SRXD6_SW_MUX_REG SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 #define SRXD6_BYTE_IN_SW_MUX 2 #define SCK6_SW_MUX_REG SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 #define SCK6_BYTE_IN_SW_MUX 1 #define SFS6_SW_MUX_REG SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 #define SFS6_BYTE_IN_SW_MUX 0 #define CSPI1_MOSI_SW_MUX_REG SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 #define CSPI1_MOSI_BYTE_IN_SW_MUX 3 #define CSPI1_MISO_SW_MUX_REG SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 #define CSPI1_MISO_BYTE_IN_SW_MUX 2 #define CSPI1_SS0_SW_MUX_REG SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 #define CSPI1_SS0_BYTE_IN_SW_MUX 1 #define CSPI1_SS1_SW_MUX_REG SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 #define CSPI1_SS1_BYTE_IN_SW_MUX 0 #define CSPI1_SS2_SW_MUX_REG SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI #define CSPI1_SS2_BYTE_IN_SW_MUX 3 #define CSPI1_SCLK_SW_MUX_REG SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI #define CSPI1_SCLK_BYTE_IN_SW_MUX 2 #define CSPI1_SPI_RDY_SW_MUX_REG SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI #define CSPI1_SPI_RDY_BYTE_IN_SW_MUX 1 #define CSPI2_MOSI_SW_MUX_REG SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI #define CSPI2_MOSI_BYTE_IN_SW_MUX 0 #define CSPI2_MISO_SW_MUX_REG SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 #define CSPI2_MISO_BYTE_IN_SW_MUX 3 #define CSPI2_SS0_SW_MUX_REG SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 #define CSPI2_SS0_BYTE_IN_SW_MUX 2 #define CSPI2_SS1_SW_MUX_REG SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 #define CSPI2_SS1_BYTE_IN_SW_MUX 1 #define CSPI2_SS2_SW_MUX_REG SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 #define CSPI2_SS2_BYTE_IN_SW_MUX 0 #define CSPI2_SCLK_SW_MUX_REG SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 #define CSPI2_SCLK_BYTE_IN_SW_MUX 3 #define CSPI2_SPI_RDY_SW_MUX_REG SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 #define CSPI2_SPI_RDY_BYTE_IN_SW_MUX 2 #define RXD1_SW_MUX_REG SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 #define RXD1_BYTE_IN_SW_MUX 1 #define TXD1_SW_MUX_REG SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 #define TXD1_BYTE_IN_SW_MUX 0 #define RTS1_SW_MUX_REG SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 #define RTS1_BYTE_IN_SW_MUX 3 #define CTS1_SW_MUX_REG SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 #define CTS1_BYTE_IN_SW_MUX 2 #define DTR_DCE1_SW_MUX_REG SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 #define DTR_DCE1_BYTE_IN_SW_MUX 1 #define DSR_DCE1_SW_MUX_REG SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 #define DSR_DCE1_BYTE_IN_SW_MUX 0 #define RI_DCE1_SW_MUX_REG SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 #define RI_DCE1_BYTE_IN_SW_MUX 3 #define DCD_DCE1_SW_MUX_REG SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 #define DCD_DCE1_BYTE_IN_SW_MUX 2 #define DTR_DTE1_SW_MUX_REG SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 #define DTR_DTE1_BYTE_IN_SW_MUX 1 #define DSR_DTE1_SW_MUX_REG SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 #define DSR_DTE1_BYTE_IN_SW_MUX 0 #define RI_DTE1_SW_MUX_REG SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 #define RI_DTE1_BYTE_IN_SW_MUX 3 #define DCD_DTE1_SW_MUX_REG SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 #define DCD_DTE1_BYTE_IN_SW_MUX 2 #define DTR_DCE2_SW_MUX_REG SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 #define DTR_DCE2_BYTE_IN_SW_MUX 1 #define RXD2_SW_MUX_REG SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 #define RXD2_BYTE_IN_SW_MUX 0 #define TXD2_SW_MUX_REG SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE #define TXD2_BYTE_IN_SW_MUX 3 #define RTS2_SW_MUX_REG SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE #define RTS2_BYTE_IN_SW_MUX 2 #define CTS2_SW_MUX_REG SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE #define CTS2_BYTE_IN_SW_MUX 1 #define BATT_LINE_SW_MUX_REG SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE #define BATT_LINE_BYTE_IN_SW_MUX 0 #define KEY_ROW0_SW_MUX_REG SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 #define KEY_ROW0_BYTE_IN_SW_MUX 3 #define KEY_ROW1_SW_MUX_REG SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 #define KEY_ROW1_BYTE_IN_SW_MUX 2 #define KEY_ROW2_SW_MUX_REG SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 #define KEY_ROW2_BYTE_IN_SW_MUX 1 #define KEY_ROW3_SW_MUX_REG SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 #define KEY_ROW3_BYTE_IN_SW_MUX 0 #define KEY_ROW4_SW_MUX_REG SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 #define KEY_ROW4_BYTE_IN_SW_MUX 3 #define KEY_ROW5_SW_MUX_REG SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 #define KEY_ROW5_BYTE_IN_SW_MUX 2 #define KEY_ROW6_SW_MUX_REG SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 #define KEY_ROW6_BYTE_IN_SW_MUX 1 #define KEY_ROW7_SW_MUX_REG SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 #define KEY_ROW7_BYTE_IN_SW_MUX 0 #define KEY_COL0_SW_MUX_REG SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 #define KEY_COL0_BYTE_IN_SW_MUX 3 #define KEY_COL1_SW_MUX_REG SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 #define KEY_COL1_BYTE_IN_SW_MUX 2 #define KEY_COL2_SW_MUX_REG SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 #define KEY_COL2_BYTE_IN_SW_MUX 1 #define KEY_COL3_SW_MUX_REG SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 #define KEY_COL3_BYTE_IN_SW_MUX 0 #define KEY_COL4_SW_MUX_REG SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 #define KEY_COL4_BYTE_IN_SW_MUX 3 #define KEY_COL5_SW_MUX_REG SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 #define KEY_COL5_BYTE_IN_SW_MUX 2 #define KEY_COL6_SW_MUX_REG SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 #define KEY_COL6_BYTE_IN_SW_MUX 1 #define KEY_COL7_SW_MUX_REG SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 #define KEY_COL7_BYTE_IN_SW_MUX 0 #define RTCK_SW_MUX_REG SW_MUX_CTL_RTCK_TCK_TMS_TDI #define RTCK_BYTE_IN_SW_MUX 3 #define TCK_SW_MUX_REG SW_MUX_CTL_RTCK_TCK_TMS_TDI #define TCK_BYTE_IN_SW_MUX 2 #define TMS_SW_MUX_REG SW_MUX_CTL_RTCK_TCK_TMS_TDI #define TMS_BYTE_IN_SW_MUX 1 #define TDI_SW_MUX_REG SW_MUX_CTL_RTCK_TCK_TMS_TDI #define TDI_BYTE_IN_SW_MUX 0 #define TDO_SW_MUX_REG SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD #define TDO_BYTE_IN_SW_MUX 3 #define TRSTB_SW_MUX_REG SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD #define TRSTB_BYTE_IN_SW_MUX 2 #define DE_B_SW_MUX_REG SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD #define DE_B_BYTE_IN_SW_MUX 1 #define SJC_MOD_SW_MUX_REG SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD #define SJC_MOD_BYTE_IN_SW_MUX 0 #define USB_PWR_SW_MUX_REG SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK #define USB_PWR_BYTE_IN_SW_MUX 3 #define USB_OC_SW_MUX_REG SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK #define USB_OC_BYTE_IN_SW_MUX 2 #define USB_BYP_SW_MUX_REG SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK #define USB_BYP_BYTE_IN_SW_MUX 1 #define USBOTG_CLK_SW_MUX_REG SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK #define USBOTG_CLK_BYTE_IN_SW_MUX 0 #define USBOTG_DIR_SW_MUX_REG SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 #define USBOTG_DIR_BYTE_IN_SW_MUX 3 #define USBOTG_STP_SW_MUX_REG SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 #define USBOTG_STP_BYTE_IN_SW_MUX 2 #define USBOTG_NXT_SW_MUX_REG SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 #define USBOTG_NXT_BYTE_IN_SW_MUX 1 #define USBOTG_DATA0_SW_MUX_REG SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 #define USBOTG_DATA0_BYTE_IN_SW_MUX 0 #define USBOTG_DATA1_SW_MUX_REG SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 #define USBOTG_DATA1_BYTE_IN_SW_MUX 3 #define USBOTG_DATA2_SW_MUX_REG SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 #define USBOTG_DATA2_BYTE_IN_SW_MUX 2 #define USBOTG_DATA3_SW_MUX_REG SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 #define USBOTG_DATA3_BYTE_IN_SW_MUX 1 #define USBOTG_DATA4_SW_MUX_REG SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 #define USBOTG_DATA4_BYTE_IN_SW_MUX 0 #define USBOTG_DATA5_SW_MUX_REG SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK #define USBOTG_DATA5_BYTE_IN_SW_MUX 3 #define USBOTG_DATA6_SW_MUX_REG SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK #define USBOTG_DATA6_BYTE_IN_SW_MUX 2 #define USBOTG_DATA7_SW_MUX_REG SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK #define USBOTG_DATA7_BYTE_IN_SW_MUX 1 #define USBH2_CLK_SW_MUX_REG SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK #define USBH2_CLK_BYTE_IN_SW_MUX 0 #define USBH2_DIR_SW_MUX_REG SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 #define USBH2_DIR_BYTE_IN_SW_MUX 3 #define USBH2_STP_SW_MUX_REG SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 #define USBH2_STP_BYTE_IN_SW_MUX 2 #define USBH2_NXT_SW_MUX_REG SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 #define USBH2_NXT_BYTE_IN_SW_MUX 1 #define USBH2_DATA0_SW_MUX_REG SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 #define USBH2_DATA0_BYTE_IN_SW_MUX 0 #define USBH2_DATA1_SW_MUX_REG SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 #define USBH2_DATA1_BYTE_IN_SW_MUX 3 #define LD0_SW_MUX_REG SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 #define LD0_BYTE_IN_SW_MUX 2 #define LD1_SW_MUX_REG SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 #define LD1_BYTE_IN_SW_MUX 1 #define LD2_SW_MUX_REG SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 #define LD2_BYTE_IN_SW_MUX 0 #define LD3_SW_MUX_REG SW_MUX_CTL_LD3_LD4_LD5_LD6 #define LD3_BYTE_IN_SW_MUX 3 #define LD4_SW_MUX_REG SW_MUX_CTL_LD3_LD4_LD5_LD6 #define LD4_BYTE_IN_SW_MUX 2 #define LD5_SW_MUX_REG SW_MUX_CTL_LD3_LD4_LD5_LD6 #define LD5_BYTE_IN_SW_MUX 1 #define LD6_SW_MUX_REG SW_MUX_CTL_LD3_LD4_LD5_LD6 #define LD6_BYTE_IN_SW_MUX 0 #define LD7_SW_MUX_REG SW_MUX_CTL_LD7_LD8_LD9_LD10 #define LD7_BYTE_IN_SW_MUX 3 #define LD8_SW_MUX_REG SW_MUX_CTL_LD7_LD8_LD9_LD10 #define LD8_BYTE_IN_SW_MUX 2 #define LD9_SW_MUX_REG SW_MUX_CTL_LD7_LD8_LD9_LD10 #define LD9_BYTE_IN_SW_MUX 1 #define LD10_SW_MUX_REG SW_MUX_CTL_LD7_LD8_LD9_LD10 #define LD10_BYTE_IN_SW_MUX 0 #define LD11_SW_MUX_REG SW_MUX_CTL_LD11_LD12_LD13_LD14 #define LD11_BYTE_IN_SW_MUX 3 #define LD12_SW_MUX_REG SW_MUX_CTL_LD11_LD12_LD13_LD14 #define LD12_BYTE_IN_SW_MUX 2 #define LD13_SW_MUX_REG SW_MUX_CTL_LD11_LD12_LD13_LD14 #define LD13_BYTE_IN_SW_MUX 1 #define LD14_SW_MUX_REG SW_MUX_CTL_LD11_LD12_LD13_LD14 #define LD14_BYTE_IN_SW_MUX 0 #define LD15_SW_MUX_REG SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 #define LD15_BYTE_IN_SW_MUX 3 #define LD16_SW_MUX_REG SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 #define LD16_BYTE_IN_SW_MUX 2 #define LD17_SW_MUX_REG SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 #define LD17_BYTE_IN_SW_MUX 1 #define VSYNC0_SW_MUX_REG SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 #define VSYNC0_BYTE_IN_SW_MUX 0 #define HSYNC_SW_MUX_REG SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I #define HSYNC_BYTE_IN_SW_MUX 3 #define FPSHIFT_SW_MUX_REG SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I #define FPSHIFT_BYTE_IN_SW_MUX 2 #define DRDY0_SW_MUX_REG SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I #define DRDY0_BYTE_IN_SW_MUX 1 #define SD_D_I_SW_MUX_REG SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I #define SD_D_I_BYTE_IN_SW_MUX 0 #define SD_D_IO_SW_MUX_REG SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 #define SD_D_IO_BYTE_IN_SW_MUX 3 #define SD_D_CLK_SW_MUX_REG SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 #define SD_D_CLK_BYTE_IN_SW_MUX 2 #define LCS0_SW_MUX_REG SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 #define LCS0_BYTE_IN_SW_MUX 1 #define LCS1_SW_MUX_REG SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 #define LCS1_BYTE_IN_SW_MUX 0 #define SER_RS_SW_MUX_REG SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ #define SER_RS_BYTE_IN_SW_MUX 3 #define PAR_RS_SW_MUX_REG SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ #define PAR_RS_BYTE_IN_SW_MUX 2 #define WRITE_SW_MUX_REG SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ #define WRITE_BYTE_IN_SW_MUX 1 #define READ_SW_MUX_REG SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ #define READ_BYTE_IN_SW_MUX 0 #define VSYNC3_SW_MUX_REG SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS #define VSYNC3_BYTE_IN_SW_MUX 3 #define CONTRAST_SW_MUX_REG SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS #define CONTRAST_BYTE_IN_SW_MUX 2 #define D3_REV_SW_MUX_REG SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS #define D3_REV_BYTE_IN_SW_MUX 1 #define D3_CLS_SW_MUX_REG SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS #define D3_CLS_BYTE_IN_SW_MUX 0 #define D3_SPL_SW_MUX_REG SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 #define D3_SPL_BYTE_IN_SW_MUX 3 #define SD1_CMD_SW_MUX_REG SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 #define SD1_CMD_BYTE_IN_SW_MUX 2 #define SD1_CLK_SW_MUX_REG SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 #define SD1_CLK_BYTE_IN_SW_MUX 1 #define SD1_DATA0_SW_MUX_REG SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 #define SD1_DATA0_BYTE_IN_SW_MUX 0 #define SD1_DATA1_SW_MUX_REG SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 #define SD1_DATA1_BYTE_IN_SW_MUX 3 #define SD1_DATA2_SW_MUX_REG SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 #define SD1_DATA2_BYTE_IN_SW_MUX 2 #define SD1_DATA3_SW_MUX_REG SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 #define SD1_DATA3_BYTE_IN_SW_MUX 1 #define ATA_CS0_SW_MUX_REG SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 #define ATA_CS0_BYTE_IN_SW_MUX 0 #define ATA_CS1_SW_MUX_REG SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK #define ATA_CS1_BYTE_IN_SW_MUX 3 #define ATA_DIOR_SW_MUX_REG SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK #define ATA_DIOR_BYTE_IN_SW_MUX 2 #define ATA_DIOW_SW_MUX_REG SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK #define ATA_DIOW_BYTE_IN_SW_MUX 1 #define ATA_DMACK_SW_MUX_REG SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK #define ATA_DMACK_BYTE_IN_SW_MUX 0 #define ATA_RESET_B_SW_MUX_REG SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI #define ATA_RESET_B_BYTE_IN_SW_MUX 3 #define CE_CONTROL_SW_MUX_REG SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI #define CE_CONTROL_BYTE_IN_SW_MUX 2 #define CLKSS_SW_MUX_REG SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI #define CLKSS_BYTE_IN_SW_MUX 1 #define CSPI3_MOSI_SW_MUX_REG SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI #define CSPI3_MOSI_BYTE_IN_SW_MUX 0 #define CSPI3_MISO_SW_MUX_REG SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD #define CSPI3_MISO_BYTE_IN_SW_MUX 3 #define CSPI3_SCLK_SW_MUX_REG SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD #define CSPI3_SCLK_BYTE_IN_SW_MUX 2 #define CSPI3_SPI_RDY_SW_MUX_REG SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD #define CSPI3_SPI_RDY_BYTE_IN_SW_MUX 1 #define TTM_PAD_SW_MUX_REG SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD #define TTM_PAD_BYTE_IN_SW_MUX 0 // SW_PAD_CTL defines : // ###################### #define CAPTURE_SW_PAD_REG SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST #define CAPTURE_BYTE_IN_SW_PAD 2 #define COMPARE_SW_PAD_REG SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST #define COMPARE_BYTE_IN_SW_PAD 1 #define WATCHDOG_RST_SW_PAD_REG SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST #define WATCHDOG_RST_BYTE_IN_SW_PAD 0 #define PWMO_SW_PAD_REG SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1 #define PWMO_BYTE_IN_SW_PAD 2 #define GPIO1_0_SW_PAD_REG SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1 #define GPIO1_0_BYTE_IN_SW_PAD 1 #define GPIO1_1_SW_PAD_REG SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1 #define GPIO1_1_BYTE_IN_SW_PAD 0 #define GPIO1_2_SW_PAD_REG SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4 #define GPIO1_2_BYTE_IN_SW_PAD 2 #define GPIO1_3_SW_PAD_REG SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4 #define GPIO1_3_BYTE_IN_SW_PAD 1 #define GPIO1_4_SW_PAD_REG SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4 #define GPIO1_4_BYTE_IN_SW_PAD 0 #define GPIO1_5_SW_PAD_REG SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0 #define GPIO1_5_BYTE_IN_SW_PAD 2 #define GPIO1_6_SW_PAD_REG SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0 #define GPIO1_6_BYTE_IN_SW_PAD 1 #define GPIO3_0_SW_PAD_REG SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0 #define GPIO3_0_BYTE_IN_SW_PAD 0 #define GPIO3_1_SW_PAD_REG SW_PAD_CTL_GPIO3_1_SCLK0_SRST0 #define GPIO3_1_BYTE_IN_SW_PAD 2 #define SCLK0_SW_PAD_REG SW_PAD_CTL_GPIO3_1_SCLK0_SRST0 #define SCLK0_BYTE_IN_SW_PAD 1 #define SRST0_SW_PAD_REG SW_PAD_CTL_GPIO3_1_SCLK0_SRST0 #define SRST0_BYTE_IN_SW_PAD 0 #define SVEN0_SW_PAD_REG SW_PAD_CTL_SVEN0_STX0_SRX0 #define SVEN0_BYTE_IN_SW_PAD 2 #define STX0_SW_PAD_REG SW_PAD_CTL_SVEN0_STX0_SRX0 #define STX0_BYTE_IN_SW_PAD 1 #define SRX0_SW_PAD_REG SW_PAD_CTL_SVEN0_STX0_SRX0 #define SRX0_BYTE_IN_SW_PAD 0 #define SIMPD0_SW_PAD_REG SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B #define SIMPD0_BYTE_IN_SW_PAD 2 #define CKIH_SW_PAD_REG SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B #define CKIH_BYTE_IN_SW_PAD 1 #define RESET_IN_B_SW_PAD_REG SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B #define RESET_IN_B_BYTE_IN_SW_PAD 0 #define POR_B_SW_PAD_REG SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0 #define POR_B_BYTE_IN_SW_PAD 2 #define CLKO_SW_PAD_REG SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0 #define CLKO_BYTE_IN_SW_PAD 1 #define BOOT_MODE0_SW_PAD_REG SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0 #define BOOT_MODE0_BYTE_IN_SW_PAD 0 #define BOOT_MODE1_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3 #define BOOT_MODE1_BYTE_IN_SW_PAD 2 #define BOOT_MODE2_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3 #define BOOT_MODE2_BYTE_IN_SW_PAD 1 #define BOOT_MODE3_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3 #define BOOT_MODE3_BYTE_IN_SW_PAD 0 #define BOOT_MODE4_SW_PAD_REG SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL #define BOOT_MODE4_BYTE_IN_SW_PAD 2 #define CKIL_SW_PAD_REG SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL #define CKIL_BYTE_IN_SW_PAD 1 #define POWER_FAIL_SW_PAD_REG SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL #define POWER_FAIL_BYTE_IN_SW_PAD 0 #define VSTBY_SW_PAD_REG SW_PAD_CTL_VSTBY_DVFS0_DVFS1 #define VSTBY_BYTE_IN_SW_PAD 2 #define DVFS0_SW_PAD_REG SW_PAD_CTL_VSTBY_DVFS0_DVFS1 #define DVFS0_BYTE_IN_SW_PAD 1 #define DVFS1_SW_PAD_REG SW_PAD_CTL_VSTBY_DVFS0_DVFS1 #define DVFS1_BYTE_IN_SW_PAD 0 #define VPG0_SW_PAD_REG SW_PAD_CTL_VPG0_VPG1_A0 #define VPG0_BYTE_IN_SW_PAD 2 #define VPG1_SW_PAD_REG SW_PAD_CTL_VPG0_VPG1_A0 #define VPG1_BYTE_IN_SW_PAD 1 #define A0_SW_PAD_REG SW_PAD_CTL_VPG0_VPG1_A0 #define A0_BYTE_IN_SW_PAD 0 #define A1_SW_PAD_REG SW_PAD_CTL_A1_A2_A3 #define A1_BYTE_IN_SW_PAD 2 #define A2_SW_PAD_REG SW_PAD_CTL_A1_A2_A3 #define A2_BYTE_IN_SW_PAD 1 #define A3_SW_PAD_REG SW_PAD_CTL_A1_A2_A3 #define A3_BYTE_IN_SW_PAD 0 #define A4_SW_PAD_REG SW_PAD_CTL_A4_A5_A6 #define A4_BYTE_IN_SW_PAD 2 #define A5_SW_PAD_REG SW_PAD_CTL_A4_A5_A6 #define A5_BYTE_IN_SW_PAD 1 #define A6_SW_PAD_REG SW_PAD_CTL_A4_A5_A6 #define A6_BYTE_IN_SW_PAD 0 #define A7_SW_PAD_REG SW_PAD_CTL_A7_A8_A9 #define A7_BYTE_IN_SW_PAD 2 #define A8_SW_PAD_REG SW_PAD_CTL_A7_A8_A9 #define A8_BYTE_IN_SW_PAD 1 #define A9_SW_PAD_REG SW_PAD_CTL_A7_A8_A9 #define A9_BYTE_IN_SW_PAD 0 #define A10_SW_PAD_REG SW_PAD_CTL_A10_MA10_A11 #define A10_BYTE_IN_SW_PAD 2 #define MA10_SW_PAD_REG SW_PAD_CTL_A10_MA10_A11 #define MA10_BYTE_IN_SW_PAD 1 #define A11_SW_PAD_REG SW_PAD_CTL_A10_MA10_A11 #define A11_BYTE_IN_SW_PAD 0 #define A12_SW_PAD_REG SW_PAD_CTL_A12_A13_A14 #define A12_BYTE_IN_SW_PAD 2 #define A13_SW_PAD_REG SW_PAD_CTL_A12_A13_A14 #define A13_BYTE_IN_SW_PAD 1 #define A14_SW_PAD_REG SW_PAD_CTL_A12_A13_A14 #define A14_BYTE_IN_SW_PAD 0 #define A15_SW_PAD_REG SW_PAD_CTL_A15_A16_A17 #define A15_BYTE_IN_SW_PAD 2 #define A16_SW_PAD_REG SW_PAD_CTL_A15_A16_A17 #define A16_BYTE_IN_SW_PAD 1 #define A17_SW_PAD_REG SW_PAD_CTL_A15_A16_A17 #define A17_BYTE_IN_SW_PAD 0 #define A18_SW_PAD_REG SW_PAD_CTL_A18_A19_A20 #define A18_BYTE_IN_SW_PAD 2 #define A19_SW_PAD_REG SW_PAD_CTL_A18_A19_A20 #define A19_BYTE_IN_SW_PAD 1 #define A20_SW_PAD_REG SW_PAD_CTL_A18_A19_A20 #define A20_BYTE_IN_SW_PAD 0 #define A21_SW_PAD_REG SW_PAD_CTL_A21_A22_A23 #define A21_BYTE_IN_SW_PAD 2 #define A22_SW_PAD_REG SW_PAD_CTL_A21_A22_A23 #define A22_BYTE_IN_SW_PAD 1 #define A23_SW_PAD_REG SW_PAD_CTL_A21_A22_A23 #define A23_BYTE_IN_SW_PAD 0 #define A24_SW_PAD_REG SW_PAD_CTL_A24_A25_SDBA1 #define A24_BYTE_IN_SW_PAD 2 #define A25_SW_PAD_REG SW_PAD_CTL_A24_A25_SDBA1 #define A25_BYTE_IN_SW_PAD 1 #define SDBA1_SW_PAD_REG SW_PAD_CTL_A24_A25_SDBA1 #define SDBA1_BYTE_IN_SW_PAD 0 #define SDBA0_SW_PAD_REG SW_PAD_CTL_SDBA0_SD0_SD1 #define SDBA0_BYTE_IN_SW_PAD 2 #define SD0_SW_PAD_REG SW_PAD_CTL_SDBA0_SD0_SD1 #define SD0_BYTE_IN_SW_PAD 1 #define SD1_SW_PAD_REG SW_PAD_CTL_SDBA0_SD0_SD1 #define SD1_BYTE_IN_SW_PAD 0 #define SD2_SW_PAD_REG SW_PAD_CTL_SD2_SD3_SD4 #define SD2_BYTE_IN_SW_PAD 2 #define SD3_SW_PAD_REG SW_PAD_CTL_SD2_SD3_SD4 #define SD3_BYTE_IN_SW_PAD 1 #define SD4_SW_PAD_REG SW_PAD_CTL_SD2_SD3_SD4 #define SD4_BYTE_IN_SW_PAD 0 #define SD5_SW_PAD_REG SW_PAD_CTL_SD5_SD6_SD7 #define SD5_BYTE_IN_SW_PAD 2 #define SD6_SW_PAD_REG SW_PAD_CTL_SD5_SD6_SD7 #define SD6_BYTE_IN_SW_PAD 1 #define SD7_SW_PAD_REG SW_PAD_CTL_SD5_SD6_SD7 #define SD7_BYTE_IN_SW_PAD 0 #define SD8_SW_PAD_REG SW_PAD_CTL_SD8_SD9_SD10 #define SD8_BYTE_IN_SW_PAD 2 #define SD9_SW_PAD_REG SW_PAD_CTL_SD8_SD9_SD10 #define SD9_BYTE_IN_SW_PAD 1 #define SD10_SW_PAD_REG SW_PAD_CTL_SD8_SD9_SD10 #define SD10_BYTE_IN_SW_PAD 0 #define SD11_SW_PAD_REG SW_PAD_CTL_SD11_SD12_SD13 #define SD11_BYTE_IN_SW_PAD 2 #define SD12_SW_PAD_REG SW_PAD_CTL_SD11_SD12_SD13 #define SD12_BYTE_IN_SW_PAD 1 #define SD13_SW_PAD_REG SW_PAD_CTL_SD11_SD12_SD13 #define SD13_BYTE_IN_SW_PAD 0 #define SD14_SW_PAD_REG SW_PAD_CTL_SD14_SD15_SD16 #define SD14_BYTE_IN_SW_PAD 2 #define SD15_SW_PAD_REG SW_PAD_CTL_SD14_SD15_SD16 #define SD15_BYTE_IN_SW_PAD 1 #define SD16_SW_PAD_REG SW_PAD_CTL_SD14_SD15_SD16 #define SD16_BYTE_IN_SW_PAD 0 #define SD17_SW_PAD_REG SW_PAD_CTL_SD17_SD18_SD19 #define SD17_BYTE_IN_SW_PAD 2 #define SD18_SW_PAD_REG SW_PAD_CTL_SD17_SD18_SD19 #define SD18_BYTE_IN_SW_PAD 1 #define SD19_SW_PAD_REG SW_PAD_CTL_SD17_SD18_SD19 #define SD19_BYTE_IN_SW_PAD 0 #define SD20_SW_PAD_REG SW_PAD_CTL_SD20_SD21_SD22 #define SD20_BYTE_IN_SW_PAD 2 #define SD21_SW_PAD_REG SW_PAD_CTL_SD20_SD21_SD22 #define SD21_BYTE_IN_SW_PAD 1 #define SD22_SW_PAD_REG SW_PAD_CTL_SD20_SD21_SD22 #define SD22_BYTE_IN_SW_PAD 0 #define SD23_SW_PAD_REG SW_PAD_CTL_SD23_SD24_SD25 #define SD23_BYTE_IN_SW_PAD 2 #define SD24_SW_PAD_REG SW_PAD_CTL_SD23_SD24_SD25 #define SD24_BYTE_IN_SW_PAD 1 #define SD25_SW_PAD_REG SW_PAD_CTL_SD23_SD24_SD25 #define SD25_BYTE_IN_SW_PAD 0 #define SD26_SW_PAD_REG SW_PAD_CTL_SD26_SD27_SD28 #define SD26_BYTE_IN_SW_PAD 2 #define SD27_SW_PAD_REG SW_PAD_CTL_SD26_SD27_SD28 #define SD27_BYTE_IN_SW_PAD 1 #define SD28_SW_PAD_REG SW_PAD_CTL_SD26_SD27_SD28 #define SD28_BYTE_IN_SW_PAD 0 #define SD29_SW_PAD_REG SW_PAD_CTL_SD29_SD30_SD31 #define SD29_BYTE_IN_SW_PAD 2 #define SD30_SW_PAD_REG SW_PAD_CTL_SD29_SD30_SD31 #define SD30_BYTE_IN_SW_PAD 1 #define SD31_SW_PAD_REG SW_PAD_CTL_SD29_SD30_SD31 #define SD31_BYTE_IN_SW_PAD 0 #define DQM0_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2 #define DQM0_BYTE_IN_SW_PAD 2 #define DQM1_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2 #define DQM1_BYTE_IN_SW_PAD 1 #define DQM2_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2 #define DQM2_BYTE_IN_SW_PAD 0 #define DQM3_SW_PAD_REG SW_PAD_CTL_DQM3_EB0_EB1 #define DQM3_BYTE_IN_SW_PAD 2 #define EB0_SW_PAD_REG SW_PAD_CTL_DQM3_EB0_EB1 #define EB0_BYTE_IN_SW_PAD 1 #define EB1_SW_PAD_REG SW_PAD_CTL_DQM3_EB0_EB1 #define EB1_BYTE_IN_SW_PAD 0 #define OE_SW_PAD_REG SW_PAD_CTL_OE_CS0_CS1 #define OE_BYTE_IN_SW_PAD 2 #define CS0_SW_PAD_REG SW_PAD_CTL_OE_CS0_CS1 #define CS0_BYTE_IN_SW_PAD 1 #define CS1_SW_PAD_REG SW_PAD_CTL_OE_CS0_CS1 #define CS1_BYTE_IN_SW_PAD 0 #define CS2_SW_PAD_REG SW_PAD_CTL_CS2_CS3_CS4 #define CS2_BYTE_IN_SW_PAD 2 #define CS3_SW_PAD_REG SW_PAD_CTL_CS2_CS3_CS4 #define CS3_BYTE_IN_SW_PAD 1 #define CS4_SW_PAD_REG SW_PAD_CTL_CS2_CS3_CS4 #define CS4_BYTE_IN_SW_PAD 0 #define CS5_SW_PAD_REG SW_PAD_CTL_CS5_ECB_LBA #define CS5_BYTE_IN_SW_PAD 2 #define ECB_SW_PAD_REG SW_PAD_CTL_CS5_ECB_LBA #define ECB_BYTE_IN_SW_PAD 1 #define LBA_SW_PAD_REG SW_PAD_CTL_CS5_ECB_LBA #define LBA_BYTE_IN_SW_PAD 0 #define BCLK_SW_PAD_REG SW_PAD_CTL_BCLK_RW_RAS #define BCLK_BYTE_IN_SW_PAD 2 #define RW_SW_PAD_REG SW_PAD_CTL_BCLK_RW_RAS #define RW_BYTE_IN_SW_PAD 1 #define RAS_SW_PAD_REG SW_PAD_CTL_BCLK_RW_RAS #define RAS_BYTE_IN_SW_PAD 0 #define CAS_SW_PAD_REG SW_PAD_CTL_CAS_SDWE_SDCKE0 #define CAS_BYTE_IN_SW_PAD 2 #define SDWE_SW_PAD_REG SW_PAD_CTL_CAS_SDWE_SDCKE0 #define SDWE_BYTE_IN_SW_PAD 1 #define SDCKE0_SW_PAD_REG SW_PAD_CTL_CAS_SDWE_SDCKE0 #define SDCKE0_BYTE_IN_SW_PAD 0 #define SDCKE1_SW_PAD_REG SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B #define SDCKE1_BYTE_IN_SW_PAD 2 #define SDCLK_SW_PAD_REG SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B #define SDCLK_BYTE_IN_SW_PAD 1 #define SDCLK_B_SW_PAD_REG SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B #define SDCLK_B_BYTE_IN_SW_PAD 0 #define SDQS0_SW_PAD_REG SW_PAD_CTL_SDQS0_SDQS1_SDQS2 #define SDQS0_BYTE_IN_SW_PAD 2 #define SDQS1_SW_PAD_REG SW_PAD_CTL_SDQS0_SDQS1_SDQS2 #define SDQS1_BYTE_IN_SW_PAD 1 #define SDQS2_SW_PAD_REG SW_PAD_CTL_SDQS0_SDQS1_SDQS2 #define SDQS2_BYTE_IN_SW_PAD 0 #define SDQS3_SW_PAD_REG SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B #define SDQS3_BYTE_IN_SW_PAD 2 #define NFWE_B_SW_PAD_REG SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B #define NFWE_B_BYTE_IN_SW_PAD 1 #define NFRE_B_SW_PAD_REG SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B #define NFRE_B_BYTE_IN_SW_PAD 0 #define NFALE_SW_PAD_REG SW_PAD_CTL_NFALE_NFCLE_NFWP_B #define NFALE_BYTE_IN_SW_PAD 2 #define NFCLE_SW_PAD_REG SW_PAD_CTL_NFALE_NFCLE_NFWP_B #define NFCLE_BYTE_IN_SW_PAD 1 #define NFWP_B_SW_PAD_REG SW_PAD_CTL_NFALE_NFCLE_NFWP_B #define NFWP_B_BYTE_IN_SW_PAD 0 #define NFCE_B_SW_PAD_REG SW_PAD_CTL_NFCE_B_NFRB_D15 #define NFCE_B_BYTE_IN_SW_PAD 2 #define NFRB_SW_PAD_REG SW_PAD_CTL_NFCE_B_NFRB_D15 #define NFRB_BYTE_IN_SW_PAD 1 #define D15_SW_PAD_REG SW_PAD_CTL_NFCE_B_NFRB_D15 #define D15_BYTE_IN_SW_PAD 0 #define D14_SW_PAD_REG SW_PAD_CTL_D14_D13_D12 #define D14_BYTE_IN_SW_PAD 2 #define D13_SW_PAD_REG SW_PAD_CTL_D14_D13_D12 #define D13_BYTE_IN_SW_PAD 1 #define D12_SW_PAD_REG SW_PAD_CTL_D14_D13_D12 #define D12_BYTE_IN_SW_PAD 0 #define D11_SW_PAD_REG SW_PAD_CTL_D11_D10_D9 #define D11_BYTE_IN_SW_PAD 2 #define D10_SW_PAD_REG SW_PAD_CTL_D11_D10_D9 #define D10_BYTE_IN_SW_PAD 1 #define D9_SW_PAD_REG SW_PAD_CTL_D11_D10_D9 #define D9_BYTE_IN_SW_PAD 0 #define D8_SW_PAD_REG SW_PAD_CTL_D8_D7_D6 #define D8_BYTE_IN_SW_PAD 2 #define D7_SW_PAD_REG SW_PAD_CTL_D8_D7_D6 #define D7_BYTE_IN_SW_PAD 1 #define D6_SW_PAD_REG SW_PAD_CTL_D8_D7_D6 #define D6_BYTE_IN_SW_PAD 0 #define D5_SW_PAD_REG SW_PAD_CTL_D5_D4_D3 #define D5_BYTE_IN_SW_PAD 2 #define D4_SW_PAD_REG SW_PAD_CTL_D5_D4_D3 #define D4_BYTE_IN_SW_PAD 1 #define D3_SW_PAD_REG SW_PAD_CTL_D5_D4_D3 #define D3_BYTE_IN_SW_PAD 0 #define D2_SW_PAD_REG SW_PAD_CTL_D2_D1_D0 #define D2_BYTE_IN_SW_PAD 2 #define D1_SW_PAD_REG SW_PAD_CTL_D2_D1_D0 #define D1_BYTE_IN_SW_PAD 1 #define D0_SW_PAD_REG SW_PAD_CTL_D2_D1_D0 #define D0_BYTE_IN_SW_PAD 0 #define PC_CD1_B_SW_PAD_REG SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B #define PC_CD1_B_BYTE_IN_SW_PAD 2 #define PC_CD2_B_SW_PAD_REG SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B #define PC_CD2_B_BYTE_IN_SW_PAD 1 #define PC_WAIT_B_SW_PAD_REG SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B #define PC_WAIT_B_BYTE_IN_SW_PAD 0 #define PC_READY_SW_PAD_REG SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1 #define PC_READY_BYTE_IN_SW_PAD 2 #define PC_PWRON_SW_PAD_REG SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1 #define PC_PWRON_BYTE_IN_SW_PAD 1 #define PC_VS1_SW_PAD_REG SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1 #define PC_VS1_BYTE_IN_SW_PAD 0 #define PC_VS2_SW_PAD_REG SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2 #define PC_VS2_BYTE_IN_SW_PAD 2 #define PC_BVD1_SW_PAD_REG SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2 #define PC_BVD1_BYTE_IN_SW_PAD 1 #define PC_BVD2_SW_PAD_REG SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2 #define PC_BVD2_BYTE_IN_SW_PAD 0 #define PC_RST_SW_PAD_REG SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B #define PC_RST_BYTE_IN_SW_PAD 2 #define IOIS16_SW_PAD_REG SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B #define IOIS16_BYTE_IN_SW_PAD 1 #define PC_RW_B_SW_PAD_REG SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B #define PC_RW_B_BYTE_IN_SW_PAD 0 #define PC_POE_SW_PAD_REG SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT #define PC_POE_BYTE_IN_SW_PAD 2 #define M_REQUEST_SW_PAD_REG SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT #define M_REQUEST_BYTE_IN_SW_PAD 1 #define M_GRANT_SW_PAD_REG SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT #define M_GRANT_BYTE_IN_SW_PAD 0 #define CSI_D4_SW_PAD_REG SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6 #define CSI_D4_BYTE_IN_SW_PAD 2 #define CSI_D5_SW_PAD_REG SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6 #define CSI_D5_BYTE_IN_SW_PAD 1 #define CSI_D6_SW_PAD_REG SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6 #define CSI_D6_BYTE_IN_SW_PAD 0 #define CSI_D7_SW_PAD_REG SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9 #define CSI_D7_BYTE_IN_SW_PAD 2 #define CSI_D8_SW_PAD_REG SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9 #define CSI_D8_BYTE_IN_SW_PAD 1 #define CSI_D9_SW_PAD_REG SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9 #define CSI_D9_BYTE_IN_SW_PAD 0 #define CSI_D10_SW_PAD_REG SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12 #define CSI_D10_BYTE_IN_SW_PAD 2 #define CSI_D11_SW_PAD_REG SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12 #define CSI_D11_BYTE_IN_SW_PAD 1 #define CSI_D12_SW_PAD_REG SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12 #define CSI_D12_BYTE_IN_SW_PAD 0 #define CSI_D13_SW_PAD_REG SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15 #define CSI_D13_BYTE_IN_SW_PAD 2 #define CSI_D14_SW_PAD_REG SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15 #define CSI_D14_BYTE_IN_SW_PAD 1 #define CSI_D15_SW_PAD_REG SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15 #define CSI_D15_BYTE_IN_SW_PAD 0 #define CSI_MCLK_SW_PAD_REG SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC #define CSI_MCLK_BYTE_IN_SW_PAD 2 #define CSI_VSYNC_SW_PAD_REG SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC #define CSI_VSYNC_BYTE_IN_SW_PAD 1 #define CSI_HSYNC_SW_PAD_REG SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC #define CSI_HSYNC_BYTE_IN_SW_PAD 0 #define CSI_PIXCLK_SW_PAD_REG SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT #define CSI_PIXCLK_BYTE_IN_SW_PAD 2 #define I2C_CLK_SW_PAD_REG SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT #define I2C_CLK_BYTE_IN_SW_PAD 1 #define I2C_DAT_SW_PAD_REG SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT #define I2C_DAT_BYTE_IN_SW_PAD 0 #define STXD3_SW_PAD_REG SW_PAD_CTL_STXD3_SRXD3_SCK3 #define STXD3_BYTE_IN_SW_PAD 2 #define SRXD3_SW_PAD_REG SW_PAD_CTL_STXD3_SRXD3_SCK3 #define SRXD3_BYTE_IN_SW_PAD 1 #define SCK3_SW_PAD_REG SW_PAD_CTL_STXD3_SRXD3_SCK3 #define SCK3_BYTE_IN_SW_PAD 0 #define SFS3_SW_PAD_REG SW_PAD_CTL_SFS3_STXD4_SRXD4 #define SFS3_BYTE_IN_SW_PAD 2 #define STXD4_SW_PAD_REG SW_PAD_CTL_SFS3_STXD4_SRXD4 #define STXD4_BYTE_IN_SW_PAD 1 #define SRXD4_SW_PAD_REG SW_PAD_CTL_SFS3_STXD4_SRXD4 #define SRXD4_BYTE_IN_SW_PAD 0 #define SCK4_SW_PAD_REG SW_PAD_CTL_SCK4_SFS4_STXD5 #define SCK4_BYTE_IN_SW_PAD 2 #define SFS4_SW_PAD_REG SW_PAD_CTL_SCK4_SFS4_STXD5 #define SFS4_BYTE_IN_SW_PAD 1 #define STXD5_SW_PAD_REG SW_PAD_CTL_SCK4_SFS4_STXD5 #define STXD5_BYTE_IN_SW_PAD 0 #define SRXD5_SW_PAD_REG SW_PAD_CTL_SRXD5_SCK5_SFS5 #define SRXD5_BYTE_IN_SW_PAD 2 #define SCK5_SW_PAD_REG SW_PAD_CTL_SRXD5_SCK5_SFS5 #define SCK5_BYTE_IN_SW_PAD 1 #define SFS5_SW_PAD_REG SW_PAD_CTL_SRXD5_SCK5_SFS5 #define SFS5_BYTE_IN_SW_PAD 0 #define STXD6_SW_PAD_REG SW_PAD_CTL_STXD6_SRXD6_SCK6 #define STXD6_BYTE_IN_SW_PAD 2 #define SRXD6_SW_PAD_REG SW_PAD_CTL_STXD6_SRXD6_SCK6 #define SRXD6_BYTE_IN_SW_PAD 1 #define SCK6_SW_PAD_REG SW_PAD_CTL_STXD6_SRXD6_SCK6 #define SCK6_BYTE_IN_SW_PAD 0 #define SFS6_SW_PAD_REG SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO #define SFS6_BYTE_IN_SW_PAD 2 #define CSPI1_MOSI_SW_PAD_REG SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO #define CSPI1_MOSI_BYTE_IN_SW_PAD 1 #define CSPI1_MISO_SW_PAD_REG SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO #define CSPI1_MISO_BYTE_IN_SW_PAD 0 #define CSPI1_SS0_SW_PAD_REG SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS2 #define CSPI1_SS0_BYTE_IN_SW_PAD 2 #define CSPI1_SS1_SW_PAD_REG SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS2 #define CSPI1_SS1_BYTE_IN_SW_PAD 1 #define CSPI1_SS2_SW_PAD_REG SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS2 #define CSPI1_SS2_BYTE_IN_SW_PAD 0 #define CSPI1_SCLK_SW_PAD_REG SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI #define CSPI1_SCLK_BYTE_IN_SW_PAD 2 #define CSPI1_SPI_RDY_SW_PAD_REG SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI #define CSPI1_SPI_RDY_BYTE_IN_SW_PAD 1 #define CSPI2_MOSI_SW_PAD_REG SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI #define CSPI2_MOSI_BYTE_IN_SW_PAD 0 #define CSPI2_MISO_SW_PAD_REG SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1 #define CSPI2_MISO_BYTE_IN_SW_PAD 2 #define CSPI2_SS0_SW_PAD_REG SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1 #define CSPI2_SS0_BYTE_IN_SW_PAD 1 #define CSPI2_SS1_SW_PAD_REG SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1 #define CSPI2_SS1_BYTE_IN_SW_PAD 0 #define CSPI2_SS2_SW_PAD_REG SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY #define CSPI2_SS2_BYTE_IN_SW_PAD 2 #define CSPI2_SCLK_SW_PAD_REG SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY #define CSPI2_SCLK_BYTE_IN_SW_PAD 1 #define CSPI2_SPI_RDY_SW_PAD_REG SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY #define CSPI2_SPI_RDY_BYTE_IN_SW_PAD 0 #define RXD1_SW_PAD_REG SW_PAD_CTL_RXD1_TXD1_RTS1 #define RXD1_BYTE_IN_SW_PAD 2 #define TXD1_SW_PAD_REG SW_PAD_CTL_RXD1_TXD1_RTS1 #define TXD1_BYTE_IN_SW_PAD 1 #define RTS1_SW_PAD_REG SW_PAD_CTL_RXD1_TXD1_RTS1 #define RTS1_BYTE_IN_SW_PAD 0 #define CTS1_SW_PAD_REG SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1 #define CTS1_BYTE_IN_SW_PAD 2 #define DTR_DCE1_SW_PAD_REG SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1 #define DTR_DCE1_BYTE_IN_SW_PAD 1 #define DSR_DCE1_SW_PAD_REG SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1 #define DSR_DCE1_BYTE_IN_SW_PAD 0 #define RI_DCE1_SW_PAD_REG SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1 #define RI_DCE1_BYTE_IN_SW_PAD 2 #define DCD_DCE1_SW_PAD_REG SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1 #define DCD_DCE1_BYTE_IN_SW_PAD 1 #define DTR_DTE1_SW_PAD_REG SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1 #define DTR_DTE1_BYTE_IN_SW_PAD 0 #define DSR_DTE1_SW_PAD_REG SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1 #define DSR_DTE1_BYTE_IN_SW_PAD 2 #define RI_DTE1_SW_PAD_REG SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1 #define RI_DTE1_BYTE_IN_SW_PAD 1 #define DCD_DTE1_SW_PAD_REG SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1 #define DCD_DTE1_BYTE_IN_SW_PAD 0 #define DTR_DCE2_SW_PAD_REG SW_PAD_CTL_DTR_DCE2_RXD2_TXD2 #define DTR_DCE2_BYTE_IN_SW_PAD 2 #define RXD2_SW_PAD_REG SW_PAD_CTL_DTR_DCE2_RXD2_TXD2 #define RXD2_BYTE_IN_SW_PAD 1 #define TXD2_SW_PAD_REG SW_PAD_CTL_DTR_DCE2_RXD2_TXD2 #define TXD2_BYTE_IN_SW_PAD 0 #define RTS2_SW_PAD_REG SW_PAD_CTL_RTS2_CTS2_BATT_LINE #define RTS2_BYTE_IN_SW_PAD 2 #define CTS2_SW_PAD_REG SW_PAD_CTL_RTS2_CTS2_BATT_LINE #define CTS2_BYTE_IN_SW_PAD 1 #define BATT_LINE_SW_PAD_REG SW_PAD_CTL_RTS2_CTS2_BATT_LINE #define BATT_LINE_BYTE_IN_SW_PAD 0 #define KEY_ROW0_SW_PAD_REG SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2 #define KEY_ROW0_BYTE_IN_SW_PAD 2 #define KEY_ROW1_SW_PAD_REG SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2 #define KEY_ROW1_BYTE_IN_SW_PAD 1 #define KEY_ROW2_SW_PAD_REG SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2 #define KEY_ROW2_BYTE_IN_SW_PAD 0 #define KEY_ROW3_SW_PAD_REG SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5 #define KEY_ROW3_BYTE_IN_SW_PAD 2 #define KEY_ROW4_SW_PAD_REG SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5 #define KEY_ROW4_BYTE_IN_SW_PAD 1 #define KEY_ROW5_SW_PAD_REG SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5 #define KEY_ROW5_BYTE_IN_SW_PAD 0 #define KEY_ROW6_SW_PAD_REG SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0 #define KEY_ROW6_BYTE_IN_SW_PAD 2 #define KEY_ROW7_SW_PAD_REG SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0 #define KEY_ROW7_BYTE_IN_SW_PAD 1 #define KEY_COL0_SW_PAD_REG SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0 #define KEY_COL0_BYTE_IN_SW_PAD 0 #define KEY_COL1_SW_PAD_REG SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3 #define KEY_COL1_BYTE_IN_SW_PAD 2 #define KEY_COL2_SW_PAD_REG SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3 #define KEY_COL2_BYTE_IN_SW_PAD 1 #define KEY_COL3_SW_PAD_REG SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3 #define KEY_COL3_BYTE_IN_SW_PAD 0 #define KEY_COL4_SW_PAD_REG SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6 #define KEY_COL4_BYTE_IN_SW_PAD 2 #define KEY_COL5_SW_PAD_REG SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6 #define KEY_COL5_BYTE_IN_SW_PAD 1 #define KEY_COL6_SW_PAD_REG SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6 #define KEY_COL6_BYTE_IN_SW_PAD 0 #define KEY_COL7_SW_PAD_REG SW_PAD_CTL_KEY_COL7_RTCK_TCK #define KEY_COL7_BYTE_IN_SW_PAD 2 #define RTCK_SW_PAD_REG SW_PAD_CTL_KEY_COL7_RTCK_TCK #define RTCK_BYTE_IN_SW_PAD 1 #define TCK_SW_PAD_REG SW_PAD_CTL_KEY_COL7_RTCK_TCK #define TCK_BYTE_IN_SW_PAD 0 #define TMS_SW_PAD_REG SW_PAD_CTL_TMS_TDI_TDO #define TMS_BYTE_IN_SW_PAD 2 #define TDI_SW_PAD_REG SW_PAD_CTL_TMS_TDI_TDO #define TDI_BYTE_IN_SW_PAD 1 #define TDO_SW_PAD_REG SW_PAD_CTL_TMS_TDI_TDO #define TDO_BYTE_IN_SW_PAD 0 #define TRSTB_SW_PAD_REG SW_PAD_CTL_TRSTB_DE_B_SJC_MOD #define TRSTB_BYTE_IN_SW_PAD 2 #define DE_B_SW_PAD_REG SW_PAD_CTL_TRSTB_DE_B_SJC_MOD #define DE_B_BYTE_IN_SW_PAD 1 #define SJC_MOD_SW_PAD_REG SW_PAD_CTL_TRSTB_DE_B_SJC_MOD #define SJC_MOD_BYTE_IN_SW_PAD 0 #define USB_PWR_SW_PAD_REG SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP #define USB_PWR_BYTE_IN_SW_PAD 2 #define USB_OC_SW_PAD_REG SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP #define USB_OC_BYTE_IN_SW_PAD 1 #define USB_BYP_SW_PAD_REG SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP #define USB_BYP_BYTE_IN_SW_PAD 0 #define USBOTG_CLK_SW_PAD_REG SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP #define USBOTG_CLK_BYTE_IN_SW_PAD 2 #define USBOTG_DIR_SW_PAD_REG SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP #define USBOTG_DIR_BYTE_IN_SW_PAD 1 #define USBOTG_STP_SW_PAD_REG SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP #define USBOTG_STP_BYTE_IN_SW_PAD 0 #define USBOTG_NXT_SW_PAD_REG SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1 #define USBOTG_NXT_BYTE_IN_SW_PAD 2 #define USBOTG_DATA0_SW_PAD_REG SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1 #define USBOTG_DATA0_BYTE_IN_SW_PAD 1 #define USBOTG_DATA1_SW_PAD_REG SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1 #define USBOTG_DATA1_BYTE_IN_SW_PAD 0 #define USBOTG_DATA2_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 #define USBOTG_DATA2_BYTE_IN_SW_PAD 2 #define USBOTG_DATA3_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 #define USBOTG_DATA3_BYTE_IN_SW_PAD 1 #define USBOTG_DATA4_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 #define USBOTG_DATA4_BYTE_IN_SW_PAD 0 #define USBOTG_DATA5_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7 #define USBOTG_DATA5_BYTE_IN_SW_PAD 2 #define USBOTG_DATA6_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7 #define USBOTG_DATA6_BYTE_IN_SW_PAD 1 #define USBOTG_DATA7_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7 #define USBOTG_DATA7_BYTE_IN_SW_PAD 0 #define USBH2_CLK_SW_PAD_REG SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP #define USBH2_CLK_BYTE_IN_SW_PAD 2 #define USBH2_DIR_SW_PAD_REG SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP #define USBH2_DIR_BYTE_IN_SW_PAD 1 #define USBH2_STP_SW_PAD_REG SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP #define USBH2_STP_BYTE_IN_SW_PAD 0 #define USBH2_NXT_SW_PAD_REG SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1 #define USBH2_NXT_BYTE_IN_SW_PAD 2 #define USBH2_DATA0_SW_PAD_REG SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1 #define USBH2_DATA0_BYTE_IN_SW_PAD 1 #define USBH2_DATA1_SW_PAD_REG SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1 #define USBH2_DATA1_BYTE_IN_SW_PAD 0 #define LD0_SW_PAD_REG SW_PAD_CTL_LD0_LD1_LD2 #define LD0_BYTE_IN_SW_PAD 2 #define LD1_SW_PAD_REG SW_PAD_CTL_LD0_LD1_LD2 #define LD1_BYTE_IN_SW_PAD 1 #define LD2_SW_PAD_REG SW_PAD_CTL_LD0_LD1_LD2 #define LD2_BYTE_IN_SW_PAD 0 #define LD3_SW_PAD_REG SW_PAD_CTL_LD3_LD4_LD5 #define LD3_BYTE_IN_SW_PAD 2 #define LD4_SW_PAD_REG SW_PAD_CTL_LD3_LD4_LD5 #define LD4_BYTE_IN_SW_PAD 1 #define LD5_SW_PAD_REG SW_PAD_CTL_LD3_LD4_LD5 #define LD5_BYTE_IN_SW_PAD 0 #define LD6_SW_PAD_REG SW_PAD_CTL_LD6_LD7_LD8 #define LD6_BYTE_IN_SW_PAD 2 #define LD7_SW_PAD_REG SW_PAD_CTL_LD6_LD7_LD8 #define LD7_BYTE_IN_SW_PAD 1 #define LD8_SW_PAD_REG SW_PAD_CTL_LD6_LD7_LD8 #define LD8_BYTE_IN_SW_PAD 0 #define LD9_SW_PAD_REG SW_PAD_CTL_LD9_LD10_LD11 #define LD9_BYTE_IN_SW_PAD 2 #define LD10_SW_PAD_REG SW_PAD_CTL_LD9_LD10_LD11 #define LD10_BYTE_IN_SW_PAD 1 #define LD11_SW_PAD_REG SW_PAD_CTL_LD9_LD10_LD11 #define LD11_BYTE_IN_SW_PAD 0 #define LD12_SW_PAD_REG SW_PAD_CTL_LD12_LD13_LD14 #define LD12_BYTE_IN_SW_PAD 2 #define LD13_SW_PAD_REG SW_PAD_CTL_LD12_LD13_LD14 #define LD13_BYTE_IN_SW_PAD 1 #define LD14_SW_PAD_REG SW_PAD_CTL_LD12_LD13_LD14 #define LD14_BYTE_IN_SW_PAD 0 #define LD15_SW_PAD_REG SW_PAD_CTL_LD15_LD16_LD17 #define LD15_BYTE_IN_SW_PAD 2 #define LD16_SW_PAD_REG SW_PAD_CTL_LD15_LD16_LD17 #define LD16_BYTE_IN_SW_PAD 1 #define LD17_SW_PAD_REG SW_PAD_CTL_LD15_LD16_LD17 #define LD17_BYTE_IN_SW_PAD 0 #define VSYNC0_SW_PAD_REG SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT #define VSYNC0_BYTE_IN_SW_PAD 2 #define HSYNC_SW_PAD_REG SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT #define HSYNC_BYTE_IN_SW_PAD 1 #define FPSHIFT_SW_PAD_REG SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT #define FPSHIFT_BYTE_IN_SW_PAD 0 #define DRDY0_SW_PAD_REG SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO #define DRDY0_BYTE_IN_SW_PAD 2 #define SD_D_I_SW_PAD_REG SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO #define SD_D_I_BYTE_IN_SW_PAD 1 #define SD_D_IO_SW_PAD_REG SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO #define SD_D_IO_BYTE_IN_SW_PAD 0 #define SD_D_CLK_SW_PAD_REG SW_PAD_CTL_SD_D_CLK_LCS0_LCS1 #define SD_D_CLK_BYTE_IN_SW_PAD 2 #define LCS0_SW_PAD_REG SW_PAD_CTL_SD_D_CLK_LCS0_LCS1 #define LCS0_BYTE_IN_SW_PAD 1 #define LCS1_SW_PAD_REG SW_PAD_CTL_SD_D_CLK_LCS0_LCS1 #define LCS1_BYTE_IN_SW_PAD 0 #define SER_RS_SW_PAD_REG SW_PAD_CTL_SER_RS_PAR_RS_WRITE #define SER_RS_BYTE_IN_SW_PAD 2 #define PAR_RS_SW_PAD_REG SW_PAD_CTL_SER_RS_PAR_RS_WRITE #define PAR_RS_BYTE_IN_SW_PAD 1 #define WRITE_SW_PAD_REG SW_PAD_CTL_SER_RS_PAR_RS_WRITE #define WRITE_BYTE_IN_SW_PAD 0 #define READ_SW_PAD_REG SW_PAD_CTL_READ_VSYNC3_CONTRAST #define READ_BYTE_IN_SW_PAD 2 #define VSYNC3_SW_PAD_REG SW_PAD_CTL_READ_VSYNC3_CONTRAST #define VSYNC3_BYTE_IN_SW_PAD 1 #define CONTRAST_SW_PAD_REG SW_PAD_CTL_READ_VSYNC3_CONTRAST #define CONTRAST_BYTE_IN_SW_PAD 0 #define D3_REV_SW_PAD_REG SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL #define D3_REV_BYTE_IN_SW_PAD 2 #define D3_CLS_SW_PAD_REG SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL #define D3_CLS_BYTE_IN_SW_PAD 1 #define D3_SPL_SW_PAD_REG SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL #define D3_SPL_BYTE_IN_SW_PAD 0 #define SD1_CMD_SW_PAD_REG SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0 #define SD1_CMD_BYTE_IN_SW_PAD 2 #define SD1_CLK_SW_PAD_REG SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0 #define SD1_CLK_BYTE_IN_SW_PAD 1 #define SD1_DATA0_SW_PAD_REG SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0 #define SD1_DATA0_BYTE_IN_SW_PAD 0 #define SD1_DATA1_SW_PAD_REG SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3 #define SD1_DATA1_BYTE_IN_SW_PAD 2 #define SD1_DATA2_SW_PAD_REG SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3 #define SD1_DATA2_BYTE_IN_SW_PAD 1 #define SD1_DATA3_SW_PAD_REG SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3 #define SD1_DATA3_BYTE_IN_SW_PAD 0 #define ATA_CS0_SW_PAD_REG SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR #define ATA_CS0_BYTE_IN_SW_PAD 2 #define ATA_CS1_SW_PAD_REG SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR #define ATA_CS1_BYTE_IN_SW_PAD 1 #define ATA_DIOR_SW_PAD_REG SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR #define ATA_DIOR_BYTE_IN_SW_PAD 0 #define ATA_DIOW_SW_PAD_REG SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B #define ATA_DIOW_BYTE_IN_SW_PAD 2 #define ATA_DMACK_SW_PAD_REG SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B #define ATA_DMACK_BYTE_IN_SW_PAD 1 #define ATA_RESET_B_SW_PAD_REG SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B #define ATA_RESET_B_BYTE_IN_SW_PAD 0 #define CE_CONTROL_SW_PAD_REG SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI #define CE_CONTROL_BYTE_IN_SW_PAD 2 #define CLKSS_SW_PAD_REG SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI #define CLKSS_BYTE_IN_SW_PAD 1 #define CSPI3_MOSI_SW_PAD_REG SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI #define CSPI3_MOSI_BYTE_IN_SW_PAD 0 #define CSPI3_MISO_SW_PAD_REG SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY #define CSPI3_MISO_BYTE_IN_SW_PAD 2 #define CSPI3_SCLK_SW_PAD_REG SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY #define CSPI3_SCLK_BYTE_IN_SW_PAD 1 #define CSPI3_SPI_RDY_SW_PAD_REG SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY #define CSPI3_SPI_RDY_BYTE_IN_SW_PAD 0 #define TTM_PAD_SW_PAD_REG SW_PAD_CTL_TTM_PAD__X__X #define TTM_PAD_BYTE_IN_SW_PAD 2 // Defines for the iomux input mode : #define gpio_in 0x01 #define func_in 0x02 #define gpio_func_in 0x03 #define alt1_in 0x04 #define gpio_alt1_in 0x05 #define func_alt1_in 0x06 #define gpio_func_alt1_in 0x07 #define alt2_in 0x08 #define gpio_alt2_in 0x09 #define func_alt2_in 0x0a #define gpio_func_alt2_in 0x0b #define alt1_alt2_in 0x0c #define gpio_alt1_alt2_in 0x0d #define func_alt1_alt2_in 0x0e #define gpio_func_alt1_alt2_in 0x0f // Defines for the iomux output mode : #define gpio_out 0x00 #define func_out 0x10 #define alt1_out 0x20 #define alt2_out 0x30 #define alt3_out 0x40 #define alt4_out 0x50 #define alt5_out 0x60 #define alt6_out 0x70 #define BYTE3_MASK 0xff000000 #define BYTE2_MASK 0xff0000 #define BYTE1_MASK 0xff00 #define BYTE0_MASK 0xff #define PAD2_MASK 0x3ff00000 #define PAD1_MASK 0xffc00 #define PAD0_MASK 0x3ff WORD get_mixed_mode (WORD byte_in_reg,WORD output_mode,WORD input_mode); void config_pad_mode(WORD pad_name,WORD output_mode,WORD input_mode); void config_pad_settings(WORD pad_name,WORD wdata); #endif