#ifndef DEFINES_H
#define DEFINES_H

// **********************************************************************************************
// **********************************************************************************************
// UART BASE ADDRESS DEFINES
// **********************************************************************************************
// **********************************************************************************************
// BOOT ROM USES UART3 AS ITS PRIMARY UART.  THUS, IT WOULD BE BEST TO ATTEMPT TO BRING
// UP MY TEST CODE USING THE SAME UART (UART3 DEFINED AS THE PRIMARY).  WHEN ATTEMPTING TO USE
// UART 2 AS THE PRIMARY UART BE SURE TO RECONFIGURE THE IOMUX TO SUPPORT !!!!!

// **********************************************************************************************
// PRIMARY_UART is defined as the UART in which BlueGUI will communicate via RS232 (UB for SCM and ARGON+)
// ALT_PRIMARY_UART is defined as (UCE or UB)the UART in which BlueGUI does NOT communicate via RS232 (UCE for Zeus)
// **********************************************************************************************

	// Original plan for Argon / SCM
	//#define PRIMARY_UART_BASE   0x43F94000l 	// ArgonPlus/SCM (UART2), EVB-UCE
	//#define UART_A_BASE 0x43F90000l   		// ArgonPlus/SCM/Zeus (UART1), EVB-UA
	//#define ALT_PRIMARY_UART_BASE 0x5000C000l   	// ArgonPlus/SCM (UART3)), EVB-UB
	//#define UART_IrDA_BASE 0x50028000l   		// ArgonPlus (UART4)), EVB-IrDA

	//NEW Plan for ArgonPlus
	#define PRIMARY_UART_BASE   0x5000C000l   	// (UART3), EVB-UB **
	#define UART_A_BASE 0x43F90000l   		// (UART1), EVB-UA
	#define ALT_PRIMARY_UART_BASE 0x43F94000l   	// (UART2), EVB-UCE **
	#define UART_IrDA_BASE 0x50028000l   		// (UART4)), EVB-IrDA

	// Plan for SCM
	//#define UART_IrDA_BASE 0x43F90000l   		// (UART1), EVB-UA

	// Plan For Zeus
	//#define PRIMARY_UART_BASE   0x5000C000l   	// (UART3), EVB-UCE **
	//#define UART_A_BASE 0x43F90000l   		// (UART1), EVB-UA
	//#define ALT_PRIMARY_UART_BASE 0x43F94000l   	// (UART2), EVB-UB **
	//#define UART_IrDA_BASE 0x43F94000l   		// (UART2), EVB-UB



// **********************************************************************************************
// **********************************************************************************************
// UART INITIALIZATION/CONFIGURATION DEFINES
// **********************************************************************************************
// **********************************************************************************************
  
#define UART_UCR1_DEFAULT  0x0001	// ArgonPlus/SCM/Zeus
#define UART_UCR2_DEFAULT  0x5027	// ArgonPlus/SCM/Zeus
#define UART_UCR3_DEFAULT  0x0000	// ArgonPlus/SCM/Zeus
#define UART_UCR4_DEFAULT  0x4000	// ArgonPlus/SCM/Zeus
#define UART_UFCR_DEFAULT  0x0A81 	// ArgonPlus/SCM/Zeus

// **********************************************************************************************
// **********************************************************************************************
// MU BaseAddress DEFINES
// **********************************************************************************************
// **********************************************************************************************

//#define ARM_MU_BASE_ADDRESS 0x43F88000  // SCM
#define ARM_MU_BASE_ADDRESS 0x43F84000  // ARGON

// **********************************************************************************************
// **********************************************************************************************
// For transmission at 115200 BAUD with a clock reference of 16.8 MHz:
// 115200 = (N /(16*9))   ==>  N ((115200)*(16)* (9)) = 16588800 Hz
// Ratio Needed for (UBIR / UBMR) is (16.5888MHz / 16.8MHz ) = (Transmit Freq / Input Freq)
// This can be factored to (864 / 875) by dividing by 19,200.
// The Hex equivelant of this is (0x0360 / 0x036B)
// Thus for 115200 BAUD with a 16.8MHz Clk you set: UBIR=0x0360 and UBMR=0x036B 
// **********************************************************************************************
// **********************************************************************************************

// Defines for 115200 BAUD with Non-Integer Division at 26.MHz
//#define UBIR_BAUD115200  0x02C5	//SCM
//#define UBMR_BAUD115200  0x2710	//SCM

// Defines for 115200 BAUD with Non-Integer Division at 66.5MHz
//#define UBIR_BAUD115200  0x0115		//ARGON +
//#define UBMR_BAUD115200  0x2710		//ARGON +

// Defines for 115200 BAUD with Non-Integer Division at 33.25MHz
#define UBIR_BAUD115200  0x22A		//ARGON +
#define UBMR_BAUD115200  0x2710		//ARGON +

	// Defines for 115200 BAUD with Non-Integer Division at 13.3MHz
	//#define UBIR_BAUD115200  0x58A
	//#define UBMR_BAUD115200  0x2710

	// Defines for 115200 BAUD with Non-Integer Division (at 16.8MHz)
	//#define UBIR_BAUD115200  0x0449
	//#define UBMR_BAUD115200  0x2710

	// Defines for 115200 BAUD with Integer Division (at 16.8MHz)
	//#define UBIR_BAUD115200  0x0000
	//#define UBMR_BAUD115200  0x0008

	// Defines for 115200 BAUD with Non-Integer Division at 8.4MHz
	//#define UBIR_BAUD115200  0x0892
	//#define UBMR_BAUD115200  0x2710

// Defines for 19200 BAUD with Non-Integer Division (at 26.0MHz)
//#define UBIR_BAUD19200  0x0076	//SCM
//#define UBMR_BAUD19200  0x2710	//SCM

// Defines for 19200 BAUD with Non-Integer Division (at 66.5MHz)
//#define UBIR_BAUD19200  0x002F  //ARGON +
//#define UBMR_BAUD19200  0x2710  //ARGON +

// Defines for 19200 BAUD with Non-Integer Division (at 33.25MHz)
#define UBIR_BAUD19200  0x5C  //ARGON +
#define UBMR_BAUD19200  0x2710  //ARGON +

	// Defines for 19200 BAUD with Non-Integer Division (at 13.3MHz)
	//#define UBIR_BAUD19200  0xEC
	//#define UBMR_BAUD19200  0x2710

	// Defines for 19200 BAUD with Non-Integer Division (at 16.8MHz)
	//#define UBIR_BAUD19200  0x00B7
	//#define UBMR_BAUD19200  0x2710

	// Defines for 19200 BAUD with Integer Division (at 16.8MHz)
	//#define UBIR_BAUD19200  0x0000
	//#define UBMR_BAUD19200  0x0035

	// Defines for 19200 BAUD with Non-Integer Division at 8.4MHz
	//#define UBIR_BAUD19200  0x016E
	//#define UBMR_BAUD19200  0x2710


// **********************************************************************************************
// **********************************************************************************************
// EXTERNAL UART BASE ADDRESS DEFINES
// WARNING ... THIS BASE ADDRESS HAS NOT BEEN DEFINED BY ARCHITECTURE YET.  IT MUST BE CHANGED.
// **********************************************************************************************
// **********************************************************************************************
#define EXT_UART1_TXRX_BASE_ADDRESS (CS4_BASE + 0x00010010)  // Per PCB CPLD spec 7/7/04
#define EXT_UART2_TXRX_BASE_ADDRESS (CS4_BASE + 0x00010000)  // Per PCB CPLD spec 7/7/04


// **********************************************************************************************
// **********************************************************************************************
// Keypad Register ADDRESS DEFINES
// **********************************************************************************************
// **********************************************************************************************
#define Keypad_KPCR 0x43FA8000l	// ArgonPlus/SCM/Zeus
#define Keypad_KPSR 0x43FA8002l	// ArgonPlus/SCM/Zeus
#define Keypad_KDDR 0x43FA8004l	// ArgonPlus/SCM/Zeus
#define Keypad_KPDR 0x43FA8006l	// ArgonPlus/SCM/Zeus


// **********************************************************************************************
// **********************************************************************************************
// EXTERNAL MEMORY BASE ADDRESS DEFINES
// **********************************************************************************************
// **********************************************************************************************
#define CS0_BASE 0xA0000000l	// ArgonPlus/SCM/Zeus
#define CS1_BASE 0xA8000000l	// ArgonPlus/SCM/Zeus
#define CS2_BASE 0xB0000000l	// ArgonPlus/SCM/Zeus
#define CS3_BASE 0xB2000000l	// ArgonPlus/SCM/Zeus
#define CS4_BASE 0xB4000000l	// ArgonPlus/SCM/Zeus
#define CS5_BASE 0xB6000000l	// ArgonPlus/SCM/Zeus


// **********************************************************************************************
// **********************************************************************************************
// IPU DEFINES
// **********************************************************************************************
// **********************************************************************************************
#define IPU_BASE 0x53FC0000l
#define IPU_IMA_ADDR (IPU_BASE + 0x00000020l)
#define IPU_IMA_DATA (IPU_BASE + 0x00000024l)
#define IPU_CONF (IPU_BASE + 0x00000000l)
#define IC_CONF (IPU_BASE + 0x00000088l)
#define IDMAC_CHA_EN (IPU_BASE + 0x000000A8l)
#define SDC_COM_CONF (IPU_BASE + 0x000000B4l)
#define IPU_CHA_BUF0_RDY (IPU_BASE + 0x00000004l)
#define IPU_CHA_BUF1_RDY (IPU_BASE + 0x00000008l)
#define IDMAC_CHA_BUSY (IPU_BASE + 0x000000b0l)

#endif //DEFINES_H