#ifndef FUNCTIONS_H #define FUNCTIONS_H #include "tortola_memory_map_defines.h" //#include "verilog_trigger_macros.h" #include "macros.h" typedef volatile unsigned long WORD; typedef volatile unsigned short HALF; typedef volatile unsigned char BYTE; // Basic read/write definitions #define reg8_read(addr) *((BYTE *)(addr)) #define reg8_write(addr,val) *((BYTE *)(addr)) = (val) #define reg16_read(addr) *((HALF *)(addr)) #define reg16_write(addr,val) *((HALF *)(addr)) = (val) #define reg32_read(addr) *((WORD *)(addr)) #define reg32_write(addr,val) *((WORD *)(addr)) = (val) #define mem8_read(addr) *((BYTE *)(addr)) #define mem8_write(addr,val) *((BYTE *)(addr)) = (val) #define mem16_read(addr) *((HALF *)(addr)) #define mem16_write(addr,val) *((HALF *)(addr)) = (val) #define mem32_read(addr) *((WORD *)(addr)) #define mem32_write(addr,val) *((WORD *)(addr)) = (val) // ***************** // * regX_read_tst * // ***************** // // Read data from a given meemory-mapped register,and check Vs. expected data. // The arguments that these functions receive : // reg_addr - the address of the register from which the data is read // expect_val - the value we expect to be read // mask - masking specific bits so that they will not be compared // These functions use the function 'compare_results'.Refer to it for further explanation. // // Example : reg8_read_tst(OWIRE_TIME_DIV,0x12,0ff) // Here we read 8 bits from an 8-bit register OWIRE_TIME_DIV of OWIRE, // and expect all 8 bits to be equal to 0x12 // // reg16_read_tst(WDOG_WSR,0x1212,0x00ff) // Here we read 16 bits from a 16-bit register WDOG_WSR of WDOG, // and expect only the lower 8 bits to be equal to 0x12 #define reg8_read_tst(reg_addr,expect_val,mask) (compare_results(reg_addr,expect_val & mask,reg8_read(reg_addr) & mask)) #define reg16_read_tst(reg_addr,expect_val,mask) (compare_results(reg_addr,expect_val & mask,reg16_read(reg_addr) & mask)) #define reg32_read_tst(reg_addr,expect_val,mask) (compare_results(reg_addr,expect_val & mask,reg32_read(reg_addr) & mask)) // The memX_read_tst functions are completely identical to the regX_read_tst. // They have been put here for convience purposes only. #define mem8_read_tst(reg_addr,expect_val,mask) (compare_results(reg_addr,expect_val & mask,reg8_read(reg_addr) & mask)) #define mem16_read_tst(reg_addr,expect_val,mask) (compare_results(reg_addr,expect_val & mask,reg16_read(reg_addr) & mask)) #define mem32_read_tst(reg_addr,expect_val,mask) (compare_results(reg_addr,expect_val & mask,reg32_read(reg_addr) & mask)) /* -------------------------------------------------------------------------- */ /** @name Set/clear bit functionality */ /*@{ BEGIN ----------------------------------------------------------------- */ /** Macro to be used for setting a bit within a 32-bit register */ #define reg32setbit(addr,bitpos) \ reg32_write((addr),(reg32_read((addr)) | (1<<(bitpos)))) /** Macro to be used for setting a bit within a 16-bit register */ #define reg16setbit(addr,bitpos) \ reg16_write((addr),(reg16_read((addr)) | (1<<(bitpos)))) /** Macro to be used for setting a bit within a 8-bit register */ #define reg8setbit(addr,bitpos) \ reg8_write((addr),(reg8_read((addr)) | (1<<(bitpos)))) /** Macro to be used for clearing a bit within a 32-bit register */ #define reg32clrbit(addr,bitpos) \ reg32_write((addr),(reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos))))) /** Macro to be used for clearing a bit within a 16-bit register */ #define reg16clrbit(addr,bitpos) \ reg16_write((addr),(reg16_read((addr)) & (0xFFFF ^ (1<<(bitpos))))) /** Macro to be used for clearing a bit within a 8-bit register */ #define reg8clrbit(addr,bitpos) \ reg8_write((addr),(reg8_read((addr)) & (0xFF ^ (1<<(bitpos))))) /*@} END -------------------------------------------------------------------- */ // ************** // * Exceptions * // ************** // run-over a pre-defined default routine. // for instance : if you want to run over the GPT interrupt routine which is defined as // 'GPT_INT_ROUTINE' (look at /vobs/vb_argon/argon_projectdir/bin/arm_gcc/include/interrupt_defines.h) // with a specific handler you had written , say : 'my_int_handler'.It will be done the following way: // // CAPTURE_INTERRUPT(GPT_INT_ROUTINE,my_int_handler) // #define CAPTURE_INTERRUPT(int_routine_addr,int_routine_name) mem32_write(int_routine_addr,int_routine_name) #define CAPTURE_EXCEPTION(int_routine_addr,int_routine_name) mem32_write(int_routine_addr,int_routine_name) // run over a default interrupt routine for a specific interrupt. // this differs from 'CAPTURE_INTERRUPT' in that you don't have to know the name // of the interrupt routine you are running over , only the interrupt number (or name) // you wish to set the routine for. // for instance : if we want to set 'my_int_handler' as the interrupt routine for // interrupt No. 29 (GPT_INT) we should do the following : // // setup_irq_hdler(29,my_int_handler) // // or , if we know the defined name for interrupt No. 29 // // setup_irq_hdler(GPT_INT,my_int_handler) // // it is highly recommended to use the names and not absolute numbers because these might change. // #define setup_irq_hdler(int_name,func_ptr) reg32_write((WORD*) (AVIC_IVR-(4*int_name)),(WORD) func_ptr ) // the same as 'setup_irq_hdler' only for FAST interrupt routines. #define setup_fiq_hdler(int_name,func_ptr) reg32_write((WORD*) (AVIC_FVR-(4*int_name)),(WORD) func_ptr ) // Enable an interrupt handler. // This is done by writing the interrupt number (using a predefined macro) // as an argument for this function. // The function writes to an internal AVIC register (AVIC_INTENNUM) // the number of the interrupt which we want to enable a handler for. // // Example : enable_hdler(GPT_INT) // This will enable the interrupt handler for the GPT interrupt // which is connected as interrupt No. 29 in Argon. // If this interrupt will occur , the appropriate interrupt routine // will be activated. #define enable_hdler( int_name ) reg32_write(AVIC_INTENNUM, int_name ) // The 'disable_hdler' works the same as the 'enable_hdler' only that it // does the opposite - disables the interrupt handler. // // Example : disable_hdler(GPT_INT) // This will disable the interrupt handler for GPT. // If the GPT interrupt will occur , the interrupt routine will // not be triggered. #define disable_hdler( int_name ) reg32_write(AVIC_INTDISNUM, int_name ) // ******************* // * verilog_trigger * // ******************* // // A function that triggers a verilog event. // Argument : trigger_code - this argument determines which event will be triggered // in the verilog stimulus. // // The available event macros can be found in : // "/vobs/vb_argon/argon_projectdir/bin/arm_gcc/include/verilog_trigger_macros.h" // // Examples : 1) verilog_trigger(arm_vt_fail) // // This will trigger the "arm_vt_fail" event. // The "arm_vt_fail" event prints out a message of Test Failure // to the log file , and it increments the arm_fail_counter // and the general error_counter // // 2) verilog_trigger(arm_vt_event4) // // This will only trigger "arm_vt_event4" . // You can wait for this event in the verilog stimulus : // '@ (SOC_TESTBENCH_NAME.arm_vt_event4)' // and act on it's arrival. // //Irwen: change it in functions.c //#define verilog_trigger(trigger_code) mem16_write(ARM_PORTHOLE_ADD , trigger_code ) void verilog_trigger(char* trigger_code); // Macro defined to perform a "nop" instruction in the ARM assembler. #define nop() asm {nop}; // ********************************************* // Added for backward compatability #define wait_for_gpio_message(val) (wait_for_gpio_mcu_message(val)) #define ccm_mcu_deep_sleep_mode ccm_mcu_stop_mode // ********************************************* // ************* // * Functions * // ************* // // For further explanations go to : // "/vobs/vb_argon/argon_projectdir/bin/arm_gcc/include/functions.c" // There you can find the complete functions , and detailed information. // compare array void compare_array(WORD *exp_val,WORD *res_val, int num_of_res); // compare results int compare_results(WORD reg_addr,WORD exp_val,WORD res_val); // info trigger void info_trigger(WORD ADD,WORD EXP_DATA , WORD ACT_DATA); // verilog trigger checktest info message void info_checktest_trigger(WORD event,WORD exp_data , WORD act_data); // check test void CheckTest(WORD *exp_val,WORD *res_val, int num_of_res); // Initialize array void InitArray(WORD *exp_val,WORD *res_val, int num_of_res); // wait for gpio message - mcu side void wait_for_gpio_mcu_message (WORD val); // word data compare void word_data_compare (WORD worda , WORD wordb); // half-word data compare void hw_data_compare (HALF worda , HALF wordb); // byte data compare void byte_data_compare (BYTE worda , BYTE wordb); // reg8 read_write test void reg8_rw_test(WORD addr, BYTE wdata, BYTE exp_rdata); // reg16 read_write test void reg16_rw_test(WORD addr, HALF wdata, HALF exp_rdata); // reg32 read_write test void reg32_rw_test(WORD addr, WORD wdata, WORD exp_rdata); // reg8_write_mask void reg8_write_mask(WORD addr , BYTE wdata , BYTE mask); // reg16_write_mask void reg16_write_mask(WORD addr , HALF wdata , HALF mask); // reg32_write_mask void reg32_write_mask(WORD addr , WORD wdata , WORD mask); // configure_iomuxc_for_gpio_message_mcu void configure_iomuxc_for_gpio_message_mcu (); // ccm_mcu_stop_mode void ccm_mcu_stop_mode (); // ccm_mcu_doze_mode void ccm_mcu_doze_mode (); // ccm_mcu_wait_mode void ccm_mcu_wait_mode (); // configure pad mode in iomuxing // for further details about this function , look at : // /vobs/vb_argon/argon_projectdir/bin/arm_gcc/include/config_pad_mode.c void config_pad_mode(WORD pad_name,WORD output_mode,WORD input_mode); // IOMUX defines // SW_MUX_CTL and SW_PAD_CTL configuration for pads // ************************************************** // These defines are generated automatically from the Argon_pins Excel table // Please do not edit it manually. // For questions please contact Avi Levi : rm96456@motorola.com #define A0_MA0 1 #define A1_MA1 2 #define A2_MA2 3 #define A3_MA3 4 #define A4_MA4 5 #define A5_MA5 6 #define A6_MA6 7 #define A7_MA7 8 #define A8_MA8 9 #define A9_MA9 10 #define A10 11 #define MA10 12 #define A11_MA11 13 #define A12_MA12 14 #define A13_MA13 15 #define A14 16 #define A15 17 #define A16 18 #define A17 19 #define A18 20 #define A19 21 #define A20 22 #define A21 23 #define A22 24 #define A23 25 #define A24 26 #define A25 27 #define SD0 28 #define SD1 29 #define SD2 30 #define SD3 31 #define SD4 32 #define SD5 33 #define SD6 34 #define SD7 35 #define SD8 36 #define SD9 37 #define SD10 38 #define SD11 39 #define SD12 40 #define SD13 41 #define SD14 42 #define SD15 43 #define SD16 44 #define SD17 45 #define SD18 46 #define SD19 47 #define SD20 48 #define SD21 49 #define SD22 50 #define SD23 51 #define SD24 52 #define SD25 53 #define SD26 54 #define SD27 55 #define SD28 56 #define SD29 57 #define SD30 58 #define SD31 59 #define SDQS0 60 #define SDQS1 61 #define MGRNT 62 #define MRQST 63 #define DQM0 64 #define DQM1 65 #define DQM2 66 #define DQM3 67 #define OE_B 68 #define CS0_B 69 #define CS1_B 70 #define CS2_B 71 #define CS3_B 72 #define CS4_B 73 #define SDBA0 74 #define SDBA1 75 #define ECB_B 76 #define LBA_B 77 #define BCLK 78 #define RW_B 79 #define EB0_B 80 #define EB3_B 81 #define RAS 82 #define CAS 83 #define SDWE 84 #define SDCKE0 85 #define SDCKE1 86 #define SDCLK 87 #define SDCLK_B 88 #define CLE 89 #define WP 90 #define ALE 91 #define RE 92 #define WE 93 #define R_B 94 #define D0 95 #define D1 96 #define D2 97 #define D3 98 #define D4 99 #define D5 100 #define D6 101 #define D7 102 #define D8 103 #define D9 104 #define D10 105 #define D11 106 #define D12 107 #define D13 108 #define D14 109 #define D15 110 #define CKIL 111 #define WB_REF_CLK_IN 112 #define MB_REF_CLK_IN 113 #define CKIH_REF_CLK_IN 114 #define CKO1 115 #define CKO2 116 #define RESET_IN_B 117 #define RESET_POR_IN_B 118 #define TEST_MODE 119 #define BOOT_MODE0 120 #define BOOT_MODE1 121 #define REF_EN_B 122 #define PM_INT 123 #define POWER_FAIL 124 #define USER_OFF 125 #define WDOG_B 126 #define TRSTB 127 #define TDO 128 #define TDI 129 #define RTCK 130 #define TCK 131 #define TMS 132 #define SJC_MOD 133 #define DE_B 134 #define EVTI_B 135 #define SIM1_CLK0 136 #define SIM1_RST0 137 #define SIM1_DATA0_RX_TX 138 #define SIM1_SVEN0 139 #define SIM1_SIMPD0 140 #define USB1_VMOUT 141 #define USB1_TXENB 142 #define USB1_VPIN 143 #define USB1_VPOUT 144 #define USB1_VMIN 145 #define USB1_XRXD 146 #define USB_VMOUT 147 #define USB_TXENB 148 #define USB_VPIN 149 #define USB_VPOUT 150 #define USB_VMIN 151 #define USB_XRXD 152 #define BBP_RX_CLK 153 #define BBP_TX_CLK 154 #define BBP_RX_FRAME 155 #define BBP_TX_FRAME 156 #define BBP_RX_DATA 157 #define BBP_TX_DATA 158 #define GPIO28 159 #define GPIO29 160 #define GPIO30 161 #define GPIO31 162 #define GPIO32 163 #define GPIO33 164 #define GPIO34 165 #define GPIO35 166 #define SDMA_EVNT0 167 #define SDMA_EVNT1 168 #define WAMMO_TX_Q_CH 169 #define WAMMO_TX_I_CH 170 #define WAMMO_RX_Q_CH 171 #define WAMMO_RX_I_CH 172 #define WAMMO_TX_FRAME 173 #define WAMMO_RX_FRAME 174 #define WAMMO_DIV_RX_I_CH 175 #define WAMMO_DIV_RX_Q_CH 176 #define WAMMO_DIV_RX_FRAME 177 #define DSM1_STBY 178 #define DSM1_RX_ON 179 #define DSM2_STBY 180 #define DSM2_VCO_EN 181 #define L1T1OUT0 182 #define L1T1OUT1 183 #define L1T1OUT2 184 #define L1T1OUT3 185 #define L1T1OUT4 186 #define L1T1OUT5 187 #define L1T2OUT0 188 #define L1T2OUT1 189 #define L1T2OUT2 190 #define L1T2OUT3 191 #define MQSPI1_CK 192 #define MQSPI1_DI 193 #define MQSPI1_DO 194 #define MQSPI1_CS0 195 #define MQSPI1_CS1 196 #define MQSPI1_CS2 197 #define MQSPI2_CK 198 #define MQSPI2_DI 199 #define MQSPI2_DO 200 #define MQSPI2_CS0 201 #define MQSPI2_CS1 202 #define UART_TXD3 203 #define UART_RXD3 204 #define UART_RTS3_B 205 #define UART_CTS3_B 206 #define GPIO0 207 #define GPIO1 208 #define GPIO2 209 #define GPIO3 210 #define GPIO4 211 #define GPIO5 212 #define GPIO6 213 #define GPIO7 214 #define GPIO8 215 #define GPIO9 216 #define GPIO10 217 #define GPIO11 218 #define GPIO12 219 #define GPIO13 220 #define GPIO14 221 #define GPIO15 222 #define GPIO16 223 #define GPIO17 224 #define GPIO36 225 #define GPIO37 226 #define GPIO18 227 #define GPIO19 228 #define GPIO20 229 #define GPIO21 230 #define GPIO22 231 #define GPIO23 232 #define GPIO24 233 #define GPIO25 234 #define GPIO26 235 #define GPIO27 236 #define UART_TXD1 237 #define UART_RXD1 238 #define UART_RTS1_B 239 #define UART_CTS1_B 240 #define UART_CTS2_B 241 #define UART_DTR2_B 242 #define UART_RI2_B 243 #define UART_DCD2_B 244 #define UART_DSR2_B 245 #define UART_MUXCTL 246 #define IRDA_TX4 247 #define IRDA_RX4 248 #define DAM1_TXD 249 #define DAM1_RXD 250 #define DAM1_T_CLK 251 #define DAM1_T_FS 252 #define DAM2_TXD 253 #define DAM2_RXD 254 #define DAM2_T_CLK 255 #define DAM2_T_FS 256 #define DAM3_TXD 257 #define DAM3_RXD 258 #define DAM3_T_CLK 259 #define DAM3_T_FS 260 #define DAM3_R_CLK 261 #define DAM3_R_FS 262 #define BATT_LINE 263 #define PWM 264 #define CSPI2_CK 265 #define CSPI2_DO 266 #define CSPI2_DI 267 #define CSPI2_CS_0 268 #define CSPI2_CS_1 269 #define CSPI1_CK 270 #define CSPI1_DO 271 #define CSPI1_DI 272 #define CSPI1_CS_0 273 #define CSPI1_CS_1 274 #define IPU_FDAT_0 275 #define IPU_FDAT_1 276 #define IPU_FDAT_2 277 #define IPU_FDAT_3 278 #define IPU_FDAT_4 279 #define IPU_FDAT_5 280 #define IPU_FDAT_6 281 #define IPU_FDAT_7 282 #define IPU_FDAT_8 283 #define IPU_FDAT_9 284 #define IPU_FDAT_10 285 #define IPU_FDAT_11 286 #define IPU_FDAT_12 287 #define IPU_FDAT_13 288 #define IPU_FDAT_14 289 #define IPU_FDAT_15 290 #define IPU_FDAT_16 291 #define IPU_FDAT_17 292 #define IPU_VSYNC0 293 #define IPU_HSYNC 294 #define IPU_VSYNC3 295 #define IPU_LCS0 296 #define IPU_FPSHIFT 297 #define IPU_DRDY0 298 #define IPU_CONTRAST1 299 #define IPU_LCS1 300 #define IPU_SD_D_IO 301 #define IPU_SD_D_O 302 #define IPU_SD_D_CLK 303 #define IPU_SER_RS 304 #define IPU_PAR_RS 305 #define IPU_WRITE 306 #define IPU_READ 307 #define IPU_D3_CLS 308 #define IPU_D3_SPL 309 #define IPU_D3_REV 310 #define IPU_CSI_MCLK 311 #define IPU_CSI_HSYNC 312 #define IPU_CSI_VSYNC 313 #define IPU_CSI_DATA_0 314 #define IPU_CSI_DATA_1 315 #define IPU_CSI_DATA_2 316 #define IPU_CSI_DATA_3 317 #define IPU_CSI_DATA_4 318 #define IPU_CSI_DATA_5 319 #define IPU_CSI_DATA_6 320 #define IPU_CSI_DATA_7 321 #define IPU_CSI_DATA_8 322 #define IPU_CSI_DATA_9 323 #define IPU_CSI_PIXCLK 324 #define I2C_CLK 325 #define I2C_DAT 326 #define KEY_ROW0 327 #define KEY_ROW1 328 #define KEY_ROW2 329 #define KEY_ROW3 330 #define KEY_ROW4 331 #define KEY_ROW5 332 #define KEY_ROW6 333 #define KEY_ROW7 334 #define KEY_COL0 335 #define KEY_COL1 336 #define KEY_COL2 337 #define KEY_COL3 338 #define KEY_COL4 339 #define KEY_COL5 340 #define KEY_COL6 341 #define KEY_COL7 342 #define MMC1_CMD 343 #define MMC1_DATA_0 344 #define MMC1_DATA_1 345 #define MMC1_DATA_2 346 #define MMC1_DATA_3 347 #define MMC1_CLK 348 #define MMC1_SDDET 349 #define MMC2_CMD 350 #define MMC2_DATA_0 351 #define MMC2_DATA_1 352 #define MMC2_DATA_2 353 #define MMC2_DATA_3 354 #define MMC2_CLK 355 #define TRACE0 356 #define TRACE1 357 #define TRACE2 358 #define TRACE3 359 #define TRACE4 360 #define TRACE5 361 #define TRACE6 362 #define TRACE7 363 #define TRACE8 364 #define TRACE9 365 #define TRACE10 366 #define TRACE11 367 #define TRACE12 368 #define TRACE13 369 #define TRACE14 370 #define TRACE15 371 #define TRACE16 372 #define TRACE17 373 #define TRACE18 374 #define TRACE19 375 #define TRACE20 376 #define TRACE21 377 #define TRACE22 378 #define TRACE23 379 #define TRACE24 380 #define TRACE25 381 #define TRACE26 382 #define TRACE27 383 #define TRACE28 384 #define TRACE29 385 #define TRACE30 386 #define TRACE31 387 #define DBGACK 388 #define TRCLK 389 #define SRST 390 #define DBGRQ 391 #define EXTRIG 392 #define MDO0 393 #define MDO1 394 #define MDO2 395 #define MDO3 396 #define MDO4 397 #define MDO5 398 #define MDO6 399 #define MDO7 400 #define MDO8 401 #define MDO9 402 #define MDO10 403 #define MDO11 404 #define MDO12 405 #define MDO13 406 #define MDO14 407 #define MDO15 408 #define MDO16 409 #define MDO17 410 #define MDO18 411 #define MDO19 412 #define MDO20 413 #define MDO21 414 #define MDO22 415 #define MDO23 416 #define MDO24 417 #define MDO25 418 #define MDO26 419 #define MDO27 420 #define MDO28 421 #define MDO29 422 #define MDO30 423 #define MDO31 424 #define MSE1 425 #define EVTO 426 #define MRDY 427 #define MCKO 428 #define MSE0 429 // SW_MUX_CTL defines : //###################### #define A0_MA0_SW_MUX_REG SW_MUX_CTL_A0_MA0_A1_MA1_A2_MA2_A3_MA3 #define A0_MA0_BYTE_IN_SW_MUX 3 #define A1_MA1_SW_MUX_REG SW_MUX_CTL_A0_MA0_A1_MA1_A2_MA2_A3_MA3 #define A1_MA1_BYTE_IN_SW_MUX 2 #define A2_MA2_SW_MUX_REG SW_MUX_CTL_A0_MA0_A1_MA1_A2_MA2_A3_MA3 #define A2_MA2_BYTE_IN_SW_MUX 1 #define A3_MA3_SW_MUX_REG SW_MUX_CTL_A0_MA0_A1_MA1_A2_MA2_A3_MA3 #define A3_MA3_BYTE_IN_SW_MUX 0 #define A4_MA4_SW_MUX_REG SW_MUX_CTL_A4_MA4_A5_MA5_A6_MA6_A7_MA7 #define A4_MA4_BYTE_IN_SW_MUX 3 #define A5_MA5_SW_MUX_REG SW_MUX_CTL_A4_MA4_A5_MA5_A6_MA6_A7_MA7 #define A5_MA5_BYTE_IN_SW_MUX 2 #define A6_MA6_SW_MUX_REG SW_MUX_CTL_A4_MA4_A5_MA5_A6_MA6_A7_MA7 #define A6_MA6_BYTE_IN_SW_MUX 1 #define A7_MA7_SW_MUX_REG SW_MUX_CTL_A4_MA4_A5_MA5_A6_MA6_A7_MA7 #define A7_MA7_BYTE_IN_SW_MUX 0 #define A8_MA8_SW_MUX_REG SW_MUX_CTL_A8_MA8_A9_MA9_A10_MA10 #define A8_MA8_BYTE_IN_SW_MUX 3 #define A9_MA9_SW_MUX_REG SW_MUX_CTL_A8_MA8_A9_MA9_A10_MA10 #define A9_MA9_BYTE_IN_SW_MUX 2 #define A10_SW_MUX_REG SW_MUX_CTL_A8_MA8_A9_MA9_A10_MA10 #define A10_BYTE_IN_SW_MUX 1 #define MA10_SW_MUX_REG SW_MUX_CTL_A8_MA8_A9_MA9_A10_MA10 #define MA10_BYTE_IN_SW_MUX 0 #define A11_MA11_SW_MUX_REG SW_MUX_CTL_A11_MA11_A12_MA12_A13_MA13_A14 #define A11_MA11_BYTE_IN_SW_MUX 3 #define A12_MA12_SW_MUX_REG SW_MUX_CTL_A11_MA11_A12_MA12_A13_MA13_A14 #define A12_MA12_BYTE_IN_SW_MUX 2 #define A13_MA13_SW_MUX_REG SW_MUX_CTL_A11_MA11_A12_MA12_A13_MA13_A14 #define A13_MA13_BYTE_IN_SW_MUX 1 #define A14_SW_MUX_REG SW_MUX_CTL_A11_MA11_A12_MA12_A13_MA13_A14 #define A14_BYTE_IN_SW_MUX 0 #define A15_SW_MUX_REG SW_MUX_CTL_A15_A16_A17_A18 #define A15_BYTE_IN_SW_MUX 3 #define A16_SW_MUX_REG SW_MUX_CTL_A15_A16_A17_A18 #define A16_BYTE_IN_SW_MUX 2 #define A17_SW_MUX_REG SW_MUX_CTL_A15_A16_A17_A18 #define A17_BYTE_IN_SW_MUX 1 #define A18_SW_MUX_REG SW_MUX_CTL_A15_A16_A17_A18 #define A18_BYTE_IN_SW_MUX 0 #define A19_SW_MUX_REG SW_MUX_CTL_A19_A20_A21_A22 #define A19_BYTE_IN_SW_MUX 3 #define A20_SW_MUX_REG SW_MUX_CTL_A19_A20_A21_A22 #define A20_BYTE_IN_SW_MUX 2 #define A21_SW_MUX_REG SW_MUX_CTL_A19_A20_A21_A22 #define A21_BYTE_IN_SW_MUX 1 #define A22_SW_MUX_REG SW_MUX_CTL_A19_A20_A21_A22 #define A22_BYTE_IN_SW_MUX 0 #define A23_SW_MUX_REG SW_MUX_CTL_A23_A24_A25_SD0 #define A23_BYTE_IN_SW_MUX 3 #define A24_SW_MUX_REG SW_MUX_CTL_A23_A24_A25_SD0 #define A24_BYTE_IN_SW_MUX 2 #define A25_SW_MUX_REG SW_MUX_CTL_A23_A24_A25_SD0 #define A25_BYTE_IN_SW_MUX 1 #define SD0_SW_MUX_REG SW_MUX_CTL_A23_A24_A25_SD0 #define SD0_BYTE_IN_SW_MUX 0 #define SD1_SW_MUX_REG SW_MUX_CTL_SD1_SD2_SD3_SD4 #define SD1_BYTE_IN_SW_MUX 3 #define SD2_SW_MUX_REG SW_MUX_CTL_SD1_SD2_SD3_SD4 #define SD2_BYTE_IN_SW_MUX 2 #define SD3_SW_MUX_REG SW_MUX_CTL_SD1_SD2_SD3_SD4 #define SD3_BYTE_IN_SW_MUX 1 #define SD4_SW_MUX_REG SW_MUX_CTL_SD1_SD2_SD3_SD4 #define SD4_BYTE_IN_SW_MUX 0 #define SD5_SW_MUX_REG SW_MUX_CTL_SD5_SD6_SD7_SD8 #define SD5_BYTE_IN_SW_MUX 3 #define SD6_SW_MUX_REG SW_MUX_CTL_SD5_SD6_SD7_SD8 #define SD6_BYTE_IN_SW_MUX 2 #define SD7_SW_MUX_REG SW_MUX_CTL_SD5_SD6_SD7_SD8 #define SD7_BYTE_IN_SW_MUX 1 #define SD8_SW_MUX_REG SW_MUX_CTL_SD5_SD6_SD7_SD8 #define SD8_BYTE_IN_SW_MUX 0 #define SD9_SW_MUX_REG SW_MUX_CTL_SD9_SD10_SD11_SD12 #define SD9_BYTE_IN_SW_MUX 3 #define SD10_SW_MUX_REG SW_MUX_CTL_SD9_SD10_SD11_SD12 #define SD10_BYTE_IN_SW_MUX 2 #define SD11_SW_MUX_REG SW_MUX_CTL_SD9_SD10_SD11_SD12 #define SD11_BYTE_IN_SW_MUX 1 #define SD12_SW_MUX_REG SW_MUX_CTL_SD9_SD10_SD11_SD12 #define SD12_BYTE_IN_SW_MUX 0 #define SD13_SW_MUX_REG SW_MUX_CTL_SD13_SD14_SD15_SD16 #define SD13_BYTE_IN_SW_MUX 3 #define SD14_SW_MUX_REG SW_MUX_CTL_SD13_SD14_SD15_SD16 #define SD14_BYTE_IN_SW_MUX 2 #define SD15_SW_MUX_REG SW_MUX_CTL_SD13_SD14_SD15_SD16 #define SD15_BYTE_IN_SW_MUX 1 #define SD16_SW_MUX_REG SW_MUX_CTL_SD13_SD14_SD15_SD16 #define SD16_BYTE_IN_SW_MUX 0 #define SD17_SW_MUX_REG SW_MUX_CTL_SD17_SD18_SD19_SD20 #define SD17_BYTE_IN_SW_MUX 3 #define SD18_SW_MUX_REG SW_MUX_CTL_SD17_SD18_SD19_SD20 #define SD18_BYTE_IN_SW_MUX 2 #define SD19_SW_MUX_REG SW_MUX_CTL_SD17_SD18_SD19_SD20 #define SD19_BYTE_IN_SW_MUX 1 #define SD20_SW_MUX_REG SW_MUX_CTL_SD17_SD18_SD19_SD20 #define SD20_BYTE_IN_SW_MUX 0 #define SD21_SW_MUX_REG SW_MUX_CTL_SD21_SD22_SD23_SD24 #define SD21_BYTE_IN_SW_MUX 3 #define SD22_SW_MUX_REG SW_MUX_CTL_SD21_SD22_SD23_SD24 #define SD22_BYTE_IN_SW_MUX 2 #define SD23_SW_MUX_REG SW_MUX_CTL_SD21_SD22_SD23_SD24 #define SD23_BYTE_IN_SW_MUX 1 #define SD24_SW_MUX_REG SW_MUX_CTL_SD21_SD22_SD23_SD24 #define SD24_BYTE_IN_SW_MUX 0 #define SD25_SW_MUX_REG SW_MUX_CTL_SD25_SD26_SD27_SD28 #define SD25_BYTE_IN_SW_MUX 3 #define SD26_SW_MUX_REG SW_MUX_CTL_SD25_SD26_SD27_SD28 #define SD26_BYTE_IN_SW_MUX 2 #define SD27_SW_MUX_REG SW_MUX_CTL_SD25_SD26_SD27_SD28 #define SD27_BYTE_IN_SW_MUX 1 #define SD28_SW_MUX_REG SW_MUX_CTL_SD25_SD26_SD27_SD28 #define SD28_BYTE_IN_SW_MUX 0 #define SD29_SW_MUX_REG SW_MUX_CTL_SD29_SD30_SD31_SDQS0 #define SD29_BYTE_IN_SW_MUX 3 #define SD30_SW_MUX_REG SW_MUX_CTL_SD29_SD30_SD31_SDQS0 #define SD30_BYTE_IN_SW_MUX 2 #define SD31_SW_MUX_REG SW_MUX_CTL_SD29_SD30_SD31_SDQS0 #define SD31_BYTE_IN_SW_MUX 1 #define SDQS0_SW_MUX_REG SW_MUX_CTL_SD29_SD30_SD31_SDQS0 #define SDQS0_BYTE_IN_SW_MUX 0 #define SDQS1_SW_MUX_REG SW_MUX_CTL_SDQS1_MGRNT_MRQST_DQM0 #define SDQS1_BYTE_IN_SW_MUX 3 #define MGRNT_SW_MUX_REG SW_MUX_CTL_SDQS1_MGRNT_MRQST_DQM0 #define MGRNT_BYTE_IN_SW_MUX 2 #define MRQST_SW_MUX_REG SW_MUX_CTL_SDQS1_MGRNT_MRQST_DQM0 #define MRQST_BYTE_IN_SW_MUX 1 #define DQM0_SW_MUX_REG SW_MUX_CTL_SDQS1_MGRNT_MRQST_DQM0 #define DQM0_BYTE_IN_SW_MUX 0 #define DQM1_SW_MUX_REG SW_MUX_CTL_DQM1_DQM2_DQM3_OE_B #define DQM1_BYTE_IN_SW_MUX 3 #define DQM2_SW_MUX_REG SW_MUX_CTL_DQM1_DQM2_DQM3_OE_B #define DQM2_BYTE_IN_SW_MUX 2 #define DQM3_SW_MUX_REG SW_MUX_CTL_DQM1_DQM2_DQM3_OE_B #define DQM3_BYTE_IN_SW_MUX 1 #define OE_B_SW_MUX_REG SW_MUX_CTL_DQM1_DQM2_DQM3_OE_B #define OE_B_BYTE_IN_SW_MUX 0 #define CS0_B_SW_MUX_REG SW_MUX_CTL_CS0_B_CS1_B_CS2_B_CS3_B #define CS0_B_BYTE_IN_SW_MUX 3 #define CS1_B_SW_MUX_REG SW_MUX_CTL_CS0_B_CS1_B_CS2_B_CS3_B #define CS1_B_BYTE_IN_SW_MUX 2 #define CS2_B_SW_MUX_REG SW_MUX_CTL_CS0_B_CS1_B_CS2_B_CS3_B #define CS2_B_BYTE_IN_SW_MUX 1 #define CS3_B_SW_MUX_REG SW_MUX_CTL_CS0_B_CS1_B_CS2_B_CS3_B #define CS3_B_BYTE_IN_SW_MUX 0 #define CS4_B_SW_MUX_REG SW_MUX_CTL_CS4_B_SDBA0_SDBA1_ECB_B #define CS4_B_BYTE_IN_SW_MUX 3 #define SDBA0_SW_MUX_REG SW_MUX_CTL_CS4_B_SDBA0_SDBA1_ECB_B #define SDBA0_BYTE_IN_SW_MUX 2 #define SDBA1_SW_MUX_REG SW_MUX_CTL_CS4_B_SDBA0_SDBA1_ECB_B #define SDBA1_BYTE_IN_SW_MUX 1 #define ECB_B_SW_MUX_REG SW_MUX_CTL_CS4_B_SDBA0_SDBA1_ECB_B #define ECB_B_BYTE_IN_SW_MUX 0 #define LBA_B_SW_MUX_REG SW_MUX_CTL_LBA_B_BCLK_RW_B_EB0_B #define LBA_B_BYTE_IN_SW_MUX 3 #define BCLK_SW_MUX_REG SW_MUX_CTL_LBA_B_BCLK_RW_B_EB0_B #define BCLK_BYTE_IN_SW_MUX 2 #define RW_B_SW_MUX_REG SW_MUX_CTL_LBA_B_BCLK_RW_B_EB0_B #define RW_B_BYTE_IN_SW_MUX 1 #define EB0_B_SW_MUX_REG SW_MUX_CTL_LBA_B_BCLK_RW_B_EB0_B #define EB0_B_BYTE_IN_SW_MUX 0 #define EB3_B_SW_MUX_REG SW_MUX_CTL_EB3_B_RAS_CAS_SDWE #define EB3_B_BYTE_IN_SW_MUX 3 #define RAS_SW_MUX_REG SW_MUX_CTL_EB3_B_RAS_CAS_SDWE #define RAS_BYTE_IN_SW_MUX 2 #define CAS_SW_MUX_REG SW_MUX_CTL_EB3_B_RAS_CAS_SDWE #define CAS_BYTE_IN_SW_MUX 1 #define SDWE_SW_MUX_REG SW_MUX_CTL_EB3_B_RAS_CAS_SDWE #define SDWE_BYTE_IN_SW_MUX 0 #define SDCKE0_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B #define SDCKE0_BYTE_IN_SW_MUX 3 #define SDCKE1_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B #define SDCKE1_BYTE_IN_SW_MUX 2 #define SDCLK_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B #define SDCLK_BYTE_IN_SW_MUX 1 #define SDCLK_B_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B #define SDCLK_B_BYTE_IN_SW_MUX 0 #define CLE_SW_MUX_REG SW_MUX_CTL_CLE_WP_ALE_RE #define CLE_BYTE_IN_SW_MUX 3 #define WP_SW_MUX_REG SW_MUX_CTL_CLE_WP_ALE_RE #define WP_BYTE_IN_SW_MUX 2 #define ALE_SW_MUX_REG SW_MUX_CTL_CLE_WP_ALE_RE #define ALE_BYTE_IN_SW_MUX 1 #define RE_SW_MUX_REG SW_MUX_CTL_CLE_WP_ALE_RE #define RE_BYTE_IN_SW_MUX 0 #define WE_SW_MUX_REG SW_MUX_CTL_WE_R_B_D0_D1 #define WE_BYTE_IN_SW_MUX 3 #define R_B_SW_MUX_REG SW_MUX_CTL_WE_R_B_D0_D1 #define R_B_BYTE_IN_SW_MUX 2 #define D0_SW_MUX_REG SW_MUX_CTL_WE_R_B_D0_D1 #define D0_BYTE_IN_SW_MUX 1 #define D1_SW_MUX_REG SW_MUX_CTL_WE_R_B_D0_D1 #define D1_BYTE_IN_SW_MUX 0 #define D2_SW_MUX_REG SW_MUX_CTL_D2_D3_D4_D5 #define D2_BYTE_IN_SW_MUX 3 #define D3_SW_MUX_REG SW_MUX_CTL_D2_D3_D4_D5 #define D3_BYTE_IN_SW_MUX 2 #define D4_SW_MUX_REG SW_MUX_CTL_D2_D3_D4_D5 #define D4_BYTE_IN_SW_MUX 1 #define D5_SW_MUX_REG SW_MUX_CTL_D2_D3_D4_D5 #define D5_BYTE_IN_SW_MUX 0 #define D6_SW_MUX_REG SW_MUX_CTL_D6_D7_D8_D9 #define D6_BYTE_IN_SW_MUX 3 #define D7_SW_MUX_REG SW_MUX_CTL_D6_D7_D8_D9 #define D7_BYTE_IN_SW_MUX 2 #define D8_SW_MUX_REG SW_MUX_CTL_D6_D7_D8_D9 #define D8_BYTE_IN_SW_MUX 1 #define D9_SW_MUX_REG SW_MUX_CTL_D6_D7_D8_D9 #define D9_BYTE_IN_SW_MUX 0 #define D10_SW_MUX_REG SW_MUX_CTL_D10_D11_D12_D13 #define D10_BYTE_IN_SW_MUX 3 #define D11_SW_MUX_REG SW_MUX_CTL_D10_D11_D12_D13 #define D11_BYTE_IN_SW_MUX 2 #define D12_SW_MUX_REG SW_MUX_CTL_D10_D11_D12_D13 #define D12_BYTE_IN_SW_MUX 1 #define D13_SW_MUX_REG SW_MUX_CTL_D10_D11_D12_D13 #define D13_BYTE_IN_SW_MUX 0 #define D14_SW_MUX_REG SW_MUX_CTL_D14_D15_CKIL_WB_REF_CLK_IN #define D14_BYTE_IN_SW_MUX 3 #define D15_SW_MUX_REG SW_MUX_CTL_D14_D15_CKIL_WB_REF_CLK_IN #define D15_BYTE_IN_SW_MUX 2 #define CKIL_SW_MUX_REG SW_MUX_CTL_D14_D15_CKIL_WB_REF_CLK_IN #define CKIL_BYTE_IN_SW_MUX 1 #define WB_REF_CLK_IN_SW_MUX_REG SW_MUX_CTL_D14_D15_CKIL_WB_REF_CLK_IN #define WB_REF_CLK_IN_BYTE_IN_SW_MUX 0 #define MB_REF_CLK_IN_SW_MUX_REG SW_MUX_CTL_MB_REF_CLK_IN_CKIH_REF_CLK_IN_CKO1_CKO2 #define MB_REF_CLK_IN_BYTE_IN_SW_MUX 3 #define CKIH_REF_CLK_IN_SW_MUX_REG SW_MUX_CTL_MB_REF_CLK_IN_CKIH_REF_CLK_IN_CKO1_CKO2 #define CKIH_REF_CLK_IN_BYTE_IN_SW_MUX 2 #define CKO1_SW_MUX_REG SW_MUX_CTL_MB_REF_CLK_IN_CKIH_REF_CLK_IN_CKO1_CKO2 #define CKO1_BYTE_IN_SW_MUX 1 #define CKO2_SW_MUX_REG SW_MUX_CTL_MB_REF_CLK_IN_CKIH_REF_CLK_IN_CKO1_CKO2 #define CKO2_BYTE_IN_SW_MUX 0 #define RESET_IN_B_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_RESET_POR_IN_B_TEST_MODE_BOOT_MODE0 #define RESET_IN_B_BYTE_IN_SW_MUX 3 #define RESET_POR_IN_B_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_RESET_POR_IN_B_TEST_MODE_BOOT_MODE0 #define RESET_POR_IN_B_BYTE_IN_SW_MUX 2 #define TEST_MODE_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_RESET_POR_IN_B_TEST_MODE_BOOT_MODE0 #define TEST_MODE_BYTE_IN_SW_MUX 1 #define BOOT_MODE0_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_RESET_POR_IN_B_TEST_MODE_BOOT_MODE0 #define BOOT_MODE0_BYTE_IN_SW_MUX 0 #define BOOT_MODE1_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_REF_EN_B_PM_INT_POWER_FAIL #define BOOT_MODE1_BYTE_IN_SW_MUX 3 #define REF_EN_B_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_REF_EN_B_PM_INT_POWER_FAIL #define REF_EN_B_BYTE_IN_SW_MUX 2 #define PM_INT_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_REF_EN_B_PM_INT_POWER_FAIL #define PM_INT_BYTE_IN_SW_MUX 1 #define POWER_FAIL_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_REF_EN_B_PM_INT_POWER_FAIL #define POWER_FAIL_BYTE_IN_SW_MUX 0 #define USER_OFF_SW_MUX_REG SW_MUX_CTL_USER_OFF_WDOG_B_TRSTB_TDO #define USER_OFF_BYTE_IN_SW_MUX 3 #define WDOG_B_SW_MUX_REG SW_MUX_CTL_USER_OFF_WDOG_B_TRSTB_TDO #define WDOG_B_BYTE_IN_SW_MUX 2 #define TRSTB_SW_MUX_REG SW_MUX_CTL_USER_OFF_WDOG_B_TRSTB_TDO #define TRSTB_BYTE_IN_SW_MUX 1 #define TDO_SW_MUX_REG SW_MUX_CTL_USER_OFF_WDOG_B_TRSTB_TDO #define TDO_BYTE_IN_SW_MUX 0 #define TDI_SW_MUX_REG SW_MUX_CTL_TDI_RTCK_TCK_TMS #define TDI_BYTE_IN_SW_MUX 3 #define RTCK_SW_MUX_REG SW_MUX_CTL_TDI_RTCK_TCK_TMS #define RTCK_BYTE_IN_SW_MUX 2 #define TCK_SW_MUX_REG SW_MUX_CTL_TDI_RTCK_TCK_TMS #define TCK_BYTE_IN_SW_MUX 1 #define TMS_SW_MUX_REG SW_MUX_CTL_TDI_RTCK_TCK_TMS #define TMS_BYTE_IN_SW_MUX 0 #define SJC_MOD_SW_MUX_REG SW_MUX_CTL_SJC_MOD_DE_B_EVTI_B_SIM1_CLK0 #define SJC_MOD_BYTE_IN_SW_MUX 3 #define DE_B_SW_MUX_REG SW_MUX_CTL_SJC_MOD_DE_B_EVTI_B_SIM1_CLK0 #define DE_B_BYTE_IN_SW_MUX 2 #define EVTI_B_SW_MUX_REG SW_MUX_CTL_SJC_MOD_DE_B_EVTI_B_SIM1_CLK0 #define EVTI_B_BYTE_IN_SW_MUX 1 #define SIM1_CLK0_SW_MUX_REG SW_MUX_CTL_SJC_MOD_DE_B_EVTI_B_SIM1_CLK0 #define SIM1_CLK0_BYTE_IN_SW_MUX 0 #define SIM1_RST0_SW_MUX_REG SW_MUX_CTL_SIM1_RST0_SIM1_DATA0_RX_TX_SIM1_SVEN0_SIM1_SIMPD0 #define SIM1_RST0_BYTE_IN_SW_MUX 3 #define SIM1_DATA0_RX_TX_SW_MUX_REG SW_MUX_CTL_SIM1_RST0_SIM1_DATA0_RX_TX_SIM1_SVEN0_SIM1_SIMPD0 #define SIM1_DATA0_RX_TX_BYTE_IN_SW_MUX 2 #define SIM1_SVEN0_SW_MUX_REG SW_MUX_CTL_SIM1_RST0_SIM1_DATA0_RX_TX_SIM1_SVEN0_SIM1_SIMPD0 #define SIM1_SVEN0_BYTE_IN_SW_MUX 1 #define SIM1_SIMPD0_SW_MUX_REG SW_MUX_CTL_SIM1_RST0_SIM1_DATA0_RX_TX_SIM1_SVEN0_SIM1_SIMPD0 #define SIM1_SIMPD0_BYTE_IN_SW_MUX 0 #define USB1_VMOUT_SW_MUX_REG SW_MUX_CTL_USB1_VMOUT_USB1_TXENB_USB1_VPIN_USB1_VPOUT #define USB1_VMOUT_BYTE_IN_SW_MUX 3 #define USB1_TXENB_SW_MUX_REG SW_MUX_CTL_USB1_VMOUT_USB1_TXENB_USB1_VPIN_USB1_VPOUT #define USB1_TXENB_BYTE_IN_SW_MUX 2 #define USB1_VPIN_SW_MUX_REG SW_MUX_CTL_USB1_VMOUT_USB1_TXENB_USB1_VPIN_USB1_VPOUT #define USB1_VPIN_BYTE_IN_SW_MUX 1 #define USB1_VPOUT_SW_MUX_REG SW_MUX_CTL_USB1_VMOUT_USB1_TXENB_USB1_VPIN_USB1_VPOUT #define USB1_VPOUT_BYTE_IN_SW_MUX 0 #define USB1_VMIN_SW_MUX_REG SW_MUX_CTL_USB1_VMIN_USB1_XRXD_USB_VMOUT_USB_TXENB #define USB1_VMIN_BYTE_IN_SW_MUX 3 #define USB1_XRXD_SW_MUX_REG SW_MUX_CTL_USB1_VMIN_USB1_XRXD_USB_VMOUT_USB_TXENB #define USB1_XRXD_BYTE_IN_SW_MUX 2 #define USB_VMOUT_SW_MUX_REG SW_MUX_CTL_USB1_VMIN_USB1_XRXD_USB_VMOUT_USB_TXENB #define USB_VMOUT_BYTE_IN_SW_MUX 1 #define USB_TXENB_SW_MUX_REG SW_MUX_CTL_USB1_VMIN_USB1_XRXD_USB_VMOUT_USB_TXENB #define USB_TXENB_BYTE_IN_SW_MUX 0 #define USB_VPIN_SW_MUX_REG SW_MUX_CTL_USB_VPIN_USB_VPOUT_USB_VMIN_USB_XRXD #define USB_VPIN_BYTE_IN_SW_MUX 3 #define USB_VPOUT_SW_MUX_REG SW_MUX_CTL_USB_VPIN_USB_VPOUT_USB_VMIN_USB_XRXD #define USB_VPOUT_BYTE_IN_SW_MUX 2 #define USB_VMIN_SW_MUX_REG SW_MUX_CTL_USB_VPIN_USB_VPOUT_USB_VMIN_USB_XRXD #define USB_VMIN_BYTE_IN_SW_MUX 1 #define USB_XRXD_SW_MUX_REG SW_MUX_CTL_USB_VPIN_USB_VPOUT_USB_VMIN_USB_XRXD #define USB_XRXD_BYTE_IN_SW_MUX 0 #define BBP_RX_CLK_SW_MUX_REG SW_MUX_CTL_BBP_RX_CLK_BBP_TX_CLK_BBP_RX_FRAME_BBP_TX_FRAME #define BBP_RX_CLK_BYTE_IN_SW_MUX 3 #define BBP_TX_CLK_SW_MUX_REG SW_MUX_CTL_BBP_RX_CLK_BBP_TX_CLK_BBP_RX_FRAME_BBP_TX_FRAME #define BBP_TX_CLK_BYTE_IN_SW_MUX 2 #define BBP_RX_FRAME_SW_MUX_REG SW_MUX_CTL_BBP_RX_CLK_BBP_TX_CLK_BBP_RX_FRAME_BBP_TX_FRAME #define BBP_RX_FRAME_BYTE_IN_SW_MUX 1 #define BBP_TX_FRAME_SW_MUX_REG SW_MUX_CTL_BBP_RX_CLK_BBP_TX_CLK_BBP_RX_FRAME_BBP_TX_FRAME #define BBP_TX_FRAME_BYTE_IN_SW_MUX 0 #define BBP_RX_DATA_SW_MUX_REG SW_MUX_CTL_BBP_RX_DATA_BBP_TX_DATA_GPIO28_GPIO29 #define BBP_RX_DATA_BYTE_IN_SW_MUX 3 #define BBP_TX_DATA_SW_MUX_REG SW_MUX_CTL_BBP_RX_DATA_BBP_TX_DATA_GPIO28_GPIO29 #define BBP_TX_DATA_BYTE_IN_SW_MUX 2 #define GPIO28_SW_MUX_REG SW_MUX_CTL_BBP_RX_DATA_BBP_TX_DATA_GPIO28_GPIO29 #define GPIO28_BYTE_IN_SW_MUX 1 #define GPIO29_SW_MUX_REG SW_MUX_CTL_BBP_RX_DATA_BBP_TX_DATA_GPIO28_GPIO29 #define GPIO29_BYTE_IN_SW_MUX 0 #define GPIO30_SW_MUX_REG SW_MUX_CTL_GPIO30_GPIO31_GPIO32_GPIO33 #define GPIO30_BYTE_IN_SW_MUX 3 #define GPIO31_SW_MUX_REG SW_MUX_CTL_GPIO30_GPIO31_GPIO32_GPIO33 #define GPIO31_BYTE_IN_SW_MUX 2 #define GPIO32_SW_MUX_REG SW_MUX_CTL_GPIO30_GPIO31_GPIO32_GPIO33 #define GPIO32_BYTE_IN_SW_MUX 1 #define GPIO33_SW_MUX_REG SW_MUX_CTL_GPIO30_GPIO31_GPIO32_GPIO33 #define GPIO33_BYTE_IN_SW_MUX 0 #define GPIO34_SW_MUX_REG SW_MUX_CTL_GPIO34_GPIO35_SDMA_EVNT0_SDMA_EVNT1 #define GPIO34_BYTE_IN_SW_MUX 3 #define GPIO35_SW_MUX_REG SW_MUX_CTL_GPIO34_GPIO35_SDMA_EVNT0_SDMA_EVNT1 #define GPIO35_BYTE_IN_SW_MUX 2 #define SDMA_EVNT0_SW_MUX_REG SW_MUX_CTL_GPIO34_GPIO35_SDMA_EVNT0_SDMA_EVNT1 #define SDMA_EVNT0_BYTE_IN_SW_MUX 1 #define SDMA_EVNT1_SW_MUX_REG SW_MUX_CTL_GPIO34_GPIO35_SDMA_EVNT0_SDMA_EVNT1 #define SDMA_EVNT1_BYTE_IN_SW_MUX 0 #define WAMMO_TX_Q_CH_SW_MUX_REG SW_MUX_CTL_WAMMO_TX_Q_CH_WAMMO_TX_I_CH_WAMMO_RX_Q_CH_WAMMO_RX_I_CH #define WAMMO_TX_Q_CH_BYTE_IN_SW_MUX 3 #define WAMMO_TX_I_CH_SW_MUX_REG SW_MUX_CTL_WAMMO_TX_Q_CH_WAMMO_TX_I_CH_WAMMO_RX_Q_CH_WAMMO_RX_I_CH #define WAMMO_TX_I_CH_BYTE_IN_SW_MUX 2 #define WAMMO_RX_Q_CH_SW_MUX_REG SW_MUX_CTL_WAMMO_TX_Q_CH_WAMMO_TX_I_CH_WAMMO_RX_Q_CH_WAMMO_RX_I_CH #define WAMMO_RX_Q_CH_BYTE_IN_SW_MUX 1 #define WAMMO_RX_I_CH_SW_MUX_REG SW_MUX_CTL_WAMMO_TX_Q_CH_WAMMO_TX_I_CH_WAMMO_RX_Q_CH_WAMMO_RX_I_CH #define WAMMO_RX_I_CH_BYTE_IN_SW_MUX 0 #define WAMMO_TX_FRAME_SW_MUX_REG SW_MUX_CTL_WAMMO_TX_FRAME_WAMMO_RX_FRAME_WAMMO_DIV_RX_I_CH_WAMMO_DIV_RX_Q_CH #define WAMMO_TX_FRAME_BYTE_IN_SW_MUX 3 #define WAMMO_RX_FRAME_SW_MUX_REG SW_MUX_CTL_WAMMO_TX_FRAME_WAMMO_RX_FRAME_WAMMO_DIV_RX_I_CH_WAMMO_DIV_RX_Q_CH #define WAMMO_RX_FRAME_BYTE_IN_SW_MUX 2 #define WAMMO_DIV_RX_I_CH_SW_MUX_REG SW_MUX_CTL_WAMMO_TX_FRAME_WAMMO_RX_FRAME_WAMMO_DIV_RX_I_CH_WAMMO_DIV_RX_Q_CH #define WAMMO_DIV_RX_I_CH_BYTE_IN_SW_MUX 1 #define WAMMO_DIV_RX_Q_CH_SW_MUX_REG SW_MUX_CTL_WAMMO_TX_FRAME_WAMMO_RX_FRAME_WAMMO_DIV_RX_I_CH_WAMMO_DIV_RX_Q_CH #define WAMMO_DIV_RX_Q_CH_BYTE_IN_SW_MUX 0 #define WAMMO_DIV_RX_FRAME_SW_MUX_REG SW_MUX_CTL_WAMMO_DIV_RX_FRAME_DSM1_STBY_DSM1_RX_ON_DSM2_STBY #define WAMMO_DIV_RX_FRAME_BYTE_IN_SW_MUX 3 #define DSM1_STBY_SW_MUX_REG SW_MUX_CTL_WAMMO_DIV_RX_FRAME_DSM1_STBY_DSM1_RX_ON_DSM2_STBY #define DSM1_STBY_BYTE_IN_SW_MUX 2 #define DSM1_RX_ON_SW_MUX_REG SW_MUX_CTL_WAMMO_DIV_RX_FRAME_DSM1_STBY_DSM1_RX_ON_DSM2_STBY #define DSM1_RX_ON_BYTE_IN_SW_MUX 1 #define DSM2_STBY_SW_MUX_REG SW_MUX_CTL_WAMMO_DIV_RX_FRAME_DSM1_STBY_DSM1_RX_ON_DSM2_STBY #define DSM2_STBY_BYTE_IN_SW_MUX 0 #define DSM2_VCO_EN_SW_MUX_REG SW_MUX_CTL_DSM2_VCO_EN_L1T1OUT0_L1T1OUT1_L1T1OUT2 #define DSM2_VCO_EN_BYTE_IN_SW_MUX 3 #define L1T1OUT0_SW_MUX_REG SW_MUX_CTL_DSM2_VCO_EN_L1T1OUT0_L1T1OUT1_L1T1OUT2 #define L1T1OUT0_BYTE_IN_SW_MUX 2 #define L1T1OUT1_SW_MUX_REG SW_MUX_CTL_DSM2_VCO_EN_L1T1OUT0_L1T1OUT1_L1T1OUT2 #define L1T1OUT1_BYTE_IN_SW_MUX 1 #define L1T1OUT2_SW_MUX_REG SW_MUX_CTL_DSM2_VCO_EN_L1T1OUT0_L1T1OUT1_L1T1OUT2 #define L1T1OUT2_BYTE_IN_SW_MUX 0 #define L1T1OUT3_SW_MUX_REG SW_MUX_CTL_L1T1OUT3_L1T1OUT4_L1T1OUT5_L1T2OUT0 #define L1T1OUT3_BYTE_IN_SW_MUX 3 #define L1T1OUT4_SW_MUX_REG SW_MUX_CTL_L1T1OUT3_L1T1OUT4_L1T1OUT5_L1T2OUT0 #define L1T1OUT4_BYTE_IN_SW_MUX 2 #define L1T1OUT5_SW_MUX_REG SW_MUX_CTL_L1T1OUT3_L1T1OUT4_L1T1OUT5_L1T2OUT0 #define L1T1OUT5_BYTE_IN_SW_MUX 1 #define L1T2OUT0_SW_MUX_REG SW_MUX_CTL_L1T1OUT3_L1T1OUT4_L1T1OUT5_L1T2OUT0 #define L1T2OUT0_BYTE_IN_SW_MUX 0 #define L1T2OUT1_SW_MUX_REG SW_MUX_CTL_L1T2OUT1_L1T2OUT2_L1T2OUT3_MQSPI1_CK #define L1T2OUT1_BYTE_IN_SW_MUX 3 #define L1T2OUT2_SW_MUX_REG SW_MUX_CTL_L1T2OUT1_L1T2OUT2_L1T2OUT3_MQSPI1_CK #define L1T2OUT2_BYTE_IN_SW_MUX 2 #define L1T2OUT3_SW_MUX_REG SW_MUX_CTL_L1T2OUT1_L1T2OUT2_L1T2OUT3_MQSPI1_CK #define L1T2OUT3_BYTE_IN_SW_MUX 1 #define MQSPI1_CK_SW_MUX_REG SW_MUX_CTL_L1T2OUT1_L1T2OUT2_L1T2OUT3_MQSPI1_CK #define MQSPI1_CK_BYTE_IN_SW_MUX 0 #define MQSPI1_DI_SW_MUX_REG SW_MUX_CTL_MQSPI1_DI_MQSPI1_DO_MQSPI1_CS0_MQSPI1_CS1 #define MQSPI1_DI_BYTE_IN_SW_MUX 3 #define MQSPI1_DO_SW_MUX_REG SW_MUX_CTL_MQSPI1_DI_MQSPI1_DO_MQSPI1_CS0_MQSPI1_CS1 #define MQSPI1_DO_BYTE_IN_SW_MUX 2 #define MQSPI1_CS0_SW_MUX_REG SW_MUX_CTL_MQSPI1_DI_MQSPI1_DO_MQSPI1_CS0_MQSPI1_CS1 #define MQSPI1_CS0_BYTE_IN_SW_MUX 1 #define MQSPI1_CS1_SW_MUX_REG SW_MUX_CTL_MQSPI1_DI_MQSPI1_DO_MQSPI1_CS0_MQSPI1_CS1 #define MQSPI1_CS1_BYTE_IN_SW_MUX 0 #define MQSPI1_CS2_SW_MUX_REG SW_MUX_CTL_MQSPI1_CS2_MQSPI2_CK_MQSPI2_DI_MQSPI2_DO #define MQSPI1_CS2_BYTE_IN_SW_MUX 3 #define MQSPI2_CK_SW_MUX_REG SW_MUX_CTL_MQSPI1_CS2_MQSPI2_CK_MQSPI2_DI_MQSPI2_DO #define MQSPI2_CK_BYTE_IN_SW_MUX 2 #define MQSPI2_DI_SW_MUX_REG SW_MUX_CTL_MQSPI1_CS2_MQSPI2_CK_MQSPI2_DI_MQSPI2_DO #define MQSPI2_DI_BYTE_IN_SW_MUX 1 #define MQSPI2_DO_SW_MUX_REG SW_MUX_CTL_MQSPI1_CS2_MQSPI2_CK_MQSPI2_DI_MQSPI2_DO #define MQSPI2_DO_BYTE_IN_SW_MUX 0 #define MQSPI2_CS0_SW_MUX_REG SW_MUX_CTL_MQSPI2_CS0_MQSPI2_CS1_UART_TXD3_UART_RXD3 #define MQSPI2_CS0_BYTE_IN_SW_MUX 3 #define MQSPI2_CS1_SW_MUX_REG SW_MUX_CTL_MQSPI2_CS0_MQSPI2_CS1_UART_TXD3_UART_RXD3 #define MQSPI2_CS1_BYTE_IN_SW_MUX 2 #define UART_TXD3_SW_MUX_REG SW_MUX_CTL_MQSPI2_CS0_MQSPI2_CS1_UART_TXD3_UART_RXD3 #define UART_TXD3_BYTE_IN_SW_MUX 1 #define UART_RXD3_SW_MUX_REG SW_MUX_CTL_MQSPI2_CS0_MQSPI2_CS1_UART_TXD3_UART_RXD3 #define UART_RXD3_BYTE_IN_SW_MUX 0 #define UART_RTS3_B_SW_MUX_REG SW_MUX_CTL_UART_RTS3_B_UART_CTS3_B_GPIO0_GPIO1 #define UART_RTS3_B_BYTE_IN_SW_MUX 3 #define UART_CTS3_B_SW_MUX_REG SW_MUX_CTL_UART_RTS3_B_UART_CTS3_B_GPIO0_GPIO1 #define UART_CTS3_B_BYTE_IN_SW_MUX 2 #define GPIO0_SW_MUX_REG SW_MUX_CTL_UART_RTS3_B_UART_CTS3_B_GPIO0_GPIO1 #define GPIO0_BYTE_IN_SW_MUX 1 #define GPIO1_SW_MUX_REG SW_MUX_CTL_UART_RTS3_B_UART_CTS3_B_GPIO0_GPIO1 #define GPIO1_BYTE_IN_SW_MUX 0 #define GPIO2_SW_MUX_REG SW_MUX_CTL_GPIO2_GPIO3_GPIO4_GPIO5 #define GPIO2_BYTE_IN_SW_MUX 3 #define GPIO3_SW_MUX_REG SW_MUX_CTL_GPIO2_GPIO3_GPIO4_GPIO5 #define GPIO3_BYTE_IN_SW_MUX 2 #define GPIO4_SW_MUX_REG SW_MUX_CTL_GPIO2_GPIO3_GPIO4_GPIO5 #define GPIO4_BYTE_IN_SW_MUX 1 #define GPIO5_SW_MUX_REG SW_MUX_CTL_GPIO2_GPIO3_GPIO4_GPIO5 #define GPIO5_BYTE_IN_SW_MUX 0 #define GPIO6_SW_MUX_REG SW_MUX_CTL_GPIO6_GPIO7_GPIO8_GPIO9 #define GPIO6_BYTE_IN_SW_MUX 3 #define GPIO7_SW_MUX_REG SW_MUX_CTL_GPIO6_GPIO7_GPIO8_GPIO9 #define GPIO7_BYTE_IN_SW_MUX 2 #define GPIO8_SW_MUX_REG SW_MUX_CTL_GPIO6_GPIO7_GPIO8_GPIO9 #define GPIO8_BYTE_IN_SW_MUX 1 #define GPIO9_SW_MUX_REG SW_MUX_CTL_GPIO6_GPIO7_GPIO8_GPIO9 #define GPIO9_BYTE_IN_SW_MUX 0 #define GPIO10_SW_MUX_REG SW_MUX_CTL_GPIO10_GPIO11_GPIO12_GPIO13 #define GPIO10_BYTE_IN_SW_MUX 3 #define GPIO11_SW_MUX_REG SW_MUX_CTL_GPIO10_GPIO11_GPIO12_GPIO13 #define GPIO11_BYTE_IN_SW_MUX 2 #define GPIO12_SW_MUX_REG SW_MUX_CTL_GPIO10_GPIO11_GPIO12_GPIO13 #define GPIO12_BYTE_IN_SW_MUX 1 #define GPIO13_SW_MUX_REG SW_MUX_CTL_GPIO10_GPIO11_GPIO12_GPIO13 #define GPIO13_BYTE_IN_SW_MUX 0 #define GPIO14_SW_MUX_REG SW_MUX_CTL_GPIO14_GPIO15_GPIO16_GPIO17 #define GPIO14_BYTE_IN_SW_MUX 3 #define GPIO15_SW_MUX_REG SW_MUX_CTL_GPIO14_GPIO15_GPIO16_GPIO17 #define GPIO15_BYTE_IN_SW_MUX 2 #define GPIO16_SW_MUX_REG SW_MUX_CTL_GPIO14_GPIO15_GPIO16_GPIO17 #define GPIO16_BYTE_IN_SW_MUX 1 #define GPIO17_SW_MUX_REG SW_MUX_CTL_GPIO14_GPIO15_GPIO16_GPIO17 #define GPIO17_BYTE_IN_SW_MUX 0 #define GPIO36_SW_MUX_REG SW_MUX_CTL_GPIO36_GPIO37_GPIO18_GPIO19 #define GPIO36_BYTE_IN_SW_MUX 3 #define GPIO37_SW_MUX_REG SW_MUX_CTL_GPIO36_GPIO37_GPIO18_GPIO19 #define GPIO37_BYTE_IN_SW_MUX 2 #define GPIO18_SW_MUX_REG SW_MUX_CTL_GPIO36_GPIO37_GPIO18_GPIO19 #define GPIO18_BYTE_IN_SW_MUX 1 #define GPIO19_SW_MUX_REG SW_MUX_CTL_GPIO36_GPIO37_GPIO18_GPIO19 #define GPIO19_BYTE_IN_SW_MUX 0 #define GPIO20_SW_MUX_REG SW_MUX_CTL_GPIO20_GPIO21_GPIO22_GPIO23 #define GPIO20_BYTE_IN_SW_MUX 3 #define GPIO21_SW_MUX_REG SW_MUX_CTL_GPIO20_GPIO21_GPIO22_GPIO23 #define GPIO21_BYTE_IN_SW_MUX 2 #define GPIO22_SW_MUX_REG SW_MUX_CTL_GPIO20_GPIO21_GPIO22_GPIO23 #define GPIO22_BYTE_IN_SW_MUX 1 #define GPIO23_SW_MUX_REG SW_MUX_CTL_GPIO20_GPIO21_GPIO22_GPIO23 #define GPIO23_BYTE_IN_SW_MUX 0 #define GPIO24_SW_MUX_REG SW_MUX_CTL_GPIO24_GPIO25_GPIO26_GPIO27 #define GPIO24_BYTE_IN_SW_MUX 3 #define GPIO25_SW_MUX_REG SW_MUX_CTL_GPIO24_GPIO25_GPIO26_GPIO27 #define GPIO25_BYTE_IN_SW_MUX 2 #define GPIO26_SW_MUX_REG SW_MUX_CTL_GPIO24_GPIO25_GPIO26_GPIO27 #define GPIO26_BYTE_IN_SW_MUX 1 #define GPIO27_SW_MUX_REG SW_MUX_CTL_GPIO24_GPIO25_GPIO26_GPIO27 #define GPIO27_BYTE_IN_SW_MUX 0 #define UART_TXD1_SW_MUX_REG SW_MUX_CTL_UART_TXD1_UART_RXD1_UART_RTS1_B_UART_CTS1_B #define UART_TXD1_BYTE_IN_SW_MUX 3 #define UART_RXD1_SW_MUX_REG SW_MUX_CTL_UART_TXD1_UART_RXD1_UART_RTS1_B_UART_CTS1_B #define UART_RXD1_BYTE_IN_SW_MUX 2 #define UART_RTS1_B_SW_MUX_REG SW_MUX_CTL_UART_TXD1_UART_RXD1_UART_RTS1_B_UART_CTS1_B #define UART_RTS1_B_BYTE_IN_SW_MUX 1 #define UART_CTS1_B_SW_MUX_REG SW_MUX_CTL_UART_TXD1_UART_RXD1_UART_RTS1_B_UART_CTS1_B #define UART_CTS1_B_BYTE_IN_SW_MUX 0 #define UART_CTS2_B_SW_MUX_REG SW_MUX_CTL_UART_CTS2_B_UART_DTR2_B_UART_RI2_B_UART_DCD2_B #define UART_CTS2_B_BYTE_IN_SW_MUX 3 #define UART_DTR2_B_SW_MUX_REG SW_MUX_CTL_UART_CTS2_B_UART_DTR2_B_UART_RI2_B_UART_DCD2_B #define UART_DTR2_B_BYTE_IN_SW_MUX 2 #define UART_RI2_B_SW_MUX_REG SW_MUX_CTL_UART_CTS2_B_UART_DTR2_B_UART_RI2_B_UART_DCD2_B #define UART_RI2_B_BYTE_IN_SW_MUX 1 #define UART_DCD2_B_SW_MUX_REG SW_MUX_CTL_UART_CTS2_B_UART_DTR2_B_UART_RI2_B_UART_DCD2_B #define UART_DCD2_B_BYTE_IN_SW_MUX 0 #define UART_DSR2_B_SW_MUX_REG SW_MUX_CTL_UART_DSR2_B_UART_MUXCTL_IRDA_TX4_IRDA_RX4 #define UART_DSR2_B_BYTE_IN_SW_MUX 3 #define UART_MUXCTL_SW_MUX_REG SW_MUX_CTL_UART_DSR2_B_UART_MUXCTL_IRDA_TX4_IRDA_RX4 #define UART_MUXCTL_BYTE_IN_SW_MUX 2 #define IRDA_TX4_SW_MUX_REG SW_MUX_CTL_UART_DSR2_B_UART_MUXCTL_IRDA_TX4_IRDA_RX4 #define IRDA_TX4_BYTE_IN_SW_MUX 1 #define IRDA_RX4_SW_MUX_REG SW_MUX_CTL_UART_DSR2_B_UART_MUXCTL_IRDA_TX4_IRDA_RX4 #define IRDA_RX4_BYTE_IN_SW_MUX 0 #define DAM1_TXD_SW_MUX_REG SW_MUX_CTL_DAM1_TXD_DAM1_RXD_DAM1_T_CLK_DAM1_T_FS #define DAM1_TXD_BYTE_IN_SW_MUX 3 #define DAM1_RXD_SW_MUX_REG SW_MUX_CTL_DAM1_TXD_DAM1_RXD_DAM1_T_CLK_DAM1_T_FS #define DAM1_RXD_BYTE_IN_SW_MUX 2 #define DAM1_T_CLK_SW_MUX_REG SW_MUX_CTL_DAM1_TXD_DAM1_RXD_DAM1_T_CLK_DAM1_T_FS #define DAM1_T_CLK_BYTE_IN_SW_MUX 1 #define DAM1_T_FS_SW_MUX_REG SW_MUX_CTL_DAM1_TXD_DAM1_RXD_DAM1_T_CLK_DAM1_T_FS #define DAM1_T_FS_BYTE_IN_SW_MUX 0 #define DAM2_TXD_SW_MUX_REG SW_MUX_CTL_DAM2_TXD_DAM2_RXD_DAM2_T_CLK_DAM2_T_FS #define DAM2_TXD_BYTE_IN_SW_MUX 3 #define DAM2_RXD_SW_MUX_REG SW_MUX_CTL_DAM2_TXD_DAM2_RXD_DAM2_T_CLK_DAM2_T_FS #define DAM2_RXD_BYTE_IN_SW_MUX 2 #define DAM2_T_CLK_SW_MUX_REG SW_MUX_CTL_DAM2_TXD_DAM2_RXD_DAM2_T_CLK_DAM2_T_FS #define DAM2_T_CLK_BYTE_IN_SW_MUX 1 #define DAM2_T_FS_SW_MUX_REG SW_MUX_CTL_DAM2_TXD_DAM2_RXD_DAM2_T_CLK_DAM2_T_FS #define DAM2_T_FS_BYTE_IN_SW_MUX 0 #define DAM3_TXD_SW_MUX_REG SW_MUX_CTL_DAM3_TXD_DAM3_RXD_DAM3_T_CLK_DAM3_T_FS #define DAM3_TXD_BYTE_IN_SW_MUX 3 #define DAM3_RXD_SW_MUX_REG SW_MUX_CTL_DAM3_TXD_DAM3_RXD_DAM3_T_CLK_DAM3_T_FS #define DAM3_RXD_BYTE_IN_SW_MUX 2 #define DAM3_T_CLK_SW_MUX_REG SW_MUX_CTL_DAM3_TXD_DAM3_RXD_DAM3_T_CLK_DAM3_T_FS #define DAM3_T_CLK_BYTE_IN_SW_MUX 1 #define DAM3_T_FS_SW_MUX_REG SW_MUX_CTL_DAM3_TXD_DAM3_RXD_DAM3_T_CLK_DAM3_T_FS #define DAM3_T_FS_BYTE_IN_SW_MUX 0 #define DAM3_R_CLK_SW_MUX_REG SW_MUX_CTL_DAM3_R_CLK_DAM3_R_FS_BATT_LINE_PWM #define DAM3_R_CLK_BYTE_IN_SW_MUX 3 #define DAM3_R_FS_SW_MUX_REG SW_MUX_CTL_DAM3_R_CLK_DAM3_R_FS_BATT_LINE_PWM #define DAM3_R_FS_BYTE_IN_SW_MUX 2 #define BATT_LINE_SW_MUX_REG SW_MUX_CTL_DAM3_R_CLK_DAM3_R_FS_BATT_LINE_PWM #define BATT_LINE_BYTE_IN_SW_MUX 1 #define PWM_SW_MUX_REG SW_MUX_CTL_DAM3_R_CLK_DAM3_R_FS_BATT_LINE_PWM #define PWM_BYTE_IN_SW_MUX 0 #define CSPI2_CK_SW_MUX_REG SW_MUX_CTL_CSPI2_CK_CSPI2_DO_CSPI2_DI_CSPI2_CS_0 #define CSPI2_CK_BYTE_IN_SW_MUX 3 #define CSPI2_DO_SW_MUX_REG SW_MUX_CTL_CSPI2_CK_CSPI2_DO_CSPI2_DI_CSPI2_CS_0 #define CSPI2_DO_BYTE_IN_SW_MUX 2 #define CSPI2_DI_SW_MUX_REG SW_MUX_CTL_CSPI2_CK_CSPI2_DO_CSPI2_DI_CSPI2_CS_0 #define CSPI2_DI_BYTE_IN_SW_MUX 1 #define CSPI2_CS_0_SW_MUX_REG SW_MUX_CTL_CSPI2_CK_CSPI2_DO_CSPI2_DI_CSPI2_CS_0 #define CSPI2_CS_0_BYTE_IN_SW_MUX 0 #define CSPI2_CS_1_SW_MUX_REG SW_MUX_CTL_CSPI2_CS_1_CSPI1_CK_CSPI1_DO_CSPI1_DI #define CSPI2_CS_1_BYTE_IN_SW_MUX 3 #define CSPI1_CK_SW_MUX_REG SW_MUX_CTL_CSPI2_CS_1_CSPI1_CK_CSPI1_DO_CSPI1_DI #define CSPI1_CK_BYTE_IN_SW_MUX 2 #define CSPI1_DO_SW_MUX_REG SW_MUX_CTL_CSPI2_CS_1_CSPI1_CK_CSPI1_DO_CSPI1_DI #define CSPI1_DO_BYTE_IN_SW_MUX 1 #define CSPI1_DI_SW_MUX_REG SW_MUX_CTL_CSPI2_CS_1_CSPI1_CK_CSPI1_DO_CSPI1_DI #define CSPI1_DI_BYTE_IN_SW_MUX 0 #define CSPI1_CS_0_SW_MUX_REG SW_MUX_CTL_CSPI1_CS_0_CSPI1_CS_1_IPU_FDAT_0_IPU_FDAT_1 #define CSPI1_CS_0_BYTE_IN_SW_MUX 3 #define CSPI1_CS_1_SW_MUX_REG SW_MUX_CTL_CSPI1_CS_0_CSPI1_CS_1_IPU_FDAT_0_IPU_FDAT_1 #define CSPI1_CS_1_BYTE_IN_SW_MUX 2 #define IPU_FDAT_0_SW_MUX_REG SW_MUX_CTL_CSPI1_CS_0_CSPI1_CS_1_IPU_FDAT_0_IPU_FDAT_1 #define IPU_FDAT_0_BYTE_IN_SW_MUX 1 #define IPU_FDAT_1_SW_MUX_REG SW_MUX_CTL_CSPI1_CS_0_CSPI1_CS_1_IPU_FDAT_0_IPU_FDAT_1 #define IPU_FDAT_1_BYTE_IN_SW_MUX 0 #define IPU_FDAT_2_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_2_IPU_FDAT_3_IPU_FDAT_4_IPU_FDAT_5 #define IPU_FDAT_2_BYTE_IN_SW_MUX 3 #define IPU_FDAT_3_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_2_IPU_FDAT_3_IPU_FDAT_4_IPU_FDAT_5 #define IPU_FDAT_3_BYTE_IN_SW_MUX 2 #define IPU_FDAT_4_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_2_IPU_FDAT_3_IPU_FDAT_4_IPU_FDAT_5 #define IPU_FDAT_4_BYTE_IN_SW_MUX 1 #define IPU_FDAT_5_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_2_IPU_FDAT_3_IPU_FDAT_4_IPU_FDAT_5 #define IPU_FDAT_5_BYTE_IN_SW_MUX 0 #define IPU_FDAT_6_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_6_IPU_FDAT_7_IPU_FDAT_8_IPU_FDAT_9 #define IPU_FDAT_6_BYTE_IN_SW_MUX 3 #define IPU_FDAT_7_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_6_IPU_FDAT_7_IPU_FDAT_8_IPU_FDAT_9 #define IPU_FDAT_7_BYTE_IN_SW_MUX 2 #define IPU_FDAT_8_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_6_IPU_FDAT_7_IPU_FDAT_8_IPU_FDAT_9 #define IPU_FDAT_8_BYTE_IN_SW_MUX 1 #define IPU_FDAT_9_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_6_IPU_FDAT_7_IPU_FDAT_8_IPU_FDAT_9 #define IPU_FDAT_9_BYTE_IN_SW_MUX 0 #define IPU_FDAT_10_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_10_IPU_FDAT_11_IPU_FDAT_12_IPU_FDAT_13 #define IPU_FDAT_10_BYTE_IN_SW_MUX 3 #define IPU_FDAT_11_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_10_IPU_FDAT_11_IPU_FDAT_12_IPU_FDAT_13 #define IPU_FDAT_11_BYTE_IN_SW_MUX 2 #define IPU_FDAT_12_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_10_IPU_FDAT_11_IPU_FDAT_12_IPU_FDAT_13 #define IPU_FDAT_12_BYTE_IN_SW_MUX 1 #define IPU_FDAT_13_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_10_IPU_FDAT_11_IPU_FDAT_12_IPU_FDAT_13 #define IPU_FDAT_13_BYTE_IN_SW_MUX 0 #define IPU_FDAT_14_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_14_IPU_FDAT_15_IPU_FDAT_16_IPU_FDAT_17 #define IPU_FDAT_14_BYTE_IN_SW_MUX 3 #define IPU_FDAT_15_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_14_IPU_FDAT_15_IPU_FDAT_16_IPU_FDAT_17 #define IPU_FDAT_15_BYTE_IN_SW_MUX 2 #define IPU_FDAT_16_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_14_IPU_FDAT_15_IPU_FDAT_16_IPU_FDAT_17 #define IPU_FDAT_16_BYTE_IN_SW_MUX 1 #define IPU_FDAT_17_SW_MUX_REG SW_MUX_CTL_IPU_FDAT_14_IPU_FDAT_15_IPU_FDAT_16_IPU_FDAT_17 #define IPU_FDAT_17_BYTE_IN_SW_MUX 0 #define IPU_VSYNC0_SW_MUX_REG SW_MUX_CTL_IPU_VSYNC0_IPU_HSYNC_IPU_VSYNC3_IPU_LCS0 #define IPU_VSYNC0_BYTE_IN_SW_MUX 3 #define IPU_HSYNC_SW_MUX_REG SW_MUX_CTL_IPU_VSYNC0_IPU_HSYNC_IPU_VSYNC3_IPU_LCS0 #define IPU_HSYNC_BYTE_IN_SW_MUX 2 #define IPU_VSYNC3_SW_MUX_REG SW_MUX_CTL_IPU_VSYNC0_IPU_HSYNC_IPU_VSYNC3_IPU_LCS0 #define IPU_VSYNC3_BYTE_IN_SW_MUX 1 #define IPU_LCS0_SW_MUX_REG SW_MUX_CTL_IPU_VSYNC0_IPU_HSYNC_IPU_VSYNC3_IPU_LCS0 #define IPU_LCS0_BYTE_IN_SW_MUX 0 #define IPU_FPSHIFT_SW_MUX_REG SW_MUX_CTL_IPU_FPSHIFT_IPU_DRDY0_IPU_CONTRAST1_IPU_LCS1 #define IPU_FPSHIFT_BYTE_IN_SW_MUX 3 #define IPU_DRDY0_SW_MUX_REG SW_MUX_CTL_IPU_FPSHIFT_IPU_DRDY0_IPU_CONTRAST1_IPU_LCS1 #define IPU_DRDY0_BYTE_IN_SW_MUX 2 #define IPU_CONTRAST1_SW_MUX_REG SW_MUX_CTL_IPU_FPSHIFT_IPU_DRDY0_IPU_CONTRAST1_IPU_LCS1 #define IPU_CONTRAST1_BYTE_IN_SW_MUX 1 #define IPU_LCS1_SW_MUX_REG SW_MUX_CTL_IPU_FPSHIFT_IPU_DRDY0_IPU_CONTRAST1_IPU_LCS1 #define IPU_LCS1_BYTE_IN_SW_MUX 0 #define IPU_SD_D_IO_SW_MUX_REG SW_MUX_CTL_IPU_SD_D_IO_IPU_SD_D_O_IPU_SD_D_CLK_IPU_SER_RS #define IPU_SD_D_IO_BYTE_IN_SW_MUX 3 #define IPU_SD_D_O_SW_MUX_REG SW_MUX_CTL_IPU_SD_D_IO_IPU_SD_D_O_IPU_SD_D_CLK_IPU_SER_RS #define IPU_SD_D_O_BYTE_IN_SW_MUX 2 #define IPU_SD_D_CLK_SW_MUX_REG SW_MUX_CTL_IPU_SD_D_IO_IPU_SD_D_O_IPU_SD_D_CLK_IPU_SER_RS #define IPU_SD_D_CLK_BYTE_IN_SW_MUX 1 #define IPU_SER_RS_SW_MUX_REG SW_MUX_CTL_IPU_SD_D_IO_IPU_SD_D_O_IPU_SD_D_CLK_IPU_SER_RS #define IPU_SER_RS_BYTE_IN_SW_MUX 0 #define IPU_PAR_RS_SW_MUX_REG SW_MUX_CTL_IPU_PAR_RS_IPU_WRITE_IPU_READ_IPU_D3_CLS #define IPU_PAR_RS_BYTE_IN_SW_MUX 3 #define IPU_WRITE_SW_MUX_REG SW_MUX_CTL_IPU_PAR_RS_IPU_WRITE_IPU_READ_IPU_D3_CLS #define IPU_WRITE_BYTE_IN_SW_MUX 2 #define IPU_READ_SW_MUX_REG SW_MUX_CTL_IPU_PAR_RS_IPU_WRITE_IPU_READ_IPU_D3_CLS #define IPU_READ_BYTE_IN_SW_MUX 1 #define IPU_D3_CLS_SW_MUX_REG SW_MUX_CTL_IPU_PAR_RS_IPU_WRITE_IPU_READ_IPU_D3_CLS #define IPU_D3_CLS_BYTE_IN_SW_MUX 0 #define IPU_D3_SPL_SW_MUX_REG SW_MUX_CTL_IPU_D3_SPL_IPU_D3_REV_IPU_CSI_MCLK_IPU_CSI_HSYNC #define IPU_D3_SPL_BYTE_IN_SW_MUX 3 #define IPU_D3_REV_SW_MUX_REG SW_MUX_CTL_IPU_D3_SPL_IPU_D3_REV_IPU_CSI_MCLK_IPU_CSI_HSYNC #define IPU_D3_REV_BYTE_IN_SW_MUX 2 #define IPU_CSI_MCLK_SW_MUX_REG SW_MUX_CTL_IPU_D3_SPL_IPU_D3_REV_IPU_CSI_MCLK_IPU_CSI_HSYNC #define IPU_CSI_MCLK_BYTE_IN_SW_MUX 1 #define IPU_CSI_HSYNC_SW_MUX_REG SW_MUX_CTL_IPU_D3_SPL_IPU_D3_REV_IPU_CSI_MCLK_IPU_CSI_HSYNC #define IPU_CSI_HSYNC_BYTE_IN_SW_MUX 0 #define IPU_CSI_VSYNC_SW_MUX_REG SW_MUX_CTL_IPU_CSI_VSYNC_IPU_CSI_DATA_0_IPU_CSI_DATA_1_IPU_CSI_DATA_2 #define IPU_CSI_VSYNC_BYTE_IN_SW_MUX 3 #define IPU_CSI_DATA_0_SW_MUX_REG SW_MUX_CTL_IPU_CSI_VSYNC_IPU_CSI_DATA_0_IPU_CSI_DATA_1_IPU_CSI_DATA_2 #define IPU_CSI_DATA_0_BYTE_IN_SW_MUX 2 #define IPU_CSI_DATA_1_SW_MUX_REG SW_MUX_CTL_IPU_CSI_VSYNC_IPU_CSI_DATA_0_IPU_CSI_DATA_1_IPU_CSI_DATA_2 #define IPU_CSI_DATA_1_BYTE_IN_SW_MUX 1 #define IPU_CSI_DATA_2_SW_MUX_REG SW_MUX_CTL_IPU_CSI_VSYNC_IPU_CSI_DATA_0_IPU_CSI_DATA_1_IPU_CSI_DATA_2 #define IPU_CSI_DATA_2_BYTE_IN_SW_MUX 0 #define IPU_CSI_DATA_3_SW_MUX_REG SW_MUX_CTL_IPU_CSI_DATA_3_IPU_CSI_DATA_4_IPU_CSI_DATA_5_IPU_CSI_DATA_6 #define IPU_CSI_DATA_3_BYTE_IN_SW_MUX 3 #define IPU_CSI_DATA_4_SW_MUX_REG SW_MUX_CTL_IPU_CSI_DATA_3_IPU_CSI_DATA_4_IPU_CSI_DATA_5_IPU_CSI_DATA_6 #define IPU_CSI_DATA_4_BYTE_IN_SW_MUX 2 #define IPU_CSI_DATA_5_SW_MUX_REG SW_MUX_CTL_IPU_CSI_DATA_3_IPU_CSI_DATA_4_IPU_CSI_DATA_5_IPU_CSI_DATA_6 #define IPU_CSI_DATA_5_BYTE_IN_SW_MUX 1 #define IPU_CSI_DATA_6_SW_MUX_REG SW_MUX_CTL_IPU_CSI_DATA_3_IPU_CSI_DATA_4_IPU_CSI_DATA_5_IPU_CSI_DATA_6 #define IPU_CSI_DATA_6_BYTE_IN_SW_MUX 0 #define IPU_CSI_DATA_7_SW_MUX_REG SW_MUX_CTL_IPU_CSI_DATA_7_IPU_CSI_DATA_8_IPU_CSI_DATA_9_IPU_CSI_PIXCLK #define IPU_CSI_DATA_7_BYTE_IN_SW_MUX 3 #define IPU_CSI_DATA_8_SW_MUX_REG SW_MUX_CTL_IPU_CSI_DATA_7_IPU_CSI_DATA_8_IPU_CSI_DATA_9_IPU_CSI_PIXCLK #define IPU_CSI_DATA_8_BYTE_IN_SW_MUX 2 #define IPU_CSI_DATA_9_SW_MUX_REG SW_MUX_CTL_IPU_CSI_DATA_7_IPU_CSI_DATA_8_IPU_CSI_DATA_9_IPU_CSI_PIXCLK #define IPU_CSI_DATA_9_BYTE_IN_SW_MUX 1 #define IPU_CSI_PIXCLK_SW_MUX_REG SW_MUX_CTL_IPU_CSI_DATA_7_IPU_CSI_DATA_8_IPU_CSI_DATA_9_IPU_CSI_PIXCLK #define IPU_CSI_PIXCLK_BYTE_IN_SW_MUX 0 #define I2C_CLK_SW_MUX_REG SW_MUX_CTL_I2C_CLK_I2C_DAT_KEY_ROW0_KEY_ROW1 #define I2C_CLK_BYTE_IN_SW_MUX 3 #define I2C_DAT_SW_MUX_REG SW_MUX_CTL_I2C_CLK_I2C_DAT_KEY_ROW0_KEY_ROW1 #define I2C_DAT_BYTE_IN_SW_MUX 2 #define KEY_ROW0_SW_MUX_REG SW_MUX_CTL_I2C_CLK_I2C_DAT_KEY_ROW0_KEY_ROW1 #define KEY_ROW0_BYTE_IN_SW_MUX 1 #define KEY_ROW1_SW_MUX_REG SW_MUX_CTL_I2C_CLK_I2C_DAT_KEY_ROW0_KEY_ROW1 #define KEY_ROW1_BYTE_IN_SW_MUX 0 #define KEY_ROW2_SW_MUX_REG SW_MUX_CTL_KEY_ROW2_KEY_ROW3_KEY_ROW4_KEY_ROW5 #define KEY_ROW2_BYTE_IN_SW_MUX 3 #define KEY_ROW3_SW_MUX_REG SW_MUX_CTL_KEY_ROW2_KEY_ROW3_KEY_ROW4_KEY_ROW5 #define KEY_ROW3_BYTE_IN_SW_MUX 2 #define KEY_ROW4_SW_MUX_REG SW_MUX_CTL_KEY_ROW2_KEY_ROW3_KEY_ROW4_KEY_ROW5 #define KEY_ROW4_BYTE_IN_SW_MUX 1 #define KEY_ROW5_SW_MUX_REG SW_MUX_CTL_KEY_ROW2_KEY_ROW3_KEY_ROW4_KEY_ROW5 #define KEY_ROW5_BYTE_IN_SW_MUX 0 #define KEY_ROW6_SW_MUX_REG SW_MUX_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0_KEY_COL1 #define KEY_ROW6_BYTE_IN_SW_MUX 3 #define KEY_ROW7_SW_MUX_REG SW_MUX_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0_KEY_COL1 #define KEY_ROW7_BYTE_IN_SW_MUX 2 #define KEY_COL0_SW_MUX_REG SW_MUX_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0_KEY_COL1 #define KEY_COL0_BYTE_IN_SW_MUX 1 #define KEY_COL1_SW_MUX_REG SW_MUX_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0_KEY_COL1 #define KEY_COL1_BYTE_IN_SW_MUX 0 #define KEY_COL2_SW_MUX_REG SW_MUX_CTL_KEY_COL2_KEY_COL3_KEY_COL4_KEY_COL5 #define KEY_COL2_BYTE_IN_SW_MUX 3 #define KEY_COL3_SW_MUX_REG SW_MUX_CTL_KEY_COL2_KEY_COL3_KEY_COL4_KEY_COL5 #define KEY_COL3_BYTE_IN_SW_MUX 2 #define KEY_COL4_SW_MUX_REG SW_MUX_CTL_KEY_COL2_KEY_COL3_KEY_COL4_KEY_COL5 #define KEY_COL4_BYTE_IN_SW_MUX 1 #define KEY_COL5_SW_MUX_REG SW_MUX_CTL_KEY_COL2_KEY_COL3_KEY_COL4_KEY_COL5 #define KEY_COL5_BYTE_IN_SW_MUX 0 #define KEY_COL6_SW_MUX_REG SW_MUX_CTL_KEY_COL6_KEY_COL7_MMC1_CMD_MMC1_DATA_0 #define KEY_COL6_BYTE_IN_SW_MUX 3 #define KEY_COL7_SW_MUX_REG SW_MUX_CTL_KEY_COL6_KEY_COL7_MMC1_CMD_MMC1_DATA_0 #define KEY_COL7_BYTE_IN_SW_MUX 2 #define MMC1_CMD_SW_MUX_REG SW_MUX_CTL_KEY_COL6_KEY_COL7_MMC1_CMD_MMC1_DATA_0 #define MMC1_CMD_BYTE_IN_SW_MUX 1 #define MMC1_DATA_0_SW_MUX_REG SW_MUX_CTL_KEY_COL6_KEY_COL7_MMC1_CMD_MMC1_DATA_0 #define MMC1_DATA_0_BYTE_IN_SW_MUX 0 #define MMC1_DATA_1_SW_MUX_REG SW_MUX_CTL_MMC1_DATA_1_MMC1_DATA_2_MMC1_DATA_3_MMC1_CLK #define MMC1_DATA_1_BYTE_IN_SW_MUX 3 #define MMC1_DATA_2_SW_MUX_REG SW_MUX_CTL_MMC1_DATA_1_MMC1_DATA_2_MMC1_DATA_3_MMC1_CLK #define MMC1_DATA_2_BYTE_IN_SW_MUX 2 #define MMC1_DATA_3_SW_MUX_REG SW_MUX_CTL_MMC1_DATA_1_MMC1_DATA_2_MMC1_DATA_3_MMC1_CLK #define MMC1_DATA_3_BYTE_IN_SW_MUX 1 #define MMC1_CLK_SW_MUX_REG SW_MUX_CTL_MMC1_DATA_1_MMC1_DATA_2_MMC1_DATA_3_MMC1_CLK #define MMC1_CLK_BYTE_IN_SW_MUX 0 #define MMC1_SDDET_SW_MUX_REG SW_MUX_CTL_MMC1_SDDET_MMC2_CMD_MMC2_DATA_0_MMC2_DATA_1 #define MMC1_SDDET_BYTE_IN_SW_MUX 3 #define MMC2_CMD_SW_MUX_REG SW_MUX_CTL_MMC1_SDDET_MMC2_CMD_MMC2_DATA_0_MMC2_DATA_1 #define MMC2_CMD_BYTE_IN_SW_MUX 2 #define MMC2_DATA_0_SW_MUX_REG SW_MUX_CTL_MMC1_SDDET_MMC2_CMD_MMC2_DATA_0_MMC2_DATA_1 #define MMC2_DATA_0_BYTE_IN_SW_MUX 1 #define MMC2_DATA_1_SW_MUX_REG SW_MUX_CTL_MMC1_SDDET_MMC2_CMD_MMC2_DATA_0_MMC2_DATA_1 #define MMC2_DATA_1_BYTE_IN_SW_MUX 0 #define MMC2_DATA_2_SW_MUX_REG SW_MUX_CTL_MMC2_DATA_2_MMC2_DATA_3_MMC2_CLK_TRACE0 #define MMC2_DATA_2_BYTE_IN_SW_MUX 3 #define MMC2_DATA_3_SW_MUX_REG SW_MUX_CTL_MMC2_DATA_2_MMC2_DATA_3_MMC2_CLK_TRACE0 #define MMC2_DATA_3_BYTE_IN_SW_MUX 2 #define MMC2_CLK_SW_MUX_REG SW_MUX_CTL_MMC2_DATA_2_MMC2_DATA_3_MMC2_CLK_TRACE0 #define MMC2_CLK_BYTE_IN_SW_MUX 1 #define TRACE0_SW_MUX_REG SW_MUX_CTL_MMC2_DATA_2_MMC2_DATA_3_MMC2_CLK_TRACE0 #define TRACE0_BYTE_IN_SW_MUX 0 #define TRACE1_SW_MUX_REG SW_MUX_CTL_TRACE1_TRACE2_TRACE3_TRACE4 #define TRACE1_BYTE_IN_SW_MUX 3 #define TRACE2_SW_MUX_REG SW_MUX_CTL_TRACE1_TRACE2_TRACE3_TRACE4 #define TRACE2_BYTE_IN_SW_MUX 2 #define TRACE3_SW_MUX_REG SW_MUX_CTL_TRACE1_TRACE2_TRACE3_TRACE4 #define TRACE3_BYTE_IN_SW_MUX 1 #define TRACE4_SW_MUX_REG SW_MUX_CTL_TRACE1_TRACE2_TRACE3_TRACE4 #define TRACE4_BYTE_IN_SW_MUX 0 #define TRACE5_SW_MUX_REG SW_MUX_CTL_TRACE5_TRACE6_TRACE7_TRACE8 #define TRACE5_BYTE_IN_SW_MUX 3 #define TRACE6_SW_MUX_REG SW_MUX_CTL_TRACE5_TRACE6_TRACE7_TRACE8 #define TRACE6_BYTE_IN_SW_MUX 2 #define TRACE7_SW_MUX_REG SW_MUX_CTL_TRACE5_TRACE6_TRACE7_TRACE8 #define TRACE7_BYTE_IN_SW_MUX 1 #define TRACE8_SW_MUX_REG SW_MUX_CTL_TRACE5_TRACE6_TRACE7_TRACE8 #define TRACE8_BYTE_IN_SW_MUX 0 #define TRACE9_SW_MUX_REG SW_MUX_CTL_TRACE9_TRACE10_TRACE11_TRACE12 #define TRACE9_BYTE_IN_SW_MUX 3 #define TRACE10_SW_MUX_REG SW_MUX_CTL_TRACE9_TRACE10_TRACE11_TRACE12 #define TRACE10_BYTE_IN_SW_MUX 2 #define TRACE11_SW_MUX_REG SW_MUX_CTL_TRACE9_TRACE10_TRACE11_TRACE12 #define TRACE11_BYTE_IN_SW_MUX 1 #define TRACE12_SW_MUX_REG SW_MUX_CTL_TRACE9_TRACE10_TRACE11_TRACE12 #define TRACE12_BYTE_IN_SW_MUX 0 #define TRACE13_SW_MUX_REG SW_MUX_CTL_TRACE13_TRACE14_TRACE15_TRACE16 #define TRACE13_BYTE_IN_SW_MUX 3 #define TRACE14_SW_MUX_REG SW_MUX_CTL_TRACE13_TRACE14_TRACE15_TRACE16 #define TRACE14_BYTE_IN_SW_MUX 2 #define TRACE15_SW_MUX_REG SW_MUX_CTL_TRACE13_TRACE14_TRACE15_TRACE16 #define TRACE15_BYTE_IN_SW_MUX 1 #define TRACE16_SW_MUX_REG SW_MUX_CTL_TRACE13_TRACE14_TRACE15_TRACE16 #define TRACE16_BYTE_IN_SW_MUX 0 #define TRACE17_SW_MUX_REG SW_MUX_CTL_TRACE17_TRACE18_TRACE19_TRACE20 #define TRACE17_BYTE_IN_SW_MUX 3 #define TRACE18_SW_MUX_REG SW_MUX_CTL_TRACE17_TRACE18_TRACE19_TRACE20 #define TRACE18_BYTE_IN_SW_MUX 2 #define TRACE19_SW_MUX_REG SW_MUX_CTL_TRACE17_TRACE18_TRACE19_TRACE20 #define TRACE19_BYTE_IN_SW_MUX 1 #define TRACE20_SW_MUX_REG SW_MUX_CTL_TRACE17_TRACE18_TRACE19_TRACE20 #define TRACE20_BYTE_IN_SW_MUX 0 #define TRACE21_SW_MUX_REG SW_MUX_CTL_TRACE21_TRACE22_TRACE23_TRACE24 #define TRACE21_BYTE_IN_SW_MUX 3 #define TRACE22_SW_MUX_REG SW_MUX_CTL_TRACE21_TRACE22_TRACE23_TRACE24 #define TRACE22_BYTE_IN_SW_MUX 2 #define TRACE23_SW_MUX_REG SW_MUX_CTL_TRACE21_TRACE22_TRACE23_TRACE24 #define TRACE23_BYTE_IN_SW_MUX 1 #define TRACE24_SW_MUX_REG SW_MUX_CTL_TRACE21_TRACE22_TRACE23_TRACE24 #define TRACE24_BYTE_IN_SW_MUX 0 #define TRACE25_SW_MUX_REG SW_MUX_CTL_TRACE25_TRACE26_TRACE27_TRACE28 #define TRACE25_BYTE_IN_SW_MUX 3 #define TRACE26_SW_MUX_REG SW_MUX_CTL_TRACE25_TRACE26_TRACE27_TRACE28 #define TRACE26_BYTE_IN_SW_MUX 2 #define TRACE27_SW_MUX_REG SW_MUX_CTL_TRACE25_TRACE26_TRACE27_TRACE28 #define TRACE27_BYTE_IN_SW_MUX 1 #define TRACE28_SW_MUX_REG SW_MUX_CTL_TRACE25_TRACE26_TRACE27_TRACE28 #define TRACE28_BYTE_IN_SW_MUX 0 #define TRACE29_SW_MUX_REG SW_MUX_CTL_TRACE29_TRACE30_TRACE31_DBGACK #define TRACE29_BYTE_IN_SW_MUX 3 #define TRACE30_SW_MUX_REG SW_MUX_CTL_TRACE29_TRACE30_TRACE31_DBGACK #define TRACE30_BYTE_IN_SW_MUX 2 #define TRACE31_SW_MUX_REG SW_MUX_CTL_TRACE29_TRACE30_TRACE31_DBGACK #define TRACE31_BYTE_IN_SW_MUX 1 #define DBGACK_SW_MUX_REG SW_MUX_CTL_TRACE29_TRACE30_TRACE31_DBGACK #define DBGACK_BYTE_IN_SW_MUX 0 #define TRCLK_SW_MUX_REG SW_MUX_CTL_TRCLK_SRST_DBGRQ_EXTRIG #define TRCLK_BYTE_IN_SW_MUX 3 #define SRST_SW_MUX_REG SW_MUX_CTL_TRCLK_SRST_DBGRQ_EXTRIG #define SRST_BYTE_IN_SW_MUX 2 #define DBGRQ_SW_MUX_REG SW_MUX_CTL_TRCLK_SRST_DBGRQ_EXTRIG #define DBGRQ_BYTE_IN_SW_MUX 1 #define EXTRIG_SW_MUX_REG SW_MUX_CTL_TRCLK_SRST_DBGRQ_EXTRIG #define EXTRIG_BYTE_IN_SW_MUX 0 #define MDO0_SW_MUX_REG SW_MUX_CTL_MDO0_MDO1_MDO2_MDO3 #define MDO0_BYTE_IN_SW_MUX 3 #define MDO1_SW_MUX_REG SW_MUX_CTL_MDO0_MDO1_MDO2_MDO3 #define MDO1_BYTE_IN_SW_MUX 2 #define MDO2_SW_MUX_REG SW_MUX_CTL_MDO0_MDO1_MDO2_MDO3 #define MDO2_BYTE_IN_SW_MUX 1 #define MDO3_SW_MUX_REG SW_MUX_CTL_MDO0_MDO1_MDO2_MDO3 #define MDO3_BYTE_IN_SW_MUX 0 #define MDO4_SW_MUX_REG SW_MUX_CTL_MDO4_MDO5_MDO6_MDO7 #define MDO4_BYTE_IN_SW_MUX 3 #define MDO5_SW_MUX_REG SW_MUX_CTL_MDO4_MDO5_MDO6_MDO7 #define MDO5_BYTE_IN_SW_MUX 2 #define MDO6_SW_MUX_REG SW_MUX_CTL_MDO4_MDO5_MDO6_MDO7 #define MDO6_BYTE_IN_SW_MUX 1 #define MDO7_SW_MUX_REG SW_MUX_CTL_MDO4_MDO5_MDO6_MDO7 #define MDO7_BYTE_IN_SW_MUX 0 #define MDO8_SW_MUX_REG SW_MUX_CTL_MDO8_MDO9_MDO10_MDO11 #define MDO8_BYTE_IN_SW_MUX 3 #define MDO9_SW_MUX_REG SW_MUX_CTL_MDO8_MDO9_MDO10_MDO11 #define MDO9_BYTE_IN_SW_MUX 2 #define MDO10_SW_MUX_REG SW_MUX_CTL_MDO8_MDO9_MDO10_MDO11 #define MDO10_BYTE_IN_SW_MUX 1 #define MDO11_SW_MUX_REG SW_MUX_CTL_MDO8_MDO9_MDO10_MDO11 #define MDO11_BYTE_IN_SW_MUX 0 #define MDO12_SW_MUX_REG SW_MUX_CTL_MDO12_MDO13_MDO14_MDO15 #define MDO12_BYTE_IN_SW_MUX 3 #define MDO13_SW_MUX_REG SW_MUX_CTL_MDO12_MDO13_MDO14_MDO15 #define MDO13_BYTE_IN_SW_MUX 2 #define MDO14_SW_MUX_REG SW_MUX_CTL_MDO12_MDO13_MDO14_MDO15 #define MDO14_BYTE_IN_SW_MUX 1 #define MDO15_SW_MUX_REG SW_MUX_CTL_MDO12_MDO13_MDO14_MDO15 #define MDO15_BYTE_IN_SW_MUX 0 #define MDO16_SW_MUX_REG SW_MUX_CTL_MDO16_MDO17_MDO18_MDO19 #define MDO16_BYTE_IN_SW_MUX 3 #define MDO17_SW_MUX_REG SW_MUX_CTL_MDO16_MDO17_MDO18_MDO19 #define MDO17_BYTE_IN_SW_MUX 2 #define MDO18_SW_MUX_REG SW_MUX_CTL_MDO16_MDO17_MDO18_MDO19 #define MDO18_BYTE_IN_SW_MUX 1 #define MDO19_SW_MUX_REG SW_MUX_CTL_MDO16_MDO17_MDO18_MDO19 #define MDO19_BYTE_IN_SW_MUX 0 #define MDO20_SW_MUX_REG SW_MUX_CTL_MDO20_MDO21_MDO22_MDO23 #define MDO20_BYTE_IN_SW_MUX 3 #define MDO21_SW_MUX_REG SW_MUX_CTL_MDO20_MDO21_MDO22_MDO23 #define MDO21_BYTE_IN_SW_MUX 2 #define MDO22_SW_MUX_REG SW_MUX_CTL_MDO20_MDO21_MDO22_MDO23 #define MDO22_BYTE_IN_SW_MUX 1 #define MDO23_SW_MUX_REG SW_MUX_CTL_MDO20_MDO21_MDO22_MDO23 #define MDO23_BYTE_IN_SW_MUX 0 #define MDO24_SW_MUX_REG SW_MUX_CTL_MDO24_MDO25_MDO26_MDO27 #define MDO24_BYTE_IN_SW_MUX 3 #define MDO25_SW_MUX_REG SW_MUX_CTL_MDO24_MDO25_MDO26_MDO27 #define MDO25_BYTE_IN_SW_MUX 2 #define MDO26_SW_MUX_REG SW_MUX_CTL_MDO24_MDO25_MDO26_MDO27 #define MDO26_BYTE_IN_SW_MUX 1 #define MDO27_SW_MUX_REG SW_MUX_CTL_MDO24_MDO25_MDO26_MDO27 #define MDO27_BYTE_IN_SW_MUX 0 #define MDO28_SW_MUX_REG SW_MUX_CTL_MDO28_MDO29_MDO30_MDO31 #define MDO28_BYTE_IN_SW_MUX 3 #define MDO29_SW_MUX_REG SW_MUX_CTL_MDO28_MDO29_MDO30_MDO31 #define MDO29_BYTE_IN_SW_MUX 2 #define MDO30_SW_MUX_REG SW_MUX_CTL_MDO28_MDO29_MDO30_MDO31 #define MDO30_BYTE_IN_SW_MUX 1 #define MDO31_SW_MUX_REG SW_MUX_CTL_MDO28_MDO29_MDO30_MDO31 #define MDO31_BYTE_IN_SW_MUX 0 #define MSE1_SW_MUX_REG SW_MUX_CTL_MSE1_EVTO_MRDY_MCKO #define MSE1_BYTE_IN_SW_MUX 3 #define EVTO_SW_MUX_REG SW_MUX_CTL_MSE1_EVTO_MRDY_MCKO #define EVTO_BYTE_IN_SW_MUX 2 #define MRDY_SW_MUX_REG SW_MUX_CTL_MSE1_EVTO_MRDY_MCKO #define MRDY_BYTE_IN_SW_MUX 1 #define MCKO_SW_MUX_REG SW_MUX_CTL_MSE1_EVTO_MRDY_MCKO #define MCKO_BYTE_IN_SW_MUX 0 #define MSE0_SW_MUX_REG SW_MUX_CTL_MSE0__X__X__X #define MSE0_BYTE_IN_SW_MUX 3 // SW_PAD_CTL defines : // ###################### #define A0_MA0_SW_PAD_REG SW_PAD_CTL_A0_MA0_A1_MA1_A2_MA2 #define A0_MA0_BYTE_IN_SW_PAD 2 #define A1_MA1_SW_PAD_REG SW_PAD_CTL_A0_MA0_A1_MA1_A2_MA2 #define A1_MA1_BYTE_IN_SW_PAD 1 #define A2_MA2_SW_PAD_REG SW_PAD_CTL_A0_MA0_A1_MA1_A2_MA2 #define A2_MA2_BYTE_IN_SW_PAD 0 #define A3_MA3_SW_PAD_REG SW_PAD_CTL_A3_MA3_A4_MA4_A5_MA5 #define A3_MA3_BYTE_IN_SW_PAD 2 #define A4_MA4_SW_PAD_REG SW_PAD_CTL_A3_MA3_A4_MA4_A5_MA5 #define A4_MA4_BYTE_IN_SW_PAD 1 #define A5_MA5_SW_PAD_REG SW_PAD_CTL_A3_MA3_A4_MA4_A5_MA5 #define A5_MA5_BYTE_IN_SW_PAD 0 #define A6_MA6_SW_PAD_REG SW_PAD_CTL_A6_MA6_A7_MA7_A8_MA8 #define A6_MA6_BYTE_IN_SW_PAD 2 #define A7_MA7_SW_PAD_REG SW_PAD_CTL_A6_MA6_A7_MA7_A8_MA8 #define A7_MA7_BYTE_IN_SW_PAD 1 #define A8_MA8_SW_PAD_REG SW_PAD_CTL_A6_MA6_A7_MA7_A8_MA8 #define A8_MA8_BYTE_IN_SW_PAD 0 #define A9_MA9_SW_PAD_REG SW_PAD_CTL_A9_MA9_A10_MA10 #define A9_MA9_BYTE_IN_SW_PAD 2 #define A10_SW_PAD_REG SW_PAD_CTL_A9_MA9_A10_MA10 #define A10_BYTE_IN_SW_PAD 1 #define MA10_SW_PAD_REG SW_PAD_CTL_A9_MA9_A10_MA10 #define MA10_BYTE_IN_SW_PAD 0 #define A11_MA11_SW_PAD_REG SW_PAD_CTL_A11_MA11_A12_MA12_A13_MA13 #define A11_MA11_BYTE_IN_SW_PAD 2 #define A12_MA12_SW_PAD_REG SW_PAD_CTL_A11_MA11_A12_MA12_A13_MA13 #define A12_MA12_BYTE_IN_SW_PAD 1 #define A13_MA13_SW_PAD_REG SW_PAD_CTL_A11_MA11_A12_MA12_A13_MA13 #define A13_MA13_BYTE_IN_SW_PAD 0 #define A14_SW_PAD_REG SW_PAD_CTL_A14_A15_A16 #define A14_BYTE_IN_SW_PAD 2 #define A15_SW_PAD_REG SW_PAD_CTL_A14_A15_A16 #define A15_BYTE_IN_SW_PAD 1 #define A16_SW_PAD_REG SW_PAD_CTL_A14_A15_A16 #define A16_BYTE_IN_SW_PAD 0 #define A17_SW_PAD_REG SW_PAD_CTL_A17_A18_A19 #define A17_BYTE_IN_SW_PAD 2 #define A18_SW_PAD_REG SW_PAD_CTL_A17_A18_A19 #define A18_BYTE_IN_SW_PAD 1 #define A19_SW_PAD_REG SW_PAD_CTL_A17_A18_A19 #define A19_BYTE_IN_SW_PAD 0 #define A20_SW_PAD_REG SW_PAD_CTL_A20_A21_A22 #define A20_BYTE_IN_SW_PAD 2 #define A21_SW_PAD_REG SW_PAD_CTL_A20_A21_A22 #define A21_BYTE_IN_SW_PAD 1 #define A22_SW_PAD_REG SW_PAD_CTL_A20_A21_A22 #define A22_BYTE_IN_SW_PAD 0 #define A23_SW_PAD_REG SW_PAD_CTL_A23_A24_A25 #define A23_BYTE_IN_SW_PAD 2 #define A24_SW_PAD_REG SW_PAD_CTL_A23_A24_A25 #define A24_BYTE_IN_SW_PAD 1 #define A25_SW_PAD_REG SW_PAD_CTL_A23_A24_A25 #define A25_BYTE_IN_SW_PAD 0 #define SD0_SW_PAD_REG SW_PAD_CTL_SD0_SD1_SD2 #define SD0_BYTE_IN_SW_PAD 2 #define SD1_SW_PAD_REG SW_PAD_CTL_SD0_SD1_SD2 #define SD1_BYTE_IN_SW_PAD 1 #define SD2_SW_PAD_REG SW_PAD_CTL_SD0_SD1_SD2 #define SD2_BYTE_IN_SW_PAD 0 #define SD3_SW_PAD_REG SW_PAD_CTL_SD3_SD4_SD5 #define SD3_BYTE_IN_SW_PAD 2 #define SD4_SW_PAD_REG SW_PAD_CTL_SD3_SD4_SD5 #define SD4_BYTE_IN_SW_PAD 1 #define SD5_SW_PAD_REG SW_PAD_CTL_SD3_SD4_SD5 #define SD5_BYTE_IN_SW_PAD 0 #define SD6_SW_PAD_REG SW_PAD_CTL_SD6_SD7_SD8 #define SD6_BYTE_IN_SW_PAD 2 #define SD7_SW_PAD_REG SW_PAD_CTL_SD6_SD7_SD8 #define SD7_BYTE_IN_SW_PAD 1 #define SD8_SW_PAD_REG SW_PAD_CTL_SD6_SD7_SD8 #define SD8_BYTE_IN_SW_PAD 0 #define SD9_SW_PAD_REG SW_PAD_CTL_SD9_SD10_SD11 #define SD9_BYTE_IN_SW_PAD 2 #define SD10_SW_PAD_REG SW_PAD_CTL_SD9_SD10_SD11 #define SD10_BYTE_IN_SW_PAD 1 #define SD11_SW_PAD_REG SW_PAD_CTL_SD9_SD10_SD11 #define SD11_BYTE_IN_SW_PAD 0 #define SD12_SW_PAD_REG SW_PAD_CTL_SD12_SD13_SD14 #define SD12_BYTE_IN_SW_PAD 2 #define SD13_SW_PAD_REG SW_PAD_CTL_SD12_SD13_SD14 #define SD13_BYTE_IN_SW_PAD 1 #define SD14_SW_PAD_REG SW_PAD_CTL_SD12_SD13_SD14 #define SD14_BYTE_IN_SW_PAD 0 #define SD15_SW_PAD_REG SW_PAD_CTL_SD15_SD16_SD17 #define SD15_BYTE_IN_SW_PAD 2 #define SD16_SW_PAD_REG SW_PAD_CTL_SD15_SD16_SD17 #define SD16_BYTE_IN_SW_PAD 1 #define SD17_SW_PAD_REG SW_PAD_CTL_SD15_SD16_SD17 #define SD17_BYTE_IN_SW_PAD 0 #define SD18_SW_PAD_REG SW_PAD_CTL_SD18_SD19_SD20 #define SD18_BYTE_IN_SW_PAD 2 #define SD19_SW_PAD_REG SW_PAD_CTL_SD18_SD19_SD20 #define SD19_BYTE_IN_SW_PAD 1 #define SD20_SW_PAD_REG SW_PAD_CTL_SD18_SD19_SD20 #define SD20_BYTE_IN_SW_PAD 0 #define SD21_SW_PAD_REG SW_PAD_CTL_SD21_SD22_SD23 #define SD21_BYTE_IN_SW_PAD 2 #define SD22_SW_PAD_REG SW_PAD_CTL_SD21_SD22_SD23 #define SD22_BYTE_IN_SW_PAD 1 #define SD23_SW_PAD_REG SW_PAD_CTL_SD21_SD22_SD23 #define SD23_BYTE_IN_SW_PAD 0 #define SD24_SW_PAD_REG SW_PAD_CTL_SD24_SD25_SD26 #define SD24_BYTE_IN_SW_PAD 2 #define SD25_SW_PAD_REG SW_PAD_CTL_SD24_SD25_SD26 #define SD25_BYTE_IN_SW_PAD 1 #define SD26_SW_PAD_REG SW_PAD_CTL_SD24_SD25_SD26 #define SD26_BYTE_IN_SW_PAD 0 #define SD27_SW_PAD_REG SW_PAD_CTL_SD27_SD28_SD29 #define SD27_BYTE_IN_SW_PAD 2 #define SD28_SW_PAD_REG SW_PAD_CTL_SD27_SD28_SD29 #define SD28_BYTE_IN_SW_PAD 1 #define SD29_SW_PAD_REG SW_PAD_CTL_SD27_SD28_SD29 #define SD29_BYTE_IN_SW_PAD 0 #define SD30_SW_PAD_REG SW_PAD_CTL_SD30_SD31_SDQS0 #define SD30_BYTE_IN_SW_PAD 2 #define SD31_SW_PAD_REG SW_PAD_CTL_SD30_SD31_SDQS0 #define SD31_BYTE_IN_SW_PAD 1 #define SDQS0_SW_PAD_REG SW_PAD_CTL_SD30_SD31_SDQS0 #define SDQS0_BYTE_IN_SW_PAD 0 #define SDQS1_SW_PAD_REG SW_PAD_CTL_SDQS1_MGRNT_MRQST #define SDQS1_BYTE_IN_SW_PAD 2 #define MGRNT_SW_PAD_REG SW_PAD_CTL_SDQS1_MGRNT_MRQST #define MGRNT_BYTE_IN_SW_PAD 1 #define MRQST_SW_PAD_REG SW_PAD_CTL_SDQS1_MGRNT_MRQST #define MRQST_BYTE_IN_SW_PAD 0 #define DQM0_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2 #define DQM0_BYTE_IN_SW_PAD 2 #define DQM1_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2 #define DQM1_BYTE_IN_SW_PAD 1 #define DQM2_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2 #define DQM2_BYTE_IN_SW_PAD 0 #define DQM3_SW_PAD_REG SW_PAD_CTL_DQM3_OE_B_CS0_B #define DQM3_BYTE_IN_SW_PAD 2 #define OE_B_SW_PAD_REG SW_PAD_CTL_DQM3_OE_B_CS0_B #define OE_B_BYTE_IN_SW_PAD 1 #define CS0_B_SW_PAD_REG SW_PAD_CTL_DQM3_OE_B_CS0_B #define CS0_B_BYTE_IN_SW_PAD 0 #define CS1_B_SW_PAD_REG SW_PAD_CTL_CS1_B_CS2_B_CS3_B #define CS1_B_BYTE_IN_SW_PAD 2 #define CS2_B_SW_PAD_REG SW_PAD_CTL_CS1_B_CS2_B_CS3_B #define CS2_B_BYTE_IN_SW_PAD 1 #define CS3_B_SW_PAD_REG SW_PAD_CTL_CS1_B_CS2_B_CS3_B #define CS3_B_BYTE_IN_SW_PAD 0 #define CS4_B_SW_PAD_REG SW_PAD_CTL_CS4_B_SDBA0_SDBA1 #define CS4_B_BYTE_IN_SW_PAD 2 #define SDBA0_SW_PAD_REG SW_PAD_CTL_CS4_B_SDBA0_SDBA1 #define SDBA0_BYTE_IN_SW_PAD 1 #define SDBA1_SW_PAD_REG SW_PAD_CTL_CS4_B_SDBA0_SDBA1 #define SDBA1_BYTE_IN_SW_PAD 0 #define ECB_B_SW_PAD_REG SW_PAD_CTL_ECB_B_LBA_B_BCLK #define ECB_B_BYTE_IN_SW_PAD 2 #define LBA_B_SW_PAD_REG SW_PAD_CTL_ECB_B_LBA_B_BCLK #define LBA_B_BYTE_IN_SW_PAD 1 #define BCLK_SW_PAD_REG SW_PAD_CTL_ECB_B_LBA_B_BCLK #define BCLK_BYTE_IN_SW_PAD 0 #define RW_B_SW_PAD_REG SW_PAD_CTL_RW_B_EB0_B_EB3_B #define RW_B_BYTE_IN_SW_PAD 2 #define EB0_B_SW_PAD_REG SW_PAD_CTL_RW_B_EB0_B_EB3_B #define EB0_B_BYTE_IN_SW_PAD 1 #define EB3_B_SW_PAD_REG SW_PAD_CTL_RW_B_EB0_B_EB3_B #define EB3_B_BYTE_IN_SW_PAD 0 #define RAS_SW_PAD_REG SW_PAD_CTL_RAS_CAS_SDWE #define RAS_BYTE_IN_SW_PAD 2 #define CAS_SW_PAD_REG SW_PAD_CTL_RAS_CAS_SDWE #define CAS_BYTE_IN_SW_PAD 1 #define SDWE_SW_PAD_REG SW_PAD_CTL_RAS_CAS_SDWE #define SDWE_BYTE_IN_SW_PAD 0 #define SDCKE0_SW_PAD_REG SW_PAD_CTL_SDCKE0_SDCKE1_SDCLK #define SDCKE0_BYTE_IN_SW_PAD 2 #define SDCKE1_SW_PAD_REG SW_PAD_CTL_SDCKE0_SDCKE1_SDCLK #define SDCKE1_BYTE_IN_SW_PAD 1 #define SDCLK_SW_PAD_REG SW_PAD_CTL_SDCKE0_SDCKE1_SDCLK #define SDCLK_BYTE_IN_SW_PAD 0 #define SDCLK_B_SW_PAD_REG SW_PAD_CTL_SDCLK_B_CLE_WP #define SDCLK_B_BYTE_IN_SW_PAD 2 #define CLE_SW_PAD_REG SW_PAD_CTL_SDCLK_B_CLE_WP #define CLE_BYTE_IN_SW_PAD 1 #define WP_SW_PAD_REG SW_PAD_CTL_SDCLK_B_CLE_WP #define WP_BYTE_IN_SW_PAD 0 #define ALE_SW_PAD_REG SW_PAD_CTL_ALE_RE_WE #define ALE_BYTE_IN_SW_PAD 2 #define RE_SW_PAD_REG SW_PAD_CTL_ALE_RE_WE #define RE_BYTE_IN_SW_PAD 1 #define WE_SW_PAD_REG SW_PAD_CTL_ALE_RE_WE #define WE_BYTE_IN_SW_PAD 0 #define R_B_SW_PAD_REG SW_PAD_CTL_R_B_D0_D1 #define R_B_BYTE_IN_SW_PAD 2 #define D0_SW_PAD_REG SW_PAD_CTL_R_B_D0_D1 #define D0_BYTE_IN_SW_PAD 1 #define D1_SW_PAD_REG SW_PAD_CTL_R_B_D0_D1 #define D1_BYTE_IN_SW_PAD 0 #define D2_SW_PAD_REG SW_PAD_CTL_D2_D3_D4 #define D2_BYTE_IN_SW_PAD 2 #define D3_SW_PAD_REG SW_PAD_CTL_D2_D3_D4 #define D3_BYTE_IN_SW_PAD 1 #define D4_SW_PAD_REG SW_PAD_CTL_D2_D3_D4 #define D4_BYTE_IN_SW_PAD 0 #define D5_SW_PAD_REG SW_PAD_CTL_D5_D6_D7 #define D5_BYTE_IN_SW_PAD 2 #define D6_SW_PAD_REG SW_PAD_CTL_D5_D6_D7 #define D6_BYTE_IN_SW_PAD 1 #define D7_SW_PAD_REG SW_PAD_CTL_D5_D6_D7 #define D7_BYTE_IN_SW_PAD 0 #define D8_SW_PAD_REG SW_PAD_CTL_D8_D9_D10 #define D8_BYTE_IN_SW_PAD 2 #define D9_SW_PAD_REG SW_PAD_CTL_D8_D9_D10 #define D9_BYTE_IN_SW_PAD 1 #define D10_SW_PAD_REG SW_PAD_CTL_D8_D9_D10 #define D10_BYTE_IN_SW_PAD 0 #define D11_SW_PAD_REG SW_PAD_CTL_D11_D12_D13 #define D11_BYTE_IN_SW_PAD 2 #define D12_SW_PAD_REG SW_PAD_CTL_D11_D12_D13 #define D12_BYTE_IN_SW_PAD 1 #define D13_SW_PAD_REG SW_PAD_CTL_D11_D12_D13 #define D13_BYTE_IN_SW_PAD 0 #define D14_SW_PAD_REG SW_PAD_CTL_D14_D15_CKIL #define D14_BYTE_IN_SW_PAD 2 #define D15_SW_PAD_REG SW_PAD_CTL_D14_D15_CKIL #define D15_BYTE_IN_SW_PAD 1 #define CKIL_SW_PAD_REG SW_PAD_CTL_D14_D15_CKIL #define CKIL_BYTE_IN_SW_PAD 0 #define WB_REF_CLK_IN_SW_PAD_REG SW_PAD_CTL_WB_REF_CLK_IN_MB_REF_CLK_IN_CKIH_REF_CLK_IN #define WB_REF_CLK_IN_BYTE_IN_SW_PAD 2 #define MB_REF_CLK_IN_SW_PAD_REG SW_PAD_CTL_WB_REF_CLK_IN_MB_REF_CLK_IN_CKIH_REF_CLK_IN #define MB_REF_CLK_IN_BYTE_IN_SW_PAD 1 #define CKIH_REF_CLK_IN_SW_PAD_REG SW_PAD_CTL_WB_REF_CLK_IN_MB_REF_CLK_IN_CKIH_REF_CLK_IN #define CKIH_REF_CLK_IN_BYTE_IN_SW_PAD 0 #define CKO1_SW_PAD_REG SW_PAD_CTL_CKO1_CKO2_RESET_IN_B #define CKO1_BYTE_IN_SW_PAD 2 #define CKO2_SW_PAD_REG SW_PAD_CTL_CKO1_CKO2_RESET_IN_B #define CKO2_BYTE_IN_SW_PAD 1 #define RESET_IN_B_SW_PAD_REG SW_PAD_CTL_CKO1_CKO2_RESET_IN_B #define RESET_IN_B_BYTE_IN_SW_PAD 0 #define RESET_POR_IN_B_SW_PAD_REG SW_PAD_CTL_RESET_POR_IN_B_TEST_MODE_BOOT_MODE0 #define RESET_POR_IN_B_BYTE_IN_SW_PAD 2 #define TEST_MODE_SW_PAD_REG SW_PAD_CTL_RESET_POR_IN_B_TEST_MODE_BOOT_MODE0 #define TEST_MODE_BYTE_IN_SW_PAD 1 #define BOOT_MODE0_SW_PAD_REG SW_PAD_CTL_RESET_POR_IN_B_TEST_MODE_BOOT_MODE0 #define BOOT_MODE0_BYTE_IN_SW_PAD 0 #define BOOT_MODE1_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_REF_EN_B_PM_INT #define BOOT_MODE1_BYTE_IN_SW_PAD 2 #define REF_EN_B_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_REF_EN_B_PM_INT #define REF_EN_B_BYTE_IN_SW_PAD 1 #define PM_INT_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_REF_EN_B_PM_INT #define PM_INT_BYTE_IN_SW_PAD 0 #define POWER_FAIL_SW_PAD_REG SW_PAD_CTL_POWER_FAIL_USER_OFF_WDOG_B #define POWER_FAIL_BYTE_IN_SW_PAD 2 #define USER_OFF_SW_PAD_REG SW_PAD_CTL_POWER_FAIL_USER_OFF_WDOG_B #define USER_OFF_BYTE_IN_SW_PAD 1 #define WDOG_B_SW_PAD_REG SW_PAD_CTL_POWER_FAIL_USER_OFF_WDOG_B #define WDOG_B_BYTE_IN_SW_PAD 0 #define TRSTB_SW_PAD_REG SW_PAD_CTL_TRSTB_TDO_TDI #define TRSTB_BYTE_IN_SW_PAD 2 #define TDO_SW_PAD_REG SW_PAD_CTL_TRSTB_TDO_TDI #define TDO_BYTE_IN_SW_PAD 1 #define TDI_SW_PAD_REG SW_PAD_CTL_TRSTB_TDO_TDI #define TDI_BYTE_IN_SW_PAD 0 #define RTCK_SW_PAD_REG SW_PAD_CTL_RTCK_TCK_TMS #define RTCK_BYTE_IN_SW_PAD 2 #define TCK_SW_PAD_REG SW_PAD_CTL_RTCK_TCK_TMS #define TCK_BYTE_IN_SW_PAD 1 #define TMS_SW_PAD_REG SW_PAD_CTL_RTCK_TCK_TMS #define TMS_BYTE_IN_SW_PAD 0 #define SJC_MOD_SW_PAD_REG SW_PAD_CTL_SJC_MOD_DE_B_EVTI_B #define SJC_MOD_BYTE_IN_SW_PAD 2 #define DE_B_SW_PAD_REG SW_PAD_CTL_SJC_MOD_DE_B_EVTI_B #define DE_B_BYTE_IN_SW_PAD 1 #define EVTI_B_SW_PAD_REG SW_PAD_CTL_SJC_MOD_DE_B_EVTI_B #define EVTI_B_BYTE_IN_SW_PAD 0 #define SIM1_CLK0_SW_PAD_REG SW_PAD_CTL_SIM1_CLK0_SIM1_RST0_SIM1_DATA0_RX_TX #define SIM1_CLK0_BYTE_IN_SW_PAD 2 #define SIM1_RST0_SW_PAD_REG SW_PAD_CTL_SIM1_CLK0_SIM1_RST0_SIM1_DATA0_RX_TX #define SIM1_RST0_BYTE_IN_SW_PAD 1 #define SIM1_DATA0_RX_TX_SW_PAD_REG SW_PAD_CTL_SIM1_CLK0_SIM1_RST0_SIM1_DATA0_RX_TX #define SIM1_DATA0_RX_TX_BYTE_IN_SW_PAD 0 #define SIM1_SVEN0_SW_PAD_REG SW_PAD_CTL_SIM1_SVEN0_SIM1_SIMPD0_USB1_VMOUT #define SIM1_SVEN0_BYTE_IN_SW_PAD 2 #define SIM1_SIMPD0_SW_PAD_REG SW_PAD_CTL_SIM1_SVEN0_SIM1_SIMPD0_USB1_VMOUT #define SIM1_SIMPD0_BYTE_IN_SW_PAD 1 #define USB1_VMOUT_SW_PAD_REG SW_PAD_CTL_SIM1_SVEN0_SIM1_SIMPD0_USB1_VMOUT #define USB1_VMOUT_BYTE_IN_SW_PAD 0 #define USB1_TXENB_SW_PAD_REG SW_PAD_CTL_USB1_TXENB_USB1_VPIN_USB1_VPOUT #define USB1_TXENB_BYTE_IN_SW_PAD 2 #define USB1_VPIN_SW_PAD_REG SW_PAD_CTL_USB1_TXENB_USB1_VPIN_USB1_VPOUT #define USB1_VPIN_BYTE_IN_SW_PAD 1 #define USB1_VPOUT_SW_PAD_REG SW_PAD_CTL_USB1_TXENB_USB1_VPIN_USB1_VPOUT #define USB1_VPOUT_BYTE_IN_SW_PAD 0 #define USB1_VMIN_SW_PAD_REG SW_PAD_CTL_USB1_VMIN_USB1_XRXD_USB_VMOUT #define USB1_VMIN_BYTE_IN_SW_PAD 2 #define USB1_XRXD_SW_PAD_REG SW_PAD_CTL_USB1_VMIN_USB1_XRXD_USB_VMOUT #define USB1_XRXD_BYTE_IN_SW_PAD 1 #define USB_VMOUT_SW_PAD_REG SW_PAD_CTL_USB1_VMIN_USB1_XRXD_USB_VMOUT #define USB_VMOUT_BYTE_IN_SW_PAD 0 #define USB_TXENB_SW_PAD_REG SW_PAD_CTL_USB_TXENB_USB_VPIN_USB_VPOUT #define USB_TXENB_BYTE_IN_SW_PAD 2 #define USB_VPIN_SW_PAD_REG SW_PAD_CTL_USB_TXENB_USB_VPIN_USB_VPOUT #define USB_VPIN_BYTE_IN_SW_PAD 1 #define USB_VPOUT_SW_PAD_REG SW_PAD_CTL_USB_TXENB_USB_VPIN_USB_VPOUT #define USB_VPOUT_BYTE_IN_SW_PAD 0 #define USB_VMIN_SW_PAD_REG SW_PAD_CTL_USB_VMIN_USB_XRXD_BBP_RX_CLK #define USB_VMIN_BYTE_IN_SW_PAD 2 #define USB_XRXD_SW_PAD_REG SW_PAD_CTL_USB_VMIN_USB_XRXD_BBP_RX_CLK #define USB_XRXD_BYTE_IN_SW_PAD 1 #define BBP_RX_CLK_SW_PAD_REG SW_PAD_CTL_USB_VMIN_USB_XRXD_BBP_RX_CLK #define BBP_RX_CLK_BYTE_IN_SW_PAD 0 #define BBP_TX_CLK_SW_PAD_REG SW_PAD_CTL_BBP_TX_CLK_BBP_RX_FRAME_BBP_TX_FRAME #define BBP_TX_CLK_BYTE_IN_SW_PAD 2 #define BBP_RX_FRAME_SW_PAD_REG SW_PAD_CTL_BBP_TX_CLK_BBP_RX_FRAME_BBP_TX_FRAME #define BBP_RX_FRAME_BYTE_IN_SW_PAD 1 #define BBP_TX_FRAME_SW_PAD_REG SW_PAD_CTL_BBP_TX_CLK_BBP_RX_FRAME_BBP_TX_FRAME #define BBP_TX_FRAME_BYTE_IN_SW_PAD 0 #define BBP_RX_DATA_SW_PAD_REG SW_PAD_CTL_BBP_RX_DATA_BBP_TX_DATA_GPIO28 #define BBP_RX_DATA_BYTE_IN_SW_PAD 2 #define BBP_TX_DATA_SW_PAD_REG SW_PAD_CTL_BBP_RX_DATA_BBP_TX_DATA_GPIO28 #define BBP_TX_DATA_BYTE_IN_SW_PAD 1 #define GPIO28_SW_PAD_REG SW_PAD_CTL_BBP_RX_DATA_BBP_TX_DATA_GPIO28 #define GPIO28_BYTE_IN_SW_PAD 0 #define GPIO29_SW_PAD_REG SW_PAD_CTL_GPIO29_GPIO30_GPIO31 #define GPIO29_BYTE_IN_SW_PAD 2 #define GPIO30_SW_PAD_REG SW_PAD_CTL_GPIO29_GPIO30_GPIO31 #define GPIO30_BYTE_IN_SW_PAD 1 #define GPIO31_SW_PAD_REG SW_PAD_CTL_GPIO29_GPIO30_GPIO31 #define GPIO31_BYTE_IN_SW_PAD 0 #define GPIO32_SW_PAD_REG SW_PAD_CTL_GPIO32_GPIO33_GPIO34 #define GPIO32_BYTE_IN_SW_PAD 2 #define GPIO33_SW_PAD_REG SW_PAD_CTL_GPIO32_GPIO33_GPIO34 #define GPIO33_BYTE_IN_SW_PAD 1 #define GPIO34_SW_PAD_REG SW_PAD_CTL_GPIO32_GPIO33_GPIO34 #define GPIO34_BYTE_IN_SW_PAD 0 #define GPIO35_SW_PAD_REG SW_PAD_CTL_GPIO35_SDMA_EVNT0_SDMA_EVNT1 #define GPIO35_BYTE_IN_SW_PAD 2 #define SDMA_EVNT0_SW_PAD_REG SW_PAD_CTL_GPIO35_SDMA_EVNT0_SDMA_EVNT1 #define SDMA_EVNT0_BYTE_IN_SW_PAD 1 #define SDMA_EVNT1_SW_PAD_REG SW_PAD_CTL_GPIO35_SDMA_EVNT0_SDMA_EVNT1 #define SDMA_EVNT1_BYTE_IN_SW_PAD 0 #define WAMMO_TX_Q_CH_SW_PAD_REG SW_PAD_CTL_WAMMO_TX_Q_CH_WAMMO_TX_I_CH_WAMMO_RX_Q_CH #define WAMMO_TX_Q_CH_BYTE_IN_SW_PAD 2 #define WAMMO_TX_I_CH_SW_PAD_REG SW_PAD_CTL_WAMMO_TX_Q_CH_WAMMO_TX_I_CH_WAMMO_RX_Q_CH #define WAMMO_TX_I_CH_BYTE_IN_SW_PAD 1 #define WAMMO_RX_Q_CH_SW_PAD_REG SW_PAD_CTL_WAMMO_TX_Q_CH_WAMMO_TX_I_CH_WAMMO_RX_Q_CH #define WAMMO_RX_Q_CH_BYTE_IN_SW_PAD 0 #define WAMMO_RX_I_CH_SW_PAD_REG SW_PAD_CTL_WAMMO_RX_I_CH_WAMMO_TX_FRAME_WAMMO_RX_FRAME #define WAMMO_RX_I_CH_BYTE_IN_SW_PAD 2 #define WAMMO_TX_FRAME_SW_PAD_REG SW_PAD_CTL_WAMMO_RX_I_CH_WAMMO_TX_FRAME_WAMMO_RX_FRAME #define WAMMO_TX_FRAME_BYTE_IN_SW_PAD 1 #define WAMMO_RX_FRAME_SW_PAD_REG SW_PAD_CTL_WAMMO_RX_I_CH_WAMMO_TX_FRAME_WAMMO_RX_FRAME #define WAMMO_RX_FRAME_BYTE_IN_SW_PAD 0 #define WAMMO_DIV_RX_I_CH_SW_PAD_REG SW_PAD_CTL_WAMMO_DIV_RX_I_CH_WAMMO_DIV_RX_Q_CH_WAMMO_DIV_RX_FRAME #define WAMMO_DIV_RX_I_CH_BYTE_IN_SW_PAD 2 #define WAMMO_DIV_RX_Q_CH_SW_PAD_REG SW_PAD_CTL_WAMMO_DIV_RX_I_CH_WAMMO_DIV_RX_Q_CH_WAMMO_DIV_RX_FRAME #define WAMMO_DIV_RX_Q_CH_BYTE_IN_SW_PAD 1 #define WAMMO_DIV_RX_FRAME_SW_PAD_REG SW_PAD_CTL_WAMMO_DIV_RX_I_CH_WAMMO_DIV_RX_Q_CH_WAMMO_DIV_RX_FRAME #define WAMMO_DIV_RX_FRAME_BYTE_IN_SW_PAD 0 #define DSM1_STBY_SW_PAD_REG SW_PAD_CTL_DSM1_STBY_DSM1_RX_ON_DSM2_STBY #define DSM1_STBY_BYTE_IN_SW_PAD 2 #define DSM1_RX_ON_SW_PAD_REG SW_PAD_CTL_DSM1_STBY_DSM1_RX_ON_DSM2_STBY #define DSM1_RX_ON_BYTE_IN_SW_PAD 1 #define DSM2_STBY_SW_PAD_REG SW_PAD_CTL_DSM1_STBY_DSM1_RX_ON_DSM2_STBY #define DSM2_STBY_BYTE_IN_SW_PAD 0 #define DSM2_VCO_EN_SW_PAD_REG SW_PAD_CTL_DSM2_VCO_EN_L1T1OUT0_L1T1OUT1 #define DSM2_VCO_EN_BYTE_IN_SW_PAD 2 #define L1T1OUT0_SW_PAD_REG SW_PAD_CTL_DSM2_VCO_EN_L1T1OUT0_L1T1OUT1 #define L1T1OUT0_BYTE_IN_SW_PAD 1 #define L1T1OUT1_SW_PAD_REG SW_PAD_CTL_DSM2_VCO_EN_L1T1OUT0_L1T1OUT1 #define L1T1OUT1_BYTE_IN_SW_PAD 0 #define L1T1OUT2_SW_PAD_REG SW_PAD_CTL_L1T1OUT2_L1T1OUT3_L1T1OUT4 #define L1T1OUT2_BYTE_IN_SW_PAD 2 #define L1T1OUT3_SW_PAD_REG SW_PAD_CTL_L1T1OUT2_L1T1OUT3_L1T1OUT4 #define L1T1OUT3_BYTE_IN_SW_PAD 1 #define L1T1OUT4_SW_PAD_REG SW_PAD_CTL_L1T1OUT2_L1T1OUT3_L1T1OUT4 #define L1T1OUT4_BYTE_IN_SW_PAD 0 #define L1T1OUT5_SW_PAD_REG SW_PAD_CTL_L1T1OUT5_L1T2OUT0_L1T2OUT1 #define L1T1OUT5_BYTE_IN_SW_PAD 2 #define L1T2OUT0_SW_PAD_REG SW_PAD_CTL_L1T1OUT5_L1T2OUT0_L1T2OUT1 #define L1T2OUT0_BYTE_IN_SW_PAD 1 #define L1T2OUT1_SW_PAD_REG SW_PAD_CTL_L1T1OUT5_L1T2OUT0_L1T2OUT1 #define L1T2OUT1_BYTE_IN_SW_PAD 0 #define L1T2OUT2_SW_PAD_REG SW_PAD_CTL_L1T2OUT2_L1T2OUT3_MQSPI1_CK #define L1T2OUT2_BYTE_IN_SW_PAD 2 #define L1T2OUT3_SW_PAD_REG SW_PAD_CTL_L1T2OUT2_L1T2OUT3_MQSPI1_CK #define L1T2OUT3_BYTE_IN_SW_PAD 1 #define MQSPI1_CK_SW_PAD_REG SW_PAD_CTL_L1T2OUT2_L1T2OUT3_MQSPI1_CK #define MQSPI1_CK_BYTE_IN_SW_PAD 0 #define MQSPI1_DI_SW_PAD_REG SW_PAD_CTL_MQSPI1_DI_MQSPI1_DO_MQSPI1_CS0 #define MQSPI1_DI_BYTE_IN_SW_PAD 2 #define MQSPI1_DO_SW_PAD_REG SW_PAD_CTL_MQSPI1_DI_MQSPI1_DO_MQSPI1_CS0 #define MQSPI1_DO_BYTE_IN_SW_PAD 1 #define MQSPI1_CS0_SW_PAD_REG SW_PAD_CTL_MQSPI1_DI_MQSPI1_DO_MQSPI1_CS0 #define MQSPI1_CS0_BYTE_IN_SW_PAD 0 #define MQSPI1_CS1_SW_PAD_REG SW_PAD_CTL_MQSPI1_CS1_MQSPI1_CS2_MQSPI2_CK #define MQSPI1_CS1_BYTE_IN_SW_PAD 2 #define MQSPI1_CS2_SW_PAD_REG SW_PAD_CTL_MQSPI1_CS1_MQSPI1_CS2_MQSPI2_CK #define MQSPI1_CS2_BYTE_IN_SW_PAD 1 #define MQSPI2_CK_SW_PAD_REG SW_PAD_CTL_MQSPI1_CS1_MQSPI1_CS2_MQSPI2_CK #define MQSPI2_CK_BYTE_IN_SW_PAD 0 #define MQSPI2_DI_SW_PAD_REG SW_PAD_CTL_MQSPI2_DI_MQSPI2_DO_MQSPI2_CS0 #define MQSPI2_DI_BYTE_IN_SW_PAD 2 #define MQSPI2_DO_SW_PAD_REG SW_PAD_CTL_MQSPI2_DI_MQSPI2_DO_MQSPI2_CS0 #define MQSPI2_DO_BYTE_IN_SW_PAD 1 #define MQSPI2_CS0_SW_PAD_REG SW_PAD_CTL_MQSPI2_DI_MQSPI2_DO_MQSPI2_CS0 #define MQSPI2_CS0_BYTE_IN_SW_PAD 0 #define MQSPI2_CS1_SW_PAD_REG SW_PAD_CTL_MQSPI2_CS1_UART_TXD3_UART_RXD3 #define MQSPI2_CS1_BYTE_IN_SW_PAD 2 #define UART_TXD3_SW_PAD_REG SW_PAD_CTL_MQSPI2_CS1_UART_TXD3_UART_RXD3 #define UART_TXD3_BYTE_IN_SW_PAD 1 #define UART_RXD3_SW_PAD_REG SW_PAD_CTL_MQSPI2_CS1_UART_TXD3_UART_RXD3 #define UART_RXD3_BYTE_IN_SW_PAD 0 #define UART_RTS3_B_SW_PAD_REG SW_PAD_CTL_UART_RTS3_B_UART_CTS3_B_GPIO0 #define UART_RTS3_B_BYTE_IN_SW_PAD 2 #define UART_CTS3_B_SW_PAD_REG SW_PAD_CTL_UART_RTS3_B_UART_CTS3_B_GPIO0 #define UART_CTS3_B_BYTE_IN_SW_PAD 1 #define GPIO0_SW_PAD_REG SW_PAD_CTL_UART_RTS3_B_UART_CTS3_B_GPIO0 #define GPIO0_BYTE_IN_SW_PAD 0 #define GPIO1_SW_PAD_REG SW_PAD_CTL_GPIO1_GPIO2_GPIO3 #define GPIO1_BYTE_IN_SW_PAD 2 #define GPIO2_SW_PAD_REG SW_PAD_CTL_GPIO1_GPIO2_GPIO3 #define GPIO2_BYTE_IN_SW_PAD 1 #define GPIO3_SW_PAD_REG SW_PAD_CTL_GPIO1_GPIO2_GPIO3 #define GPIO3_BYTE_IN_SW_PAD 0 #define GPIO4_SW_PAD_REG SW_PAD_CTL_GPIO4_GPIO5_GPIO6 #define GPIO4_BYTE_IN_SW_PAD 2 #define GPIO5_SW_PAD_REG SW_PAD_CTL_GPIO4_GPIO5_GPIO6 #define GPIO5_BYTE_IN_SW_PAD 1 #define GPIO6_SW_PAD_REG SW_PAD_CTL_GPIO4_GPIO5_GPIO6 #define GPIO6_BYTE_IN_SW_PAD 0 #define GPIO7_SW_PAD_REG SW_PAD_CTL_GPIO7_GPIO8_GPIO9 #define GPIO7_BYTE_IN_SW_PAD 2 #define GPIO8_SW_PAD_REG SW_PAD_CTL_GPIO7_GPIO8_GPIO9 #define GPIO8_BYTE_IN_SW_PAD 1 #define GPIO9_SW_PAD_REG SW_PAD_CTL_GPIO7_GPIO8_GPIO9 #define GPIO9_BYTE_IN_SW_PAD 0 #define GPIO10_SW_PAD_REG SW_PAD_CTL_GPIO10_GPIO11_GPIO12 #define GPIO10_BYTE_IN_SW_PAD 2 #define GPIO11_SW_PAD_REG SW_PAD_CTL_GPIO10_GPIO11_GPIO12 #define GPIO11_BYTE_IN_SW_PAD 1 #define GPIO12_SW_PAD_REG SW_PAD_CTL_GPIO10_GPIO11_GPIO12 #define GPIO12_BYTE_IN_SW_PAD 0 #define GPIO13_SW_PAD_REG SW_PAD_CTL_GPIO13_GPIO14_GPIO15 #define GPIO13_BYTE_IN_SW_PAD 2 #define GPIO14_SW_PAD_REG SW_PAD_CTL_GPIO13_GPIO14_GPIO15 #define GPIO14_BYTE_IN_SW_PAD 1 #define GPIO15_SW_PAD_REG SW_PAD_CTL_GPIO13_GPIO14_GPIO15 #define GPIO15_BYTE_IN_SW_PAD 0 #define GPIO16_SW_PAD_REG SW_PAD_CTL_GPIO16_GPIO17_GPIO36 #define GPIO16_BYTE_IN_SW_PAD 2 #define GPIO17_SW_PAD_REG SW_PAD_CTL_GPIO16_GPIO17_GPIO36 #define GPIO17_BYTE_IN_SW_PAD 1 #define GPIO36_SW_PAD_REG SW_PAD_CTL_GPIO16_GPIO17_GPIO36 #define GPIO36_BYTE_IN_SW_PAD 0 #define GPIO37_SW_PAD_REG SW_PAD_CTL_GPIO37_GPIO18_GPIO19 #define GPIO37_BYTE_IN_SW_PAD 2 #define GPIO18_SW_PAD_REG SW_PAD_CTL_GPIO37_GPIO18_GPIO19 #define GPIO18_BYTE_IN_SW_PAD 1 #define GPIO19_SW_PAD_REG SW_PAD_CTL_GPIO37_GPIO18_GPIO19 #define GPIO19_BYTE_IN_SW_PAD 0 #define GPIO20_SW_PAD_REG SW_PAD_CTL_GPIO20_GPIO21_GPIO22 #define GPIO20_BYTE_IN_SW_PAD 2 #define GPIO21_SW_PAD_REG SW_PAD_CTL_GPIO20_GPIO21_GPIO22 #define GPIO21_BYTE_IN_SW_PAD 1 #define GPIO22_SW_PAD_REG SW_PAD_CTL_GPIO20_GPIO21_GPIO22 #define GPIO22_BYTE_IN_SW_PAD 0 #define GPIO23_SW_PAD_REG SW_PAD_CTL_GPIO23_GPIO24_GPIO25 #define GPIO23_BYTE_IN_SW_PAD 2 #define GPIO24_SW_PAD_REG SW_PAD_CTL_GPIO23_GPIO24_GPIO25 #define GPIO24_BYTE_IN_SW_PAD 1 #define GPIO25_SW_PAD_REG SW_PAD_CTL_GPIO23_GPIO24_GPIO25 #define GPIO25_BYTE_IN_SW_PAD 0 #define GPIO26_SW_PAD_REG SW_PAD_CTL_GPIO26_GPIO27_UART_TXD1 #define GPIO26_BYTE_IN_SW_PAD 2 #define GPIO27_SW_PAD_REG SW_PAD_CTL_GPIO26_GPIO27_UART_TXD1 #define GPIO27_BYTE_IN_SW_PAD 1 #define UART_TXD1_SW_PAD_REG SW_PAD_CTL_GPIO26_GPIO27_UART_TXD1 #define UART_TXD1_BYTE_IN_SW_PAD 0 #define UART_RXD1_SW_PAD_REG SW_PAD_CTL_UART_RXD1_UART_RTS1_B_UART_CTS1_B #define UART_RXD1_BYTE_IN_SW_PAD 2 #define UART_RTS1_B_SW_PAD_REG SW_PAD_CTL_UART_RXD1_UART_RTS1_B_UART_CTS1_B #define UART_RTS1_B_BYTE_IN_SW_PAD 1 #define UART_CTS1_B_SW_PAD_REG SW_PAD_CTL_UART_RXD1_UART_RTS1_B_UART_CTS1_B #define UART_CTS1_B_BYTE_IN_SW_PAD 0 #define UART_CTS2_B_SW_PAD_REG SW_PAD_CTL_UART_CTS2_B_UART_DTR2_B_UART_RI2_B #define UART_CTS2_B_BYTE_IN_SW_PAD 2 #define UART_DTR2_B_SW_PAD_REG SW_PAD_CTL_UART_CTS2_B_UART_DTR2_B_UART_RI2_B #define UART_DTR2_B_BYTE_IN_SW_PAD 1 #define UART_RI2_B_SW_PAD_REG SW_PAD_CTL_UART_CTS2_B_UART_DTR2_B_UART_RI2_B #define UART_RI2_B_BYTE_IN_SW_PAD 0 #define UART_DCD2_B_SW_PAD_REG SW_PAD_CTL_UART_DCD2_B_UART_DSR2_B_UART_MUXCTL #define UART_DCD2_B_BYTE_IN_SW_PAD 2 #define UART_DSR2_B_SW_PAD_REG SW_PAD_CTL_UART_DCD2_B_UART_DSR2_B_UART_MUXCTL #define UART_DSR2_B_BYTE_IN_SW_PAD 1 #define UART_MUXCTL_SW_PAD_REG SW_PAD_CTL_UART_DCD2_B_UART_DSR2_B_UART_MUXCTL #define UART_MUXCTL_BYTE_IN_SW_PAD 0 #define IRDA_TX4_SW_PAD_REG SW_PAD_CTL_IRDA_TX4_IRDA_RX4_DAM1_TXD #define IRDA_TX4_BYTE_IN_SW_PAD 2 #define IRDA_RX4_SW_PAD_REG SW_PAD_CTL_IRDA_TX4_IRDA_RX4_DAM1_TXD #define IRDA_RX4_BYTE_IN_SW_PAD 1 #define DAM1_TXD_SW_PAD_REG SW_PAD_CTL_IRDA_TX4_IRDA_RX4_DAM1_TXD #define DAM1_TXD_BYTE_IN_SW_PAD 0 #define DAM1_RXD_SW_PAD_REG SW_PAD_CTL_DAM1_RXD_DAM1_T_CLK_DAM1_T_FS #define DAM1_RXD_BYTE_IN_SW_PAD 2 #define DAM1_T_CLK_SW_PAD_REG SW_PAD_CTL_DAM1_RXD_DAM1_T_CLK_DAM1_T_FS #define DAM1_T_CLK_BYTE_IN_SW_PAD 1 #define DAM1_T_FS_SW_PAD_REG SW_PAD_CTL_DAM1_RXD_DAM1_T_CLK_DAM1_T_FS #define DAM1_T_FS_BYTE_IN_SW_PAD 0 #define DAM2_TXD_SW_PAD_REG SW_PAD_CTL_DAM2_TXD_DAM2_RXD_DAM2_T_CLK #define DAM2_TXD_BYTE_IN_SW_PAD 2 #define DAM2_RXD_SW_PAD_REG SW_PAD_CTL_DAM2_TXD_DAM2_RXD_DAM2_T_CLK #define DAM2_RXD_BYTE_IN_SW_PAD 1 #define DAM2_T_CLK_SW_PAD_REG SW_PAD_CTL_DAM2_TXD_DAM2_RXD_DAM2_T_CLK #define DAM2_T_CLK_BYTE_IN_SW_PAD 0 #define DAM2_T_FS_SW_PAD_REG SW_PAD_CTL_DAM2_T_FS_DAM3_TXD_DAM3_RXD #define DAM2_T_FS_BYTE_IN_SW_PAD 2 #define DAM3_TXD_SW_PAD_REG SW_PAD_CTL_DAM2_T_FS_DAM3_TXD_DAM3_RXD #define DAM3_TXD_BYTE_IN_SW_PAD 1 #define DAM3_RXD_SW_PAD_REG SW_PAD_CTL_DAM2_T_FS_DAM3_TXD_DAM3_RXD #define DAM3_RXD_BYTE_IN_SW_PAD 0 #define DAM3_T_CLK_SW_PAD_REG SW_PAD_CTL_DAM3_T_CLK_DAM3_T_FS_DAM3_R_CLK #define DAM3_T_CLK_BYTE_IN_SW_PAD 2 #define DAM3_T_FS_SW_PAD_REG SW_PAD_CTL_DAM3_T_CLK_DAM3_T_FS_DAM3_R_CLK #define DAM3_T_FS_BYTE_IN_SW_PAD 1 #define DAM3_R_CLK_SW_PAD_REG SW_PAD_CTL_DAM3_T_CLK_DAM3_T_FS_DAM3_R_CLK #define DAM3_R_CLK_BYTE_IN_SW_PAD 0 #define DAM3_R_FS_SW_PAD_REG SW_PAD_CTL_DAM3_R_FS_BATT_LINE_PWM #define DAM3_R_FS_BYTE_IN_SW_PAD 2 #define BATT_LINE_SW_PAD_REG SW_PAD_CTL_DAM3_R_FS_BATT_LINE_PWM #define BATT_LINE_BYTE_IN_SW_PAD 1 #define PWM_SW_PAD_REG SW_PAD_CTL_DAM3_R_FS_BATT_LINE_PWM #define PWM_BYTE_IN_SW_PAD 0 #define CSPI2_CK_SW_PAD_REG SW_PAD_CTL_CSPI2_CK_CSPI2_DO_CSPI2_DI #define CSPI2_CK_BYTE_IN_SW_PAD 2 #define CSPI2_DO_SW_PAD_REG SW_PAD_CTL_CSPI2_CK_CSPI2_DO_CSPI2_DI #define CSPI2_DO_BYTE_IN_SW_PAD 1 #define CSPI2_DI_SW_PAD_REG SW_PAD_CTL_CSPI2_CK_CSPI2_DO_CSPI2_DI #define CSPI2_DI_BYTE_IN_SW_PAD 0 #define CSPI2_CS_0_SW_PAD_REG SW_PAD_CTL_CSPI2_CS_0_CSPI2_CS_1_CSPI1_CK #define CSPI2_CS_0_BYTE_IN_SW_PAD 2 #define CSPI2_CS_1_SW_PAD_REG SW_PAD_CTL_CSPI2_CS_0_CSPI2_CS_1_CSPI1_CK #define CSPI2_CS_1_BYTE_IN_SW_PAD 1 #define CSPI1_CK_SW_PAD_REG SW_PAD_CTL_CSPI2_CS_0_CSPI2_CS_1_CSPI1_CK #define CSPI1_CK_BYTE_IN_SW_PAD 0 #define CSPI1_DO_SW_PAD_REG SW_PAD_CTL_CSPI1_DO_CSPI1_DI_CSPI1_CS_0 #define CSPI1_DO_BYTE_IN_SW_PAD 2 #define CSPI1_DI_SW_PAD_REG SW_PAD_CTL_CSPI1_DO_CSPI1_DI_CSPI1_CS_0 #define CSPI1_DI_BYTE_IN_SW_PAD 1 #define CSPI1_CS_0_SW_PAD_REG SW_PAD_CTL_CSPI1_DO_CSPI1_DI_CSPI1_CS_0 #define CSPI1_CS_0_BYTE_IN_SW_PAD 0 #define CSPI1_CS_1_SW_PAD_REG SW_PAD_CTL_CSPI1_CS_1_IPU_FDAT_0_IPU_FDAT_1 #define CSPI1_CS_1_BYTE_IN_SW_PAD 2 #define IPU_FDAT_0_SW_PAD_REG SW_PAD_CTL_CSPI1_CS_1_IPU_FDAT_0_IPU_FDAT_1 #define IPU_FDAT_0_BYTE_IN_SW_PAD 1 #define IPU_FDAT_1_SW_PAD_REG SW_PAD_CTL_CSPI1_CS_1_IPU_FDAT_0_IPU_FDAT_1 #define IPU_FDAT_1_BYTE_IN_SW_PAD 0 #define IPU_FDAT_2_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_2_IPU_FDAT_3_IPU_FDAT_4 #define IPU_FDAT_2_BYTE_IN_SW_PAD 2 #define IPU_FDAT_3_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_2_IPU_FDAT_3_IPU_FDAT_4 #define IPU_FDAT_3_BYTE_IN_SW_PAD 1 #define IPU_FDAT_4_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_2_IPU_FDAT_3_IPU_FDAT_4 #define IPU_FDAT_4_BYTE_IN_SW_PAD 0 #define IPU_FDAT_5_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_5_IPU_FDAT_6_IPU_FDAT_7 #define IPU_FDAT_5_BYTE_IN_SW_PAD 2 #define IPU_FDAT_6_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_5_IPU_FDAT_6_IPU_FDAT_7 #define IPU_FDAT_6_BYTE_IN_SW_PAD 1 #define IPU_FDAT_7_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_5_IPU_FDAT_6_IPU_FDAT_7 #define IPU_FDAT_7_BYTE_IN_SW_PAD 0 #define IPU_FDAT_8_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_8_IPU_FDAT_9_IPU_FDAT_10 #define IPU_FDAT_8_BYTE_IN_SW_PAD 2 #define IPU_FDAT_9_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_8_IPU_FDAT_9_IPU_FDAT_10 #define IPU_FDAT_9_BYTE_IN_SW_PAD 1 #define IPU_FDAT_10_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_8_IPU_FDAT_9_IPU_FDAT_10 #define IPU_FDAT_10_BYTE_IN_SW_PAD 0 #define IPU_FDAT_11_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_11_IPU_FDAT_12_IPU_FDAT_13 #define IPU_FDAT_11_BYTE_IN_SW_PAD 2 #define IPU_FDAT_12_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_11_IPU_FDAT_12_IPU_FDAT_13 #define IPU_FDAT_12_BYTE_IN_SW_PAD 1 #define IPU_FDAT_13_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_11_IPU_FDAT_12_IPU_FDAT_13 #define IPU_FDAT_13_BYTE_IN_SW_PAD 0 #define IPU_FDAT_14_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_14_IPU_FDAT_15_IPU_FDAT_16 #define IPU_FDAT_14_BYTE_IN_SW_PAD 2 #define IPU_FDAT_15_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_14_IPU_FDAT_15_IPU_FDAT_16 #define IPU_FDAT_15_BYTE_IN_SW_PAD 1 #define IPU_FDAT_16_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_14_IPU_FDAT_15_IPU_FDAT_16 #define IPU_FDAT_16_BYTE_IN_SW_PAD 0 #define IPU_FDAT_17_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_17_IPU_VSYNC0_IPU_HSYNC #define IPU_FDAT_17_BYTE_IN_SW_PAD 2 #define IPU_VSYNC0_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_17_IPU_VSYNC0_IPU_HSYNC #define IPU_VSYNC0_BYTE_IN_SW_PAD 1 #define IPU_HSYNC_SW_PAD_REG SW_PAD_CTL_IPU_FDAT_17_IPU_VSYNC0_IPU_HSYNC #define IPU_HSYNC_BYTE_IN_SW_PAD 0 #define IPU_VSYNC3_SW_PAD_REG SW_PAD_CTL_IPU_VSYNC3_IPU_LCS0_IPU_FPSHIFT #define IPU_VSYNC3_BYTE_IN_SW_PAD 2 #define IPU_LCS0_SW_PAD_REG SW_PAD_CTL_IPU_VSYNC3_IPU_LCS0_IPU_FPSHIFT #define IPU_LCS0_BYTE_IN_SW_PAD 1 #define IPU_FPSHIFT_SW_PAD_REG SW_PAD_CTL_IPU_VSYNC3_IPU_LCS0_IPU_FPSHIFT #define IPU_FPSHIFT_BYTE_IN_SW_PAD 0 #define IPU_DRDY0_SW_PAD_REG SW_PAD_CTL_IPU_DRDY0_IPU_CONTRAST1_IPU_LCS1 #define IPU_DRDY0_BYTE_IN_SW_PAD 2 #define IPU_CONTRAST1_SW_PAD_REG SW_PAD_CTL_IPU_DRDY0_IPU_CONTRAST1_IPU_LCS1 #define IPU_CONTRAST1_BYTE_IN_SW_PAD 1 #define IPU_LCS1_SW_PAD_REG SW_PAD_CTL_IPU_DRDY0_IPU_CONTRAST1_IPU_LCS1 #define IPU_LCS1_BYTE_IN_SW_PAD 0 #define IPU_SD_D_IO_SW_PAD_REG SW_PAD_CTL_IPU_SD_D_IO_IPU_SD_D_O_IPU_SD_D_CLK #define IPU_SD_D_IO_BYTE_IN_SW_PAD 2 #define IPU_SD_D_O_SW_PAD_REG SW_PAD_CTL_IPU_SD_D_IO_IPU_SD_D_O_IPU_SD_D_CLK #define IPU_SD_D_O_BYTE_IN_SW_PAD 1 #define IPU_SD_D_CLK_SW_PAD_REG SW_PAD_CTL_IPU_SD_D_IO_IPU_SD_D_O_IPU_SD_D_CLK #define IPU_SD_D_CLK_BYTE_IN_SW_PAD 0 #define IPU_SER_RS_SW_PAD_REG SW_PAD_CTL_IPU_SER_RS_IPU_PAR_RS_IPU_WRITE #define IPU_SER_RS_BYTE_IN_SW_PAD 2 #define IPU_PAR_RS_SW_PAD_REG SW_PAD_CTL_IPU_SER_RS_IPU_PAR_RS_IPU_WRITE #define IPU_PAR_RS_BYTE_IN_SW_PAD 1 #define IPU_WRITE_SW_PAD_REG SW_PAD_CTL_IPU_SER_RS_IPU_PAR_RS_IPU_WRITE #define IPU_WRITE_BYTE_IN_SW_PAD 0 #define IPU_READ_SW_PAD_REG SW_PAD_CTL_IPU_READ_IPU_D3_CLS_IPU_D3_SPL #define IPU_READ_BYTE_IN_SW_PAD 2 #define IPU_D3_CLS_SW_PAD_REG SW_PAD_CTL_IPU_READ_IPU_D3_CLS_IPU_D3_SPL #define IPU_D3_CLS_BYTE_IN_SW_PAD 1 #define IPU_D3_SPL_SW_PAD_REG SW_PAD_CTL_IPU_READ_IPU_D3_CLS_IPU_D3_SPL #define IPU_D3_SPL_BYTE_IN_SW_PAD 0 #define IPU_D3_REV_SW_PAD_REG SW_PAD_CTL_IPU_D3_REV_IPU_CSI_MCLK_IPU_CSI_HSYNC #define IPU_D3_REV_BYTE_IN_SW_PAD 2 #define IPU_CSI_MCLK_SW_PAD_REG SW_PAD_CTL_IPU_D3_REV_IPU_CSI_MCLK_IPU_CSI_HSYNC #define IPU_CSI_MCLK_BYTE_IN_SW_PAD 1 #define IPU_CSI_HSYNC_SW_PAD_REG SW_PAD_CTL_IPU_D3_REV_IPU_CSI_MCLK_IPU_CSI_HSYNC #define IPU_CSI_HSYNC_BYTE_IN_SW_PAD 0 #define IPU_CSI_VSYNC_SW_PAD_REG SW_PAD_CTL_IPU_CSI_VSYNC_IPU_CSI_DATA_0_IPU_CSI_DATA_1 #define IPU_CSI_VSYNC_BYTE_IN_SW_PAD 2 #define IPU_CSI_DATA_0_SW_PAD_REG SW_PAD_CTL_IPU_CSI_VSYNC_IPU_CSI_DATA_0_IPU_CSI_DATA_1 #define IPU_CSI_DATA_0_BYTE_IN_SW_PAD 1 #define IPU_CSI_DATA_1_SW_PAD_REG SW_PAD_CTL_IPU_CSI_VSYNC_IPU_CSI_DATA_0_IPU_CSI_DATA_1 #define IPU_CSI_DATA_1_BYTE_IN_SW_PAD 0 #define IPU_CSI_DATA_2_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_2_IPU_CSI_DATA_3_IPU_CSI_DATA_4 #define IPU_CSI_DATA_2_BYTE_IN_SW_PAD 2 #define IPU_CSI_DATA_3_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_2_IPU_CSI_DATA_3_IPU_CSI_DATA_4 #define IPU_CSI_DATA_3_BYTE_IN_SW_PAD 1 #define IPU_CSI_DATA_4_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_2_IPU_CSI_DATA_3_IPU_CSI_DATA_4 #define IPU_CSI_DATA_4_BYTE_IN_SW_PAD 0 #define IPU_CSI_DATA_5_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_5_IPU_CSI_DATA_6_IPU_CSI_DATA_7 #define IPU_CSI_DATA_5_BYTE_IN_SW_PAD 2 #define IPU_CSI_DATA_6_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_5_IPU_CSI_DATA_6_IPU_CSI_DATA_7 #define IPU_CSI_DATA_6_BYTE_IN_SW_PAD 1 #define IPU_CSI_DATA_7_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_5_IPU_CSI_DATA_6_IPU_CSI_DATA_7 #define IPU_CSI_DATA_7_BYTE_IN_SW_PAD 0 #define IPU_CSI_DATA_8_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_8_IPU_CSI_DATA_9_IPU_CSI_PIXCLK #define IPU_CSI_DATA_8_BYTE_IN_SW_PAD 2 #define IPU_CSI_DATA_9_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_8_IPU_CSI_DATA_9_IPU_CSI_PIXCLK #define IPU_CSI_DATA_9_BYTE_IN_SW_PAD 1 #define IPU_CSI_PIXCLK_SW_PAD_REG SW_PAD_CTL_IPU_CSI_DATA_8_IPU_CSI_DATA_9_IPU_CSI_PIXCLK #define IPU_CSI_PIXCLK_BYTE_IN_SW_PAD 0 #define I2C_CLK_SW_PAD_REG SW_PAD_CTL_I2C_CLK_I2C_DAT_KEY_ROW0 #define I2C_CLK_BYTE_IN_SW_PAD 2 #define I2C_DAT_SW_PAD_REG SW_PAD_CTL_I2C_CLK_I2C_DAT_KEY_ROW0 #define I2C_DAT_BYTE_IN_SW_PAD 1 #define KEY_ROW0_SW_PAD_REG SW_PAD_CTL_I2C_CLK_I2C_DAT_KEY_ROW0 #define KEY_ROW0_BYTE_IN_SW_PAD 0 #define KEY_ROW1_SW_PAD_REG SW_PAD_CTL_KEY_ROW1_KEY_ROW2_KEY_ROW3 #define KEY_ROW1_BYTE_IN_SW_PAD 2 #define KEY_ROW2_SW_PAD_REG SW_PAD_CTL_KEY_ROW1_KEY_ROW2_KEY_ROW3 #define KEY_ROW2_BYTE_IN_SW_PAD 1 #define KEY_ROW3_SW_PAD_REG SW_PAD_CTL_KEY_ROW1_KEY_ROW2_KEY_ROW3 #define KEY_ROW3_BYTE_IN_SW_PAD 0 #define KEY_ROW4_SW_PAD_REG SW_PAD_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6 #define KEY_ROW4_BYTE_IN_SW_PAD 2 #define KEY_ROW5_SW_PAD_REG SW_PAD_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6 #define KEY_ROW5_BYTE_IN_SW_PAD 1 #define KEY_ROW6_SW_PAD_REG SW_PAD_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6 #define KEY_ROW6_BYTE_IN_SW_PAD 0 #define KEY_ROW7_SW_PAD_REG SW_PAD_CTL_KEY_ROW7_KEY_COL0_KEY_COL1 #define KEY_ROW7_BYTE_IN_SW_PAD 2 #define KEY_COL0_SW_PAD_REG SW_PAD_CTL_KEY_ROW7_KEY_COL0_KEY_COL1 #define KEY_COL0_BYTE_IN_SW_PAD 1 #define KEY_COL1_SW_PAD_REG SW_PAD_CTL_KEY_ROW7_KEY_COL0_KEY_COL1 #define KEY_COL1_BYTE_IN_SW_PAD 0 #define KEY_COL2_SW_PAD_REG SW_PAD_CTL_KEY_COL2_KEY_COL3_KEY_COL4 #define KEY_COL2_BYTE_IN_SW_PAD 2 #define KEY_COL3_SW_PAD_REG SW_PAD_CTL_KEY_COL2_KEY_COL3_KEY_COL4 #define KEY_COL3_BYTE_IN_SW_PAD 1 #define KEY_COL4_SW_PAD_REG SW_PAD_CTL_KEY_COL2_KEY_COL3_KEY_COL4 #define KEY_COL4_BYTE_IN_SW_PAD 0 #define KEY_COL5_SW_PAD_REG SW_PAD_CTL_KEY_COL5_KEY_COL6_KEY_COL7 #define KEY_COL5_BYTE_IN_SW_PAD 2 #define KEY_COL6_SW_PAD_REG SW_PAD_CTL_KEY_COL5_KEY_COL6_KEY_COL7 #define KEY_COL6_BYTE_IN_SW_PAD 1 #define KEY_COL7_SW_PAD_REG SW_PAD_CTL_KEY_COL5_KEY_COL6_KEY_COL7 #define KEY_COL7_BYTE_IN_SW_PAD 0 #define MMC1_CMD_SW_PAD_REG SW_PAD_CTL_MMC1_CMD_MMC1_DATA_0_MMC1_DATA_1 #define MMC1_CMD_BYTE_IN_SW_PAD 2 #define MMC1_DATA_0_SW_PAD_REG SW_PAD_CTL_MMC1_CMD_MMC1_DATA_0_MMC1_DATA_1 #define MMC1_DATA_0_BYTE_IN_SW_PAD 1 #define MMC1_DATA_1_SW_PAD_REG SW_PAD_CTL_MMC1_CMD_MMC1_DATA_0_MMC1_DATA_1 #define MMC1_DATA_1_BYTE_IN_SW_PAD 0 #define MMC1_DATA_2_SW_PAD_REG SW_PAD_CTL_MMC1_DATA_2_MMC1_DATA_3_MMC1_CLK #define MMC1_DATA_2_BYTE_IN_SW_PAD 2 #define MMC1_DATA_3_SW_PAD_REG SW_PAD_CTL_MMC1_DATA_2_MMC1_DATA_3_MMC1_CLK #define MMC1_DATA_3_BYTE_IN_SW_PAD 1 #define MMC1_CLK_SW_PAD_REG SW_PAD_CTL_MMC1_DATA_2_MMC1_DATA_3_MMC1_CLK #define MMC1_CLK_BYTE_IN_SW_PAD 0 #define MMC1_SDDET_SW_PAD_REG SW_PAD_CTL_MMC1_SDDET_MMC2_CMD_MMC2_DATA_0 #define MMC1_SDDET_BYTE_IN_SW_PAD 2 #define MMC2_CMD_SW_PAD_REG SW_PAD_CTL_MMC1_SDDET_MMC2_CMD_MMC2_DATA_0 #define MMC2_CMD_BYTE_IN_SW_PAD 1 #define MMC2_DATA_0_SW_PAD_REG SW_PAD_CTL_MMC1_SDDET_MMC2_CMD_MMC2_DATA_0 #define MMC2_DATA_0_BYTE_IN_SW_PAD 0 #define MMC2_DATA_1_SW_PAD_REG SW_PAD_CTL_MMC2_DATA_1_MMC2_DATA_2_MMC2_DATA_3 #define MMC2_DATA_1_BYTE_IN_SW_PAD 2 #define MMC2_DATA_2_SW_PAD_REG SW_PAD_CTL_MMC2_DATA_1_MMC2_DATA_2_MMC2_DATA_3 #define MMC2_DATA_2_BYTE_IN_SW_PAD 1 #define MMC2_DATA_3_SW_PAD_REG SW_PAD_CTL_MMC2_DATA_1_MMC2_DATA_2_MMC2_DATA_3 #define MMC2_DATA_3_BYTE_IN_SW_PAD 0 #define MMC2_CLK_SW_PAD_REG SW_PAD_CTL_MMC2_CLK_TRACE0_TRACE1 #define MMC2_CLK_BYTE_IN_SW_PAD 2 #define TRACE0_SW_PAD_REG SW_PAD_CTL_MMC2_CLK_TRACE0_TRACE1 #define TRACE0_BYTE_IN_SW_PAD 1 #define TRACE1_SW_PAD_REG SW_PAD_CTL_MMC2_CLK_TRACE0_TRACE1 #define TRACE1_BYTE_IN_SW_PAD 0 #define TRACE2_SW_PAD_REG SW_PAD_CTL_TRACE2_TRACE3_TRACE4 #define TRACE2_BYTE_IN_SW_PAD 2 #define TRACE3_SW_PAD_REG SW_PAD_CTL_TRACE2_TRACE3_TRACE4 #define TRACE3_BYTE_IN_SW_PAD 1 #define TRACE4_SW_PAD_REG SW_PAD_CTL_TRACE2_TRACE3_TRACE4 #define TRACE4_BYTE_IN_SW_PAD 0 #define TRACE5_SW_PAD_REG SW_PAD_CTL_TRACE5_TRACE6_TRACE7 #define TRACE5_BYTE_IN_SW_PAD 2 #define TRACE6_SW_PAD_REG SW_PAD_CTL_TRACE5_TRACE6_TRACE7 #define TRACE6_BYTE_IN_SW_PAD 1 #define TRACE7_SW_PAD_REG SW_PAD_CTL_TRACE5_TRACE6_TRACE7 #define TRACE7_BYTE_IN_SW_PAD 0 #define TRACE8_SW_PAD_REG SW_PAD_CTL_TRACE8_TRACE9_TRACE10 #define TRACE8_BYTE_IN_SW_PAD 2 #define TRACE9_SW_PAD_REG SW_PAD_CTL_TRACE8_TRACE9_TRACE10 #define TRACE9_BYTE_IN_SW_PAD 1 #define TRACE10_SW_PAD_REG SW_PAD_CTL_TRACE8_TRACE9_TRACE10 #define TRACE10_BYTE_IN_SW_PAD 0 #define TRACE11_SW_PAD_REG SW_PAD_CTL_TRACE11_TRACE12_TRACE13 #define TRACE11_BYTE_IN_SW_PAD 2 #define TRACE12_SW_PAD_REG SW_PAD_CTL_TRACE11_TRACE12_TRACE13 #define TRACE12_BYTE_IN_SW_PAD 1 #define TRACE13_SW_PAD_REG SW_PAD_CTL_TRACE11_TRACE12_TRACE13 #define TRACE13_BYTE_IN_SW_PAD 0 #define TRACE14_SW_PAD_REG SW_PAD_CTL_TRACE14_TRACE15_TRACE16 #define TRACE14_BYTE_IN_SW_PAD 2 #define TRACE15_SW_PAD_REG SW_PAD_CTL_TRACE14_TRACE15_TRACE16 #define TRACE15_BYTE_IN_SW_PAD 1 #define TRACE16_SW_PAD_REG SW_PAD_CTL_TRACE14_TRACE15_TRACE16 #define TRACE16_BYTE_IN_SW_PAD 0 #define TRACE17_SW_PAD_REG SW_PAD_CTL_TRACE17_TRACE18_TRACE19 #define TRACE17_BYTE_IN_SW_PAD 2 #define TRACE18_SW_PAD_REG SW_PAD_CTL_TRACE17_TRACE18_TRACE19 #define TRACE18_BYTE_IN_SW_PAD 1 #define TRACE19_SW_PAD_REG SW_PAD_CTL_TRACE17_TRACE18_TRACE19 #define TRACE19_BYTE_IN_SW_PAD 0 #define TRACE20_SW_PAD_REG SW_PAD_CTL_TRACE20_TRACE21_TRACE22 #define TRACE20_BYTE_IN_SW_PAD 2 #define TRACE21_SW_PAD_REG SW_PAD_CTL_TRACE20_TRACE21_TRACE22 #define TRACE21_BYTE_IN_SW_PAD 1 #define TRACE22_SW_PAD_REG SW_PAD_CTL_TRACE20_TRACE21_TRACE22 #define TRACE22_BYTE_IN_SW_PAD 0 #define TRACE23_SW_PAD_REG SW_PAD_CTL_TRACE23_TRACE24_TRACE25 #define TRACE23_BYTE_IN_SW_PAD 2 #define TRACE24_SW_PAD_REG SW_PAD_CTL_TRACE23_TRACE24_TRACE25 #define TRACE24_BYTE_IN_SW_PAD 1 #define TRACE25_SW_PAD_REG SW_PAD_CTL_TRACE23_TRACE24_TRACE25 #define TRACE25_BYTE_IN_SW_PAD 0 #define TRACE26_SW_PAD_REG SW_PAD_CTL_TRACE26_TRACE27_TRACE28 #define TRACE26_BYTE_IN_SW_PAD 2 #define TRACE27_SW_PAD_REG SW_PAD_CTL_TRACE26_TRACE27_TRACE28 #define TRACE27_BYTE_IN_SW_PAD 1 #define TRACE28_SW_PAD_REG SW_PAD_CTL_TRACE26_TRACE27_TRACE28 #define TRACE28_BYTE_IN_SW_PAD 0 #define TRACE29_SW_PAD_REG SW_PAD_CTL_TRACE29_TRACE30_TRACE31 #define TRACE29_BYTE_IN_SW_PAD 2 #define TRACE30_SW_PAD_REG SW_PAD_CTL_TRACE29_TRACE30_TRACE31 #define TRACE30_BYTE_IN_SW_PAD 1 #define TRACE31_SW_PAD_REG SW_PAD_CTL_TRACE29_TRACE30_TRACE31 #define TRACE31_BYTE_IN_SW_PAD 0 #define DBGACK_SW_PAD_REG SW_PAD_CTL_DBGACK_TRCLK_SRST #define DBGACK_BYTE_IN_SW_PAD 2 #define TRCLK_SW_PAD_REG SW_PAD_CTL_DBGACK_TRCLK_SRST #define TRCLK_BYTE_IN_SW_PAD 1 #define SRST_SW_PAD_REG SW_PAD_CTL_DBGACK_TRCLK_SRST #define SRST_BYTE_IN_SW_PAD 0 #define DBGRQ_SW_PAD_REG SW_PAD_CTL_DBGRQ_EXTRIG_MDO0 #define DBGRQ_BYTE_IN_SW_PAD 2 #define EXTRIG_SW_PAD_REG SW_PAD_CTL_DBGRQ_EXTRIG_MDO0 #define EXTRIG_BYTE_IN_SW_PAD 1 #define MDO0_SW_PAD_REG SW_PAD_CTL_DBGRQ_EXTRIG_MDO0 #define MDO0_BYTE_IN_SW_PAD 0 #define MDO1_SW_PAD_REG SW_PAD_CTL_MDO1_MDO2_MDO3 #define MDO1_BYTE_IN_SW_PAD 2 #define MDO2_SW_PAD_REG SW_PAD_CTL_MDO1_MDO2_MDO3 #define MDO2_BYTE_IN_SW_PAD 1 #define MDO3_SW_PAD_REG SW_PAD_CTL_MDO1_MDO2_MDO3 #define MDO3_BYTE_IN_SW_PAD 0 #define MDO4_SW_PAD_REG SW_PAD_CTL_MDO4_MDO5_MDO6 #define MDO4_BYTE_IN_SW_PAD 2 #define MDO5_SW_PAD_REG SW_PAD_CTL_MDO4_MDO5_MDO6 #define MDO5_BYTE_IN_SW_PAD 1 #define MDO6_SW_PAD_REG SW_PAD_CTL_MDO4_MDO5_MDO6 #define MDO6_BYTE_IN_SW_PAD 0 #define MDO7_SW_PAD_REG SW_PAD_CTL_MDO7_MDO8_MDO9 #define MDO7_BYTE_IN_SW_PAD 2 #define MDO8_SW_PAD_REG SW_PAD_CTL_MDO7_MDO8_MDO9 #define MDO8_BYTE_IN_SW_PAD 1 #define MDO9_SW_PAD_REG SW_PAD_CTL_MDO7_MDO8_MDO9 #define MDO9_BYTE_IN_SW_PAD 0 #define MDO10_SW_PAD_REG SW_PAD_CTL_MDO10_MDO11_MDO12 #define MDO10_BYTE_IN_SW_PAD 2 #define MDO11_SW_PAD_REG SW_PAD_CTL_MDO10_MDO11_MDO12 #define MDO11_BYTE_IN_SW_PAD 1 #define MDO12_SW_PAD_REG SW_PAD_CTL_MDO10_MDO11_MDO12 #define MDO12_BYTE_IN_SW_PAD 0 #define MDO13_SW_PAD_REG SW_PAD_CTL_MDO13_MDO14_MDO15 #define MDO13_BYTE_IN_SW_PAD 2 #define MDO14_SW_PAD_REG SW_PAD_CTL_MDO13_MDO14_MDO15 #define MDO14_BYTE_IN_SW_PAD 1 #define MDO15_SW_PAD_REG SW_PAD_CTL_MDO13_MDO14_MDO15 #define MDO15_BYTE_IN_SW_PAD 0 #define MDO16_SW_PAD_REG SW_PAD_CTL_MDO16_MDO17_MDO18 #define MDO16_BYTE_IN_SW_PAD 2 #define MDO17_SW_PAD_REG SW_PAD_CTL_MDO16_MDO17_MDO18 #define MDO17_BYTE_IN_SW_PAD 1 #define MDO18_SW_PAD_REG SW_PAD_CTL_MDO16_MDO17_MDO18 #define MDO18_BYTE_IN_SW_PAD 0 #define MDO19_SW_PAD_REG SW_PAD_CTL_MDO19_MDO20_MDO21 #define MDO19_BYTE_IN_SW_PAD 2 #define MDO20_SW_PAD_REG SW_PAD_CTL_MDO19_MDO20_MDO21 #define MDO20_BYTE_IN_SW_PAD 1 #define MDO21_SW_PAD_REG SW_PAD_CTL_MDO19_MDO20_MDO21 #define MDO21_BYTE_IN_SW_PAD 0 #define MDO22_SW_PAD_REG SW_PAD_CTL_MDO22_MDO23_MDO24 #define MDO22_BYTE_IN_SW_PAD 2 #define MDO23_SW_PAD_REG SW_PAD_CTL_MDO22_MDO23_MDO24 #define MDO23_BYTE_IN_SW_PAD 1 #define MDO24_SW_PAD_REG SW_PAD_CTL_MDO22_MDO23_MDO24 #define MDO24_BYTE_IN_SW_PAD 0 #define MDO25_SW_PAD_REG SW_PAD_CTL_MDO25_MDO26_MDO27 #define MDO25_BYTE_IN_SW_PAD 2 #define MDO26_SW_PAD_REG SW_PAD_CTL_MDO25_MDO26_MDO27 #define MDO26_BYTE_IN_SW_PAD 1 #define MDO27_SW_PAD_REG SW_PAD_CTL_MDO25_MDO26_MDO27 #define MDO27_BYTE_IN_SW_PAD 0 #define MDO28_SW_PAD_REG SW_PAD_CTL_MDO28_MDO29_MDO30 #define MDO28_BYTE_IN_SW_PAD 2 #define MDO29_SW_PAD_REG SW_PAD_CTL_MDO28_MDO29_MDO30 #define MDO29_BYTE_IN_SW_PAD 1 #define MDO30_SW_PAD_REG SW_PAD_CTL_MDO28_MDO29_MDO30 #define MDO30_BYTE_IN_SW_PAD 0 #define MDO31_SW_PAD_REG SW_PAD_CTL_MDO31_MSE1_EVTO #define MDO31_BYTE_IN_SW_PAD 2 #define MSE1_SW_PAD_REG SW_PAD_CTL_MDO31_MSE1_EVTO #define MSE1_BYTE_IN_SW_PAD 1 #define EVTO_SW_PAD_REG SW_PAD_CTL_MDO31_MSE1_EVTO #define EVTO_BYTE_IN_SW_PAD 0 #define MRDY_SW_PAD_REG SW_PAD_CTL_MRDY_MCKO_MSE0 #define MRDY_BYTE_IN_SW_PAD 2 #define MCKO_SW_PAD_REG SW_PAD_CTL_MRDY_MCKO_MSE0 #define MCKO_BYTE_IN_SW_PAD 1 #define MSE0_SW_PAD_REG SW_PAD_CTL_MRDY_MCKO_MSE0 #define MSE0_BYTE_IN_SW_PAD 0 // Defines for the iomux input mode : #define gpio_in 0x01 #define func_in 0x02 #define gpio_func_in 0x03 #define alt1_in 0x04 #define gpio_alt1_in 0x05 #define func_alt1_in 0x06 #define gpio_func_alt1_in 0x07 #define alt2_in 0x08 #define gpio_alt2_in 0x09 #define func_alt2_in 0x0a #define gpio_func_alt2_in 0x0b #define alt1_alt2_in 0x0c #define gpio_alt1_alt2_in 0x0d #define func_alt1_alt2_in 0x0e #define gpio_func_alt1_alt2_in 0x0f // Defines for the iomux output mode : #define gpio_out 0x00 #define func_out 0x10 #define alt1_out 0x20 #define alt2_out 0x30 #define alt3_out 0x40 #define alt4_out 0x50 #define alt5_out 0x60 #define alt6_out 0x70 #define BYTE3_MASK 0xff000000 #define BYTE2_MASK 0xff0000 #define BYTE1_MASK 0xff00 #define BYTE0_MASK 0xff #define PAD2_MASK 0x3ff00000 #define PAD1_MASK 0xffc00 #define PAD0_MASK 0x3ff #endif