// this file contains varius common iomux setting functions.
// the functions are on the form:
// set_iomux_<bus/block>_via_<ports/mode>
// function list:
// set_iomux_arm11pevntbus_via_audio_ports (using audio ports 3-6 - 16 bit)
// set_iomux_arm11pevntbus_via_full_uart   (using all 20 bits)
// set_iomux_etm_via_etm_primary_24bit     
// set_iomux_etm_via_etm_primary_16bit     
// set_iomux_etm_via_etm_primary_8bit
// set_iomux_etm_via_alternate_etm_16bit
// set_iomux_etm_via_alternate_etm_8bit
// set_iomux_uart1_via_full_uart           (12 bit, using both DTE and DCE pads)
// set_iomux_uart1_via_8wire_dce           (8 bit, DCE mode. note that this is pad configuration ONLY)
// set_iomux_uart1_via_8wire_dte           (8 bit, DTE mode. note that this is pad configuration ONLY)
// set_iomux_uart2_via_8wire_dce           (8 bit, DCE mode. note that this is pad configuration ONLY)
// set_iomux_uart2_via_8wire_dte           (8 bit, DTE mode. note that this is pad configuration ONLY)
// set_iomux_uart3_via_cspi1               (via CSPI1_MOSI CSPI1_MISO CSPI1_SS0 CSPI1_SS2)
// set_iomux_uart3_via_cspi3               (via CSPI3_MOSI CSPI3_MISO CSPI3_SCLK CSPI3_SPI_RDY)
// set_iomux_uart4_via_usbotg              (via USBOTG_DATA5 USBOTG_DATA4 USBOTG_DATA3 USBOTG_DATA0)
// set_iomux_uart4_via_ata                 (via ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW)
// set_iomux_uart5_via_usbh2               (via USBH2_CLK USBH2_DIR USBH2_STP USBH2_NXT)
// set_iomux_uart5_via_pcmcia              (via PC_VS2 PC_BVD1 PC_BVD2 PC_RST)
// set_iomux_cspi1_via_cspi_8bit           (uses dedicated pins and CSPI2_SS1)
// set_iomux_cspi1_via_cspi_and_uart_8bit  (uses dedicated pins and DCD_DCE1)
// set_iomux_cspi1_via_uart_8bit           (uses alternate setting via UART pins)
// set_iomux_cspi2_via_cspi_8bit           (uses dedicated pins and CSPI1_SS1)        
// set_iomux_cspi3_via_cspi_8bit           (uses dedicated pins and CSPI1_SS0 CSPI1_SS2 CSPI2_SS0 CSPI2_SS1)
// set_iomux_mshc1_via_sdhc1               (MSHC1 takes over SDHC1 dedicated pins. 6 bit)
// set_iomux_mshc2_via_pcmcia              (via PC_CD1_B, PC_CD2_B, PC_WAIT_B, PC_READY, PC_POWERON, PC_VS1)
// set_iomux_epit1_via_gpt                 (put COMPARE in alt4)
// set_iomux_epit2_via_gpt                 (put COMPARE in alt5) 
// set_iomux_gpt_via_alternate_setting     (CAPTURE becomes input clock, COMPARE becomes capture)
// set_iomux_i2c3_via_cspi2                (via CSPI2_SS2 and CSPI2_SCLK)
// set_iomux_i2c2_via_cspi2                (via CSPI2_MOSI and CSPI2_MISO)
// set_iomux_i2c2_via_uart1                (via RI_DTE1 and DCD_DTE1)
// set_iomux_i2c1_via_dedicated_pins
// set_iomux_audio_port3_via_dedicated_pins
// set_iomux_audio_port4_via_dedicated_pins
// set_iomux_audio_port5_via_dedicated_pins
// set_iomux_audio_port6_via_dedicated_pins
// set_iomux_cspi1_via_dedicated_pins
// set_iomux_cspi2_via_dedicated_pins
// set_iomux_cspi3_via_dedicated_pins
// set_iomux_uart1_via_dedicated_pins
// set_iomux_uart2_via_dedicated_pins
// set_iomux_sim_via_dedicated_pins
// set_iomux_kpp_via_dedicated_pins
// set_iomux_gpt_via_dedicated_pins
// set_iomux_sdhc1_via_dedicated_pins

// contact: giladb, RM96492, FIL

//#include "config_pad_mode.h"
#include "functions.h"

// dedicated pins functions:

void set_iomux_i2c1_via_dedicated_pins(){
    reg32_write_mask(SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT,0x00001212,0x0000ffff);
}

//void set_iomux_gpt_via_dedicated_pins (){
//    config_pad_mode(COMPARE,func_out,func_in);
//    config_pad_mode(CAPTURE,func_out,func_in);
//}

void set_iomux_kpp_via_dedicated_pins (){
    reg32_write(SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3,0x12121212);
    reg32_write(SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7,0x12121212);
    reg32_write(SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3,0x12121212);
    reg32_write(SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7,0x12121212);
}

void set_iomux_audio_port3_via_dedicated_pins (){
    reg32_write(SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3,0x12121212);
}

void set_iomux_audio_port4_via_dedicated_pins (){
    reg32_write(SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4,0x12121212);
}

void set_iomux_audio_port5_via_dedicated_pins (){
    reg32_write(SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5,0x12121212);
}

void set_iomux_audio_port6_via_dedicated_pins (){
    reg32_write(SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6,0x12121212);
}
   
void set_iomux_cspi1_via_dedicated_pins (){
    reg32_write(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1,0x12121212);
    reg32_write_mask(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI,0x12121200,0xffffff00);
}

void set_iomux_cspi2_via_dedicated_pins (){
    reg32_write_mask(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI,0x00000012,0x000000ff);
    reg32_write(SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2,0x12121212);
    reg32_write_mask(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1,0x12120000,0xffff0000);
}

void set_iomux_cspi3_via_dedicated_pins (){
    reg32_write_mask(SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI,0x00000012,0x000000ff);
    reg32_write_mask(SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD,0x12121200,0xffffff00);
}

void set_iomux_uart1_via_dedicated_pins (){
   reg32_write_mask(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x12120000,0xffff0000);
   reg32_write_mask(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1, 0x00001212,0x0000ffff);
}

void set_iomux_uart2_via_dedicated_pins (){
   reg32_write_mask(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, 0x00000012,0x000000ff);
   reg32_write_mask(SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE, 0x12121200,0xffffff00);
}

void set_iomux_sim_via_dedicated_pins (){
    reg32_write_mask(SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0,0x12121200,0xffffff00);
    reg32_write_mask(SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH,0x12121200,0xffffff00);
}

void set_iomux_sdhc1_via_dedicated_pins(){
    reg32_write_mask(SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0,0x00121212,0x00ffffff);
    reg32_write_mask(SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0,0x12121200,0xffffff00);
}

// ARM debug (event bus) functions reused from:
// /vobs/vb_tortola/tortola_designdir/verification/vectors/conn_fulluart_arm11pevntbus/stimulus/conn_fulluart_arm11pevntbus.c

void set_iomux_arm11pevntbus_via_audio_ports(){ //using audio ports 3-6
 // configure ARM EVNTBUS 0-15 for alt5 outputs
 reg32_write(SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3,0x60606060); // EVB0,EVB1,EVB2,EVB3
 reg32_write(SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4,0x60606060); // EVB4,EVB5,EVB6,EVB7
 reg32_write(SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5,0x60606060); // EVB8,EVB9,EVB10,EVB11
 reg32_write(SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6,0x60606060); // EVB12,EVB13,EVB14,EVB15
 return;
}

void set_iomux_arm11pevntbus_via_full_uart(){
   // Configure ARM EVNTBUS 0-19 for alt5 outputs
   // EVB0, EVB1, EVB2, EVB3
   reg32_write(SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3,0x60606060); 
   // EVB4, EVB5, EVB6, EVB7
   reg32_write(SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4,0x60606060); 
   // EVB8, EVB9, EVB10, EVB11
   reg32_write(SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5,0x60606060); 
   // EVB12, EVB13, EVB14, EVB15
   reg32_write(SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6,0x60606060); 
   // EVB16, EVB17
   reg32_write_mask(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x12126060, 0x0000ffff);  
   // EVB18, EVB19
   reg32_write_mask(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, 0x60601212, 0xffff0000);  
   return;
}

// ETM iomux functions reused from:
// /vobs/vb_tortola/tortola_designdir/verification/vectors/dbg_arm11p_etm_trace_port_config/stimulus/dbg_arm11p_etm_trace_port_config.c

void set_iomux_etm_via_etm_primery_24bit(){
    //TRACEDATA[03:00]: NFWE_B, NFRE_B, NFALE, NFCLE
    reg32_write(SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE,0x50505050);
    //TRACEDATA[06:04]: NFWP_B, NFCE_B, NFRB
    reg32_write_mask(SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15,0x505050ff,0xffffff00);
    //TRACEDATA[10:07]: STXD3, SRXD3, SCK3, SFS3
    reg32_write(SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3,0x50505050);
    //TRACEDATA[14:11]: STXD6, SRXD6, SCK6, SFS6
    reg32_write(SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6,0x50505050);
    //TRACEDATA[18:15]: CSPI1_MOSI, CSPI1_MISO, CSPI1_SS0, CSPI1_SS1
    reg32_write(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1,0x50505050);
    //TRACEDATA[19]: CSPI1_SS2
    reg32_write_mask(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI,0x50ffffff,0xff000000);
    //TRACEDATA[20]: USBH2_CLK
    reg32_write_mask(SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK,0xffffff50,0x000000ff);
    //TRACEDATA[23:21],TRACECTL: USBH2_DIR, USBH2_STP, USBH2_NXT, USBH2_DATA0
    reg32_write(SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0,0x50505050);
    //TRACECLK: USBH2_DATA1
    reg32_write_mask(SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2,0x50ffffff,0xff000000);
}

void set_iomux_etm_via_etm_primery_16bit(){
    //TRACEDATA[03:00]: NFWE_B, NFRE_B, NFALE, NFCLE
    reg32_write(SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE,0x50505050);
    //TRACEDATA[06:04]: NFWP_B, NFCE_B, NFRB
    reg32_write_mask(SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15,0x505050ff,0xffffff00);
    //TRACEDATA[10:07]: STXD3, SRXD3, SCK3, SFS3
    reg32_write(SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3,0x50505050);
    //TRACEDATA[14:11]: STXD6, SRXD6, SCK6, SFS6
    reg32_write(SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6,0x50505050);
    //TRACEDATA[15]: CSPI1_MOSI 
    reg32_write_mask(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1,0x50ffffff,0xff000000);
    //TRACECTL: USBH2_DATA0
    reg32_write_mask(SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0,0xffffff50,0x000000ff);
    //TRACECLK: USBH2_DATA1
    reg32_write_mask(SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2,0x50ffffff,0xff000000);
}

void set_iomux_etm_via_etm_primery_8bit(){
    //TRACEDATA[03:00]: NFWE_B, NFRE_B, NFALE, NFCLE
    reg32_write(SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE,0x50505050);
    //TRACEDATA[06:04]: NFWP_B, NFCE_B, NFRB
    reg32_write_mask(SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15,0x505050ff,0xffffff00);
    //TRACEDATA[07]: STXD3
    reg32_write_mask(SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3,0x50ffffff,0xff000000);
    //TRACECTL: USBH2_DATA0
    reg32_write_mask(SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0,0xffffff50,0x000000ff);
    //TRACECLK: USBH2_DATA1
    reg32_write_mask(SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2,0x50ffffff,0xff000000);
}

void set_iomux_etm_via_alternate_etm_8bit(){
    //TRACECLK, TRACEDATA[02:00]: KEY_ROW4, KEY_ROW5, KEY_ROW6, KEY_ROW7
    reg32_write(SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7,0x50505050);
    //TRACEDATA[03]: KEY_COL3
    reg32_write_mask(SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3,0xffffff50,0x000000ff);
    //TRACEDATA[07:04]: KEY_COL4, KEY_COL5, KEY_COL6, KEY_COL7
    reg32_write(SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7,0x50505050);
    //TRACECTL: KEY_ROW3
    reg32_write_mask(SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3,0xffffff50,0x000000ff);
    reg16_write_mask(KPP_KPCR,0x0000,0xf8f8); 
}

void set_iomux_etm_via_alternate_etm_16bit(){
    //TRACECLK, TRACEDATA[02:00]: KEY_ROW4, KEY_ROW5, KEY_ROW6, KEY_ROW7
    reg32_write(SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7,0x50505050);
    //TRACEDATA[03]: KEY_COL3
    reg32_write_mask(SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3,0xffffff50,0x000000ff);
    //TRACEDATA[07:04]: KEY_COL4, KEY_COL5, KEY_COL6, KEY_COL7
    reg32_write(SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7,0x50505050);
    //TRACECTL: KEY_ROW3
    reg32_write_mask(SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3,0xffffff50,0x000000ff);
    reg16_write_mask(KPP_KPCR,0x0000,0xf8f8); 
    //TRACEDATA[10:08]: SRXD3, SCK3, SFS3
    reg32_write_mask(SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3,0xff505050,0x00ffffff);
    //TRACEDATA[14:11]: STXD6, SRXD6, SCK6, SFS6
    reg32_write(SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6,0x50505050);
    //TRACEDATA[15]: CSPI1_MOSI 
    reg32_write_mask(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1,0x50ffffff,0xff000000);

}

// uart iomux functions reused from:
// /vobs/vb_tortola/tortola_projectdir/bin/arm_gcc/muc_software/hal_uart/include/uart_functions.h
// and anything over 4 bit was added

void set_iomux_uart1_via_full_uart(){
   reg32_write_mask(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,0x12120000,0xffff0000);
   reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1,0x12121212);
   reg32_write_mask(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1,0x00001212,0x0000ffff);
   reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1,0x12121212); 
}

void set_iomux_uart1_via_8wire_dce(){
   reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1,0x12121212);
   reg32_write_mask(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1,0x12120000,0xffff0000); 
   reg32_write_mask(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1,0x00001212,0x0000ffff); 
}

void set_iomux_uart1_via_8wire_dte(){
   reg32_write_mask(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1,0x00001212,0x0000ffff);
   reg32_write_mask(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1,0x12120000,0xffff0000);
   reg32_write_mask(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1,0x00001212,0x0000ffff); 
   reg32_write_mask(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,0x12120000,0xffff0000);      
}

void set_iomux_uart2_via_8wire_dce(){
   reg32_write_mask(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,0x00001212,0x0000ffff);
   reg32_write_mask(SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE,0x12121200,0xffffff00);
   reg32_write_mask(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1,0x00000040,0x000000ff);
   reg32_write_mask(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1,0x40400000,0xffff0000); 
}

void set_iomux_uart2_via_8wire_dte(){
   reg32_write_mask(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,0x24240012,0xffff00ff);
   reg32_write_mask(SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE,0x12121200,0xffffff00);
   reg32_write_mask(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1,0x00004024,0x0000ffff); 
}

void set_iomux_uart3_via_cspi1(){
   // UART3: ALT2
   reg32_write_mask(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1,
               0x38383800,0xffffff00);  // RXD,TXD,RTS,__
   reg32_write_mask(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI, 
               0x38000000,0xff000000);  // CTS,__,__,__
}

void set_iomux_uart3_via_cspi3(){
   reg32_write_mask(SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI,0x00000024,0x000000ff);
   reg32_write_mask(SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD,0x24242400,0xffffff00);
}

void set_iomux_uart4_via_usbotg(){
   // UART4: ALT
   reg32_write_mask(SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK,0x38000000,0xff000000 );    //RTS4,__,__,__
   reg32_write_mask(SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4,
               0x00003838,0x0000ffff);  // __,__,RXD,TXD
   reg32_write_mask(SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0,
               0x00000038,0x000000ff);  // __,__,__,CTS
}

void set_iomux_uart4_via_ata(){
   reg32_write_mask(SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0,0x00000024,0x000000ff);
   reg32_write_mask(SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK,0x24242400,0xffffff00);
}

void set_iomux_uart5_via_usbh2(){ 
   // UART5: ALT1
   reg32_write_mask(SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK,
               0x00000024,0x000000ff);  // __,__,__,RTS5
   reg32_write_mask(SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0,
               0x24242400,0xffffff00);  // RXD,TXD,CTS,__
}

void set_iomux_uart5_via_pcmcia(){
   reg32_write_mask(SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2,0x00383838,0x00ffffff);
   reg32_write_mask(SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE,0x38000000,0xff000000);
}

// cspi iomux functions reused from:
// /vobs/vb_tortola/tortola_projectdir/bin/arm_gcc/muc_software/hal_cspi/include/cspi_defines.h
// and then redited so that even their mother wouldn't recognize them

void set_iomux_cspi1_via_cspi_8bit (){ 
   set_iomux_cspi1_via_dedicated_pins;
   // put CSPI1'SS3 on CSPI2_SS1
   reg32_write_mask(SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1, 0x00000038,0x000000ff);
}

void set_iomux_cspi1_via_uart_8bit (){
    // SPI_RDY, SS3, -- , -- 
    reg32_write_mask(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x24240000 ,0xffff0000);
    //enable HW mode for MOSI, MISO, SS0, SS1, SS2
    reg32_write_mask(GP_REG,0xffffffff,0x00000004);
    // --, --, --, SCLK
    reg32_write_mask(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x00000024, 0x000000ff);
}

void set_iomux_cspi1_via_cspi_and_uart_8bit (){ 
   set_iomux_cspi1_via_dedicated_pins;
   // put CSPI1'SS3 on DCD_DCE1
   reg32_write_mask(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x00240000,0x00ff0000);
}

void set_iomux_cspi2_via_cspi_8bit (){
    set_iomux_cspi2_via_dedicated_pins;
    // put CSPI2'SS2 on CSPI1_SS1
    reg32_write_mask(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1, 0x00000038 ,0x000000ff);
}

void set_iomux_cspi3_via_cspi_8bit (){
    set_iomux_cspi3_via_dedicated_pins;
    // --, --, CSPI3'SS2, --
    reg32_write_mask(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1,0x00003800 ,0x0000ff00);
    // CSPI3'SS3, --, --, --
    reg32_write_mask(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI,0x38000000,0xff000000);
    // --, CSPI3'SS0, CSPI3'SS1, --
    reg32_write_mask(SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2,0x00242400,0x00ffff00);
}

//timer, i2c & memstick functions are not reused, but new and untested.

void set_iomux_mshc1_via_sdhc1(){
    reg32_write_mask(SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0,0x00242424,0x00ffffff);
    reg32_write_mask(SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0,0x24242400,0xffffff00);
}

void set_iomux_mshc2_via_pcmcia(){
    reg32_write_mask(SW_MUX_CTL_D2_D1_D0_PC_CD1_B,0x00000038,0x000000ff);
    reg32_write(SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON,0x38383838);
    reg32_write_mask(SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2,0x38000000,0xff000000);
}
   
//void set_iomux_epit1_via_gpt (){
//    config_pad_mode(COMPARE,alt4_out,func_in);
//}

//void set_iomux_epit2_via_gpt (){
//    config_pad_mode(COMPARE,alt5_out,func_in);
//}

//void set_iomux_gpt_via_alternate_setting (){
//    config_pad_mode(CAPTURE,func_out,alt2_in);
//    config_pad_mode(COMPARE,func_out,alt1_in);
//}

void set_iomux_i2c3_via_cspi2(){
    reg32_write_mask(SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2,0x00000024,0x000000ff);
    reg32_write_mask(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1,0x24000000,0xff000000);
}

void set_iomux_i2c2_via_cspi2(){
    reg32_write_mask(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI,0x00000024,0x000000ff);
    reg32_write_mask(SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2,0x24000000,0xff000000);
}

void set_iomux_i2c2_via_uart1(){
    reg32_write_mask(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,0x38380000,0xffff0000);
}