/*---------------------------------------------------------------------- * FILE: uart_defines.h *----------------------------------------------------------------------- * (C) Copyright 2001 Metrowerks Corp. * ALL RIGHTS RESERVED . * * THIS IS CONFIDENTIAL PROPRIETARY SOURCE CODE OF METROWERKS CORP. * * The copyright notice above does not evidence any * actual or intended publication of such source code. *----------------------------------------------------------------------- * * DESCRIPTION: UART loopback test on the TORTOLA (i.mx31) board * Common UARTs defines * * REFERENCES: * 1) TORTOLA spec * * HISTORY: * * 01 Feb 2005 zeldal Created * *--------------------------------------------------------------------------*/ #ifndef UART_DEFINES_H_ #define UART_DEFINES_H_ // ========================================================================= // // ------------------------ UART 1 specific defines ------------------------ // // ========================================================================= // #define SELECT_UART1 #ifdef SELECT_UART1 // // Register layout; inherits addresses and offsets from memory_map_defines.h // #define UART_REG_BASE UART1_BASE_ADDR #define UART_REG_URXD UART1_URXD_1 #define UART_REG_UTXD UART1_UTXD_1 #define UART_REG_UCR1 UART1_UCR1_1 #define UART_REG_UCR2 UART1_UCR2_1 #define UART_REG_UCR3 UART1_UCR3_1 #define UART_REG_UCR4 UART1_UCR4_1 #define UART_REG_UFCR UART1_UFCR_1 #define UART_REG_USR1 UART1_USR1_1 #define UART_REG_USR2 UART1_USR2_1 #define UART_REG_UESC UART1_UESC_1 #define UART_REG_UTIM UART1_UTIM_1 #define UART_REG_UBIR UART1_UBIR_1 #define UART_REG_UBMR UART1_UBMR_1 #define UART_REG_UBRC UART1_UBRC_1 #define UART_REG_ONEMS UART1_ONEMS_1 #define UART_REG_UTS UART1_UTS_1 #define UART_TX_INT_ROUTINE \ UART1_TX_INT_ROUTINE #define UART_RX_INT_ROUTINE \ UART1_RX_INT_ROUTINE #define UART_MINT_INT_ROUTINE \ UART1_MINT_INT_ROUTINE #define UART_ANDED_INT_ROUTINE \ UART1_ANDED_INT_ROUTINE // Interrupt numbers assigned to this UART instance #define UART_TX_INTNUM ___NO_TX_INT_FOR_UART1___ #define UART_RX_INTNUM ___NO_RX_INT_FOR_UART1___ #define UART_MINT_INTNUM ___NO_MINT_INT_FOR_UART1___ #define UART_AND3_INTNUM 45 /* Disables all interrupts related to UART1: 45 Use comma to make sure this is a single statement ... */ #define DISABLE_ALL_UART_IRQS \ reg32write(AVIC_INTDISNUM, UART_AND3_INTNUM) #endif /* SELECT_UART1 */ // ========================================================================= // // ------------------------ UART 2 specific defines ------------------------ // // ========================================================================= // #ifdef SELECT_UART2 // // Register layout; inherits addresses and offsets from memory_map_defines.h // #define UART_REG_BASE UART2_BASE_ADDR #define UART_REG_URXD UART2_URXD_2 #define UART_REG_UTXD UART2_UTXD_2 #define UART_REG_UCR1 UART2_UCR1_2 #define UART_REG_UCR2 UART2_UCR2_2 #define UART_REG_UCR3 UART2_UCR3_2 #define UART_REG_UCR4 UART2_UCR4_2 #define UART_REG_UFCR UART2_UFCR_2 #define UART_REG_USR1 UART2_USR1_2 #define UART_REG_USR2 UART2_USR2_2 #define UART_REG_UESC UART2_UESC_2 #define UART_REG_UTIM UART2_UTIM_2 #define UART_REG_UBIR UART2_UBIR_2 #define UART_REG_UBMR UART2_UBMR_2 #define UART_REG_UBRC UART2_UBRC_2 #define UART_REG_ONEMS UART2_ONEMS_2 #define UART_REG_UTS UART2_UTS_2 #define UART_TX_INT_ROUTINE \ UART2_TX_INT_ROUTINE #define UART_RX_INT_ROUTINE \ UART2_RX_INT_ROUTINE #define UART_MINT_INT_ROUTINE \ UART2_MINT_INT_ROUTINE #define UART_ANDED_INT_ROUTINE \ UART2_ANDED_INT_ROUTINE // Interrupt numbers assigned to this UART instance #define UART_TX_INTNUM ___NO_TX_INT_FOR_UART2___ #define UART_RX_INTNUM ___NO_RX_INT_FOR_UART2___ #define UART_MINT_INTNUM ___NO_MINT_INT_FOR_UART2___ #define UART_AND3_INTNUM 32 /* Disables all interrupts related to UART2: 32 Use comma to make sure this is a single statement ... */ #define DISABLE_ALL_UART_IRQS \ reg32write(AVIC_INTDISNUM, UART_AND3_INTNUM) #endif /* SELECT_UART2 */ // ========================================================================= // // ------------------------ UART 3 specific defines ------------------------ // // ========================================================================= // #ifdef SELECT_UART3 // // Register layout; inherits addresses and offsets from memory_map_defines.h // #define UART_REG_BASE UART3_BASE_ADDR #define UART_REG_URXD UART3_URXD_3 #define UART_REG_UTXD UART3_UTXD_3 #define UART_REG_UCR1 UART3_UCR1_3 #define UART_REG_UCR2 UART3_UCR2_3 #define UART_REG_UCR3 UART3_UCR3_3 #define UART_REG_UCR4 UART3_UCR4_3 #define UART_REG_UFCR UART3_UFCR_3 #define UART_REG_USR1 UART3_USR1_3 #define UART_REG_USR2 UART3_USR2_3 #define UART_REG_UESC UART3_UESC_3 #define UART_REG_UTIM UART3_UTIM_3 #define UART_REG_UBIR UART3_UBIR_3 #define UART_REG_UBMR UART3_UBMR_3 #define UART_REG_UBRC UART3_UBRC_3 #define UART_REG_ONEMS UART3_ONEMS_3 #define UART_REG_UTS UART3_UTS_3 #define UART_TX_INT_ROUTINE \ UART3_TX_INT_ROUTINE #define UART_RX_INT_ROUTINE \ UART3_RX_INT_ROUTINE #define UART_MINT_INT_ROUTINE \ UART3_MINT_INT_ROUTINE #define UART_ANDED_INT_ROUTINE \ UART3_ANDED_INT_ROUTINE // Interrupt numbers assigned to this UART instance #define UART_TX_INTNUM ___NO_TX_INT_FOR_UART3___ #define UART_RX_INTNUM ___NO_RX_INT_FOR_UART3___ #define UART_MINT_INTNUM ___NO_MINT_INT_FOR_UART3___ #define UART_AND3_INTNUM 18 /* Disables all interrupts related to UART3: 18 Use comma to make sure this is a single statement ... */ #define DISABLE_ALL_UART_IRQS \ reg32write(AVIC_INTDISNUM, UART_AND3_INTNUM) #endif /* SELECT_UART3 */ // ========================================================================= // // ------------------------ UART 4 specific defines ------------------------ // // ========================================================================= // #ifdef SELECT_UART4 // // Register layout; inherits addresses and offsets from memory_map_defines.h // #define UART_REG_BASE UART4_BASE_ADDR #define UART_REG_URXD UART4_URXD_4 #define UART_REG_UTXD UART4_UTXD_4 #define UART_REG_UCR1 UART4_UCR1_4 #define UART_REG_UCR2 UART4_UCR2_4 #define UART_REG_UCR3 UART4_UCR3_4 #define UART_REG_UCR4 UART4_UCR4_4 #define UART_REG_UFCR UART4_UFCR_4 #define UART_REG_USR1 UART4_USR1_4 #define UART_REG_USR2 UART4_USR2_4 #define UART_REG_UESC UART4_UESC_4 #define UART_REG_UTIM UART4_UTIM_4 #define UART_REG_UBIR UART4_UBIR_4 #define UART_REG_UBMR UART4_UBMR_4 #define UART_REG_UBRC UART4_UBRC_4 #define UART_REG_ONEMS UART4_ONEMS_4 #define UART_REG_UTS UART4_UTS_4 #define UART_USE_ANDED_IRQS #define UART_TX_INT_ROUTINE \ ___NO_TX_INT_ROUTINE_FOR_UART4___ #define UART_RX_INT_ROUTINE \ ___NO_RX_INT_ROUTINE_FOR_UART4___ #define UART_MINT_INT_ROUTINE \ ___NO_MINT_INT_ROUTINE_FOR_UART4___ #define UART_ANDED_INT_ROUTINE \ UART4_ANDED_INT_ROUTINE // Interrupt numbers assigned to this UART instance #define UART_TX_INTNUM ___NO_TX_INT_FOR_UART4___ #define UART_RX_INTNUM ___NO_RX_INT_FOR_UART4___ #define UART_MINT_INTNUM ___NO_MINT_INT_FOR_UART4___ #define UART_AND3_INTNUM 46 /* Disables all interrupts related to UART4: 46 ORed(tx, rx, mint) Use comma to make sure this is a single statement ... */ #define DISABLE_ALL_UART_IRQS \ reg32write(AVIC_INTDISNUM, UART_AND3_INTNUM) #endif /* SELECT_UART4 */ // ========================================================================= // // ------------------------ UART 5 specific defines ------------------------ // // ========================================================================= // #ifdef SELECT_UART5 // // Register layout; inherits addresses and offsets from memory_map_defines.h // #define UART_REG_BASE UART5_BASE_ADDR #define UART_REG_URXD UART5_URXD_5 #define UART_REG_UTXD UART5_UTXD_5 #define UART_REG_UCR1 UART5_UCR1_5 #define UART_REG_UCR2 UART5_UCR2_5 #define UART_REG_UCR3 UART5_UCR3_5 #define UART_REG_UCR4 UART5_UCR4_5 #define UART_REG_UFCR UART5_UFCR_5 #define UART_REG_USR1 UART5_USR1_5 #define UART_REG_USR2 UART5_USR2_5 #define UART_REG_UESC UART5_UESC_5 #define UART_REG_UTIM UART5_UTIM_5 #define UART_REG_UBIR UART5_UBIR_5 #define UART_REG_UBMR UART5_UBMR_5 #define UART_REG_UBRC UART5_UBRC_5 #define UART_REG_ONEMS UART5_ONEMS_5 #define UART_REG_UTS UART5_UTS_5 #define UART_USE_ANDED_IRQS #define UART_TX_INT_ROUTINE \ ___NO_TX_INT_ROUTINE_FOR_UART5___ #define UART_RX_INT_ROUTINE \ ___NO_RX_INT_ROUTINE_FOR_UART5___ #define UART_MINT_INT_ROUTINE \ ___NO_MINT_INT_ROUTINE_FOR_UART5___ #define UART_ANDED_INT_ROUTINE \ UART5_ANDED_INT_ROUTINE // Interrupt numbers assigned to this UART instance #define UART_TX_INTNUM ___NO_TX_INT_FOR_UART5___ #define UART_RX_INTNUM ___NO_RX_INT_FOR_UART5___ #define UART_MINT_INTNUM ___NO_MINT_INT_FOR_UART5___ #define UART_AND3_INTNUM 47 /* Disables all interrupts related to UART5: 47 ORed(tx, rx, mint) Use comma to make sure this is a single statement ... */ #define DISABLE_ALL_UART_IRQS \ reg32write(AVIC_INTDISNUM, UART_AND3_INTNUM) #endif /* SELECT_UART5 */ // ========================================================================= // // -------------------------- UART register layout ------------------------- // // ========================================================================= // /*----------------------------------------------------------------------------*\ Bit masks used to describe the registers of the UART, there are four masks - ... _RESETVAL - Expected register value after hardware reset - ... _READONLY - A bit set within this mask denotes a read-only bit - ... _FIXED0 - A bit set within this mask denotes a reserved bit ('0') - ... _FIXED1 - A bit set within this mask denotes a reserved bit ('1') - ... _NOTTOUCH - A bit set within this mask denotes that the corresponding bit has side effects and should not be exercised. - ... _DISABLES - Defines the value to be used for bits with side effects \*----------------------------------------------------------------------------*/ /* URXD */ #define UART_REG_URXD_RESETVAL 0x8000 #define UART_REG_URXD_READONLY 0x7CFF #define UART_REG_URXD_FIXED0 0x0300 #define UART_REG_URXD_FIXED1 0x8000 #define UART_REG_URXD_NOTTOUCH 0x0000 #define UART_REG_URXD_DISABLES 0x0000 /* UTXD */ #define UART_REG_UTXD_RESETVAL 0x0000 #define UART_REG_UTXD_READONLY 0x0000 #define UART_REG_UTXD_FIXED0 0xFF00 #define UART_REG_UTXD_FIXED1 0x0000 #define UART_REG_UTXD_NOTTOUCH 0x0000 #define UART_REG_UTXD_DISABLES 0x0000 /* UCR1 */ #define UART_REG_UCR1_RESETVAL 0x0000 #define UART_REG_UCR1_READONLY 0x0000 // Change requested by kent mou on 15-07-04 #define UART_REG_UCR1_FIXED0 0x0000 #define UART_REG_UCR1_FIXED1 0x0000 #define UART_REG_UCR1_NOTTOUCH 0x0000 #define UART_REG_UCR1_DISABLES 0x0000 /* UCR2 */ #define UART_REG_UCR2_RESETVAL 0x0001 #define UART_REG_UCR2_READONLY 0x0001 #define UART_REG_UCR2_FIXED0 0x0000 #define UART_REG_UCR2_FIXED1 0x0000 #define UART_REG_UCR2_NOTTOUCH 0x0001 #define UART_REG_UCR2_DISABLES 0x0001 /* Better don't request a SW reset */ /* UCR3 */ #define UART_REG_UCR3_RESETVAL 0x0700 #define UART_REG_UCR3_READONLY 0x0000 #define UART_REG_UCR3_FIXED0 0x0000 #define UART_REG_UCR3_FIXED1 0x0000 #define UART_REG_UCR3_NOTTOUCH 0x0000 #define UART_REG_UCR3_DISABLES 0x0000 /* UCR4 */ #define UART_REG_UCR4_RESETVAL 0x8000 #define UART_REG_UCR4_READONLY 0x0000 // Change requested by kent mou on 15-07-04 #define UART_REG_UCR4_FIXED0 0x0000 #define UART_REG_UCR4_FIXED1 0x0000 #define UART_REG_UCR4_NOTTOUCH 0x0000 #define UART_REG_UCR4_DISABLES 0x0000 /* UFCR */ #define UART_REG_UFCR_RESETVAL 0x0801 #define UART_REG_UFCR_READONLY 0x0000 #define UART_REG_UFCR_FIXED0 0x0000 #define UART_REG_UFCR_FIXED1 0x0000 #define UART_REG_UFCR_NOTTOUCH 0x0000 #define UART_REG_UFCR_DISABLES 0x0000 /* USR1 */ #define UART_REG_USR1_RESETVAL 0x2040 #define UART_REG_USR1_READONLY 0xFFF0 #define UART_REG_USR1_FIXED0 0x000F #define UART_REG_USR1_FIXED1 0x0000 #define UART_REG_USR1_NOTTOUCH 0x0000 #define UART_REG_USR1_DISABLES 0x9D30 /* Do not toggle w1c bits */ /* USR2 */ #define UART_REG_USR2_RESETVAL 0x4008 #define UART_REG_USR2_READONLY 0xFFFF #define UART_REG_USR2_FIXED0 0x0000 #define UART_REG_USR2_FIXED1 0x0000 #define UART_REG_USR2_NOTTOUCH 0x0000 #define UART_REG_USR2_DISABLES 0xBDD6 /* Do not toggle w1c bits */ /* UESC */ #define UART_REG_UESC_RESETVAL 0x002B #define UART_REG_UESC_READONLY 0x0000 #define UART_REG_UESC_FIXED0 0xFF00 #define UART_REG_UESC_FIXED1 0x0000 #define UART_REG_UESC_NOTTOUCH 0x0000 #define UART_REG_UESC_DISABLES 0x0000 /* UTIM */ #define UART_REG_UTIM_RESETVAL 0x0000 #define UART_REG_UTIM_READONLY 0x0000 #define UART_REG_UTIM_FIXED0 0xF000 #define UART_REG_UTIM_FIXED1 0x0000 #define UART_REG_UTIM_NOTTOUCH 0x0000 #define UART_REG_UTIM_DISABLES 0x0000 /* UBIR */ #define UART_REG_UBIR_RESETVAL 0x0000 #define UART_REG_UBIR_READONLY 0x0000 #define UART_REG_UBIR_FIXED0 0x0000 #define UART_REG_UBIR_FIXED1 0x0000 #define UART_REG_UBIR_NOTTOUCH 0x0000 #define UART_REG_UBIR_DISABLES 0x0000 /* UBMR */ #define UART_REG_UBMR_RESETVAL 0x0000 #define UART_REG_UBMR_READONLY 0x0000 #define UART_REG_UBMR_FIXED0 0x0000 #define UART_REG_UBMR_FIXED1 0x0000 #define UART_REG_UBMR_NOTTOUCH 0x0000 #define UART_REG_UBMR_DISABLES 0x0000 /* UBRC */ #define UART_REG_UBRC_RESETVAL 0x0004 #define UART_REG_UBRC_READONLY 0xFFFF #define UART_REG_UBRC_FIXED0 0x0000 #define UART_REG_UBRC_FIXED1 0x0000 #define UART_REG_UBRC_NOTTOUCH 0x0000 #define UART_REG_UBRC_DISABLES 0x0000 /* ONEMS */ #define UART_REG_ONEMS_RESETVAL 0x0000 #define UART_REG_ONEMS_READONLY 0x0000 #define UART_REG_ONEMS_FIXED0 0x0000 #define UART_REG_ONEMS_FIXED1 0x0000 #define UART_REG_ONEMS_NOTTOUCH 0x0000 #define UART_REG_ONEMS_DISABLES 0x0000 /* UTS */ #define UART_REG_UTS_RESETVAL 0x0060 #define UART_REG_UTS_READONLY 0x0079 #define UART_REG_UTS_FIXED0 0xC186 #define UART_REG_UTS_FIXED1 0x0000 #define UART_REG_UTS_NOTTOUCH 0x0000 #define UART_REG_UTS_DISABLES 0x0000 // ========================================================================= // // -------------------------- UART register content ------------------------ // // ========================================================================= // /*----------------------------------------------------------------------------*\ UCR1 - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define UART_UCR1_ICD_BP 10 #define UART_UCR1_ICD_SZ 0x3 #define UART_UCR1_ADEN_BP 15 #define UART_UCR1_ADEN 0x8000 #define UART_UCR1_ADBR_BP 14 #define UART_UCR1_ADBR 0x4000 #define UART_UCR1_TRDYEN_BP 13 #define UART_UCR1_TRDYEN 0x2000 #define UART_UCR1_IDEN_BP 12 #define UART_UCR1_IDEN 0x1000 #define UART_UCR1_RRDYEN_BP 9 #define UART_UCR1_RRDYEN 0x0200 #define UART_UCR1_RXDMAEN_BP 8 #define UART_UCR1_RXDMAEN 0x0100 #define UART_UCR1_IREN_BP 7 #define UART_UCR1_IREN 0x0080 #define UART_UCR1_TXMPTYEN_BP 6 #define UART_UCR1_TXMPTYEN 0x0040 #define UART_UCR1_RTSDEN_BP 5 #define UART_UCR1_RTSDEN 0x0020 #define UART_UCR1_SNDBRK_BP 4 #define UART_UCR1_SNDBRK 0x0010 #define UART_UCR1_TXDMAEN_BP 3 #define UART_UCR1_TXDMAEN 0x0008 #define UART_UCR1_DOZE_BP 1 #define UART_UCR1_DOZE 0x0002 #define UART_UCR1_UARTEN_BP 0 #define UART_UCR1_UARTEN 0x0001 /*----------------------------------------------------------------------------*\ UCR2 - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define UART_UCR1_RTEC_BP 9 #define UART_UCR1_RTEC_SZ 0x3 #define UART_UCR2_ESCI_BP 15 #define UART_UCR2_ESCI 0x8000 #define UART_UCR2_IRTS_BP 14 #define UART_UCR2_IRTS 0x4000 #define UART_UCR2_CTSC_BP 13 #define UART_UCR2_CTSC 0x2000 #define UART_UCR2_CTS_BP 12 #define UART_UCR2_CTS 0x1000 #define UART_UCR2_ESCEN_BP 11 #define UART_UCR2_ESCEN 0x0800 #define UART_UCR2_PREN_BP 8 #define UART_UCR2_PREN 0x0100 #define UART_UCR2_PROE_BP 7 #define UART_UCR2_PROE 0x0080 #define UART_UCR2_STPB_BP 6 #define UART_UCR2_STPB 0x0040 #define UART_UCR2_WS_BP 5 #define UART_UCR2_WS 0x0020 #define UART_UCR2_RTSEN_BP 4 #define UART_UCR2_RTSEN 0x0010 #define UART_UCR2_ATEN_BP 3 #define UART_UCR2_ATEN 0x0008 #define UART_UCR2_TXEN_BP 2 #define UART_UCR2_TXEN 0x0004 #define UART_UCR2_RXEN_BP 1 #define UART_UCR2_RXEN 0x0002 #define UART_UCR2_SRSTb_BP 0 #define UART_UCR2_SRSTb 0x0001 /*----------------------------------------------------------------------------*\ UCR3 - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define UART_UCR1_DPEC_BP 14 #define UART_UCR1_DPEC_SZ 0x3 #define UART_UCR3_DTREN_BP 13 #define UART_UCR3_DTREN 0x2000 #define UART_UCR3_PARERREN_BP 12 #define UART_UCR3_PARERREN 0x1000 #define UART_UCR3_FRAERREN_BP 11 #define UART_UCR3_FRAERREN 0x0800 #define UART_UCR3_DSR_BP 10 #define UART_UCR3_DSR 0x0400 #define UART_UCR3_DCD_BP 9 #define UART_UCR3_DCD 0x0200 #define UART_UCR3_RI_BP 8 #define UART_UCR3_RI 0x0100 #define UART_UCR3_ADNIMP_BP 7 #define UART_UCR3_ADNIMP 0x0080 #define UART_UCR3_RXDSEN_BP 6 #define UART_UCR3_RXDSEN 0x0040 #define UART_UCR3_AIRINTEN_BP 5 #define UART_UCR3_AIRINTEN 0x0020 #define UART_UCR3_AWAKEN_BP 4 #define UART_UCR3_AWAKEN 0x0010 #define UART_UCR3_DTRDEN_BP 3 #define UART_UCR3_DTRDEN 0x0008 #define UART_UCR3_RXDMUXSEL_BP 2 #define UART_UCR3_RXDMUXSEL 0x0004 #define UART_UCR3_INVT_BP 1 #define UART_UCR3_INVT 0x0002 #define UART_UCR3_ACIEN_BP 0 #define UART_UCR3_ACIEN 0x0001 /*----------------------------------------------------------------------------*\ UCR4 - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define UART_UCR4_CTSTL_BP 10 #define UART_UCR4_CTSTL_SZ 0x3F #define UART_UCR4_INVR_BP 9 #define UART_UCR4_INVR 0x0200 #define UART_UCR4_ENIRI_BP 8 #define UART_UCR4_ENIRI 0x0100 #define UART_UCR4_WKEN_BP 7 #define UART_UCR4_WKEN 0x0080 #define UART_UCR4_IRSC_BP 5 #define UART_UCR4_IRSC 0x0020 #define UART_UCR4_LBBYP_BP 4 #define UART_UCR4_LBBYP 0x0010 #define UART_UCR4_TCEN_BP 3 #define UART_UCR4_TCEN 0x0008 #define UART_UCR4_BKEN_BP 2 #define UART_UCR4_BKEN 0x0004 #define UART_UCR4_OREN_BP 1 #define UART_UCR4_OREN 0x0002 #define UART_UCR4_DREN_BP 0 #define UART_UCR4_DREN 0x0001 /*----------------------------------------------------------------------------*\ UFCR - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define UART_UFCR_TXTL_BP 10 #define UART_UFCR_TXTL_SZ 0x3F #define UART_UFCR_RFDIV_BP 7 #define UART_UFCR_RFDIV_SZ 0x7 #define UART_UFCR_DCEDTE 0x0040 #define UART_UFCR_RXTL_BP 0 #define UART_UFCR_RXTL_SZ 0x3F /*----------------------------------------------------------------------------*\ USR1 - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define UART_USR1_PARITYERR_BP 15 #define UART_USR1_PARITYERR 0x8000 #define UART_USR1_RTSS_BP 14 #define UART_USR1_RTSS 0x4000 #define UART_USR1_TRDY_BP 13 #define UART_USR1_TRDY 0x2000 #define UART_USR1_RTSD_BP 12 #define UART_USR1_RTSD 0x1000 #define UART_USR1_ESCF_BP 11 #define UART_USR1_ESCF 0x0800 #define UART_USR1_FRAMERR_BP 10 #define UART_USR1_FRAMERR 0x0400 #define UART_USR1_RRDY_BP 9 #define UART_USR1_RRDY 0x0200 #define UART_USR1_AGTIM_BP 8 #define UART_USR1_AGTIM 0x0100 #define UART_USR1_DTRD_BP 7 #define UART_USR1_DTRD 0x0080 #define UART_USR1_RXDS_BP 6 #define UART_USR1_RXDS 0x0040 #define UART_USR1_AIRINT_BP 5 #define UART_USR1_AIRINT 0x0020 #define UART_USR1_AWAKE_BP 4 #define UART_USR1_AWAKE 0x0010 /*----------------------------------------------------------------------------*\ USR2 - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define UART_USR2_ADET_BP 15 #define UART_USR2_ADET 0x8000 #define UART_USR2_TXFE_BP 14 #define UART_USR2_TXFE 0x4000 #define UART_USR2_DTRF_BP 13 #define UART_USR2_DTRF 0x2000 #define UART_USR2_IDLE_BP 12 #define UART_USR2_IDLE 0x1000 #define UART_USR2_ACST_BP 11 #define UART_USR2_ACST 0x0800 #define UART_USR2_RIDELT_BP 10 #define UART_USR2_RIDELT 0x0400 #define UART_USR2_RIIN_BP 9 #define UART_USR2_RIIN 0x0200 #define UART_USR2_IRINT_BP 8 #define UART_USR2_IRINT 0x0100 #define UART_USR2_WAKE_BP 7 #define UART_USR2_WAKE 0x0080 #define UART_USR2_DCDDELT_BP 6 #define UART_USR2_DCDDELT 0x0040 #define UART_USR2_DCDIN_BP 5 #define UART_USR2_DCDIN 0x0020 #define UART_USR2_RTSF_BP 4 #define UART_USR2_RTSF 0x0010 #define UART_USR2_TXDC_BP 3 #define UART_USR2_TXDC 0x0008 #define UART_USR2_BRCD_BP 2 #define UART_USR2_BRCD 0x0004 #define UART_USR2_ORE_BP 1 #define UART_USR2_ORE 0x0002 #define UART_USR2_RDR_BP 0 #define UART_USR2_RDR 0x0001 /*----------------------------------------------------------------------------*\ UTS - Bit positions, bit masks and field selection masks \*----------------------------------------------------------------------------*/ #define UART_UTS_FRCPERR_BP 13 #define UART_UTS_FRCPERR 0x2000 #define UART_UTS_LOOP_BP 12 #define UART_UTS_LOOP 0x1000 #define UART_UTS_DBGEN_BP 11 #define UART_UTS_DBGEN 0x0800 #define UART_UTS_LOOPIR_BP 10 #define UART_UTS_LOOPIR 0x0400 #define UART_UTS_RDXDBG_BP 9 #define UART_UTS_RDXDBG 0x0200 #define UART_UTS_TXEMPTY_BP 6 #define UART_UTS_TXEMPTY 0x0040 #define UART_UTS_RXEMPTY_BP 5 #define UART_UTS_RXEMPTY 0x0020 #define UART_UTS_TXFULL_BP 4 #define UART_UTS_TXFULL 0x0010 #define UART_UTS_RXFULL_BP 3 #define UART_UTS_RXFULL 0x0008 #define UART_UTS_SOFTRST_BP 0 #define UART_UTS_SOFTRST 0x0001 #endif /* UART_DEFINES_H_ */