/*---------------------------------------------------------------------- * FILE: uart_functions.c *----------------------------------------------------------------------- * (C) Copyright 2001 Metrowerks Corp. * ALL RIGHTS RESERVED . * * THIS IS CONFIDENTIAL PROPRIETARY SOURCE CODE OF METROWERKS CORP. * * The copyright notice above does not evidence any * actual or intended publication of such source code. *----------------------------------------------------------------------- * * DESCRIPTION: UARTs loopback test on the TORTOLA (i.mx31) board * Common UARTs functions * * REFERENCES: * 1) TORTOLA spec * * HISTORY: * * 01 Feb 2005 zeldal Created * *--------------------------------------------------------------------------*/ #include //#ifndef UART_FUNCTIONS_H__ //#define UART_FUNCTIONS_H__ /* Prevent multiple inclusions */ #include "uart_defines.h" #include "uart_functions.h" #include "tortola_memory_map_defines.h" //#include "tstsrv.h" #include "verif_common.h" /* Common functions of verification environment */ #include "functions.h" #define UART_REST_TIMEOUT 0xf00000 void UART_WRITE_4BYTES( UINT08 Val1, UINT08 Val2, UINT08 Val3, UINT08 Val4 ); // ========================================================================= // // --- UART control register setup - standard version (defaults) ----------- // // ========================================================================= // /*! Default settings for the UART; defined as follows: - enable/disable the UART (dependent on param), enable in DOZE state - enables the transmitter and the receiver, enable low power features - 8 bit character length, two stop bits, odd parity - input pin is ipp_uart_rxd_mux for serial and IR interfaces - no automatic baud rate detection, enables related new features - disables the infrared interface, active low transmission & reception - disables the escape sequence detection logic - disables all DMA request - disables all interrupts - default settings for a) idle condition (4 frames), don't send a BREAK character b) RTS triggers on positive edges only, corresponding pin is ignored c) CTS ipp_uart_cts_b controlled by receiver, CTS trigger level = 32 d) DSR/DTR output pin is logic zero, detect rising edges only e) DCE mode only: ipp_uart_ri_dce_o_b & ipp_uart_dcd_dce_o_b are 0 */ int UART_RESET( int Enable ) { UART_REGSIZE RegValue; int rc = 0; int TimeOUT = UART_REST_TIMEOUT; /* UCR1 settings: - no automatic baud rate detection (ADBR=0), disable related interrupt (ADEN=0) - detect an idle condition when the RXD is idle for more than 4 frames (ICD=00), disable the related interrupt (IDEN=0) - do not send a BREAK character (SNDBRK=0) - disable the infrared interface (IREN=0) - disable DMA request related to the transmitter (TXDMAEN=0) and the receiver (RXDMAEN) - disable the interrupts related to RRDY (RRDYEN=0), TRDY (TRDYEN=0), TXFE (TXMPTYEN=0), and RTSD (TRSDEN=0) */ RegValue = 0x0000; if (Enable) RegValue |= UART_UCR1_UARTEN; uart_write(UCR1, RegValue); /* UCR2 settings: - disables the interrupt related to RTSF (UCR2'RTSEN=0) - disables the interrupt related to AGTIM (UCR2'ATEN=0) - disables the interrupt related to ESCF (UCR2'ESCI=0) - disable escape sequence detection logic (UCR2'ESCEN=0) - enable the parity generator in the transmitter and the parity checker in the receiver (UCR2'PREN=1), generate odd parity (UCR2'PROE=1) - enables the receiver (UCR2'RXEN=1) - enables the transmitter (UCR2'TXEN=1) - ignores the RTS pin (UCR2'IRTS=1) - the ipp_uart_cts_b pin is controlled by the receiver (UCR2'CTSC=1), UCR2'CTS bit has no function due to this - RTS interrupt is triggered on a positive edge only (UCR2'RTEC=00) - transmit one stop bits (UCR2'STPB=0) - 8 bit transmit and receive character length (UCR2'WS=1) - does not perform a software reset (UCR2'SRSTb=1) */ uart_write(UCR2, /* 0x61E6 */ UART_UCR2_IRTS | UART_UCR2_CTSC | UART_UCR2_PREN | UART_UCR2_PROE | UART_UCR2_WS | UART_UCR2_TXEN | UART_UCR2_RXEN | UART_UCR2_SRSTb); /* UCR3 settings: - enables new features of autobaud detection (UCR3'ADNIMP=0) - disables the interrupt related to ACST (UCR3'ACIEN=0) - disables the interrupt related to PARITYERR (UCR3'PARERREN=0) - disables the interrupt related to FRAMERR (UCR3'FRAERREN=0) - disables the interrupt related to AIRINT (UCR3'AIRINTEN=0) - disables the interrupt related to AWAKE (UCR3'AWAKEN=0) - disables the interrupt related to DTRF (UCR3'DTREN=0) - disables the interrupt related to DTRD (UCR3'DTRDEN=0) - detect a DTR/DSR an rising edges only (UCR3'DPEC=00), [DTREN disabled] - DSR/DTR output pin is logic zero (UCR3'DSR=0) - Infrared transmission is active low (UCR3'INVT=0) - Input pin is ipp_uart_rxd_mux for serial and IR interfaces (UCR3'RDXMUXSEL=1) - RIDELT interrupt disabled (DTE mode) or ipp_uart_ri_dce_o_b pin is logic zero (DCE mode) (UCR3'RI=0) - DCDDELT interrupt disabled (DTE mode) or ipp_uart_dcd_dce_o_b pin is logic zero (DCE mode) (UCR3'DCD=0) */ uart_write(UCR3, /* 0x0004 */ UART_UCR3_RXDMUXSEL); // always use ipp_uart_rxd_mux /* UCR4 settings: - CTS trigger level is 32 characters (CTSTL = 32) - expect an active low (inverted) infrared reception (UCR4'INVR=0) - disables the interrupt related to IRINT (UCR4'ENIRI=0) - disables the interrupt related to WAKE (UCR4'WKEN=0) - disables the interrupt related to TXDC (UCR4'TCEN=0) - disables the interrupt related to BRCD (UCR4'BKEN=0) - disables the interrupt related to ORE (UCR4'OREN=0) - disables the interrupt related to RDR (UCR4'DREN=0) - enable low power features (LPBYP=0) - vote logic uses the sampling clock; no special infrared case (IRSC=0) */ uart_write(UCR4, /* 0x8000 */ (32 << UART_UCR4_CTSTL_BP) ); // In cases where a software reset is pending (NOT started above), it makes // sense to wait until this is finished. The bit SOFTRST in UTS indicates // whether a software reset is still active. do { RegValue = uart_read(UTS); } while ((RegValue & UART_UTS_SOFTRST) != 0 && TimeOUT-- > 0); if (TimeOUT <= 0) rc = 1; return rc; } // UART_RESET() /*! Performs a software reset; has to wait for 4 clock cycles of CKIH. Since CKIH is a slow clock, it is good to check for the software reset to be finished before exiting this function. The SOFTRST bit in UTS indicates whether the software reset is still running. */ int UART_SWRESET( void ) { int TimeOUT = UART_REST_TIMEOUT; UART_REGSIZE RegValue; int rc = 0; uart_clrbit(UCR2, UART_UCR2_SRSTb_BP); do // Make sure to wait, in case a software reset is pending { RegValue = uart_read(UTS); } while ((RegValue & UART_UTS_SOFTRST) != 0 && TimeOUT-- > 0); if (TimeOUT <= 0) rc = 1; return rc; } // ========================================================================= // // --- UART control register setup - standard version (defaults) ----------- // // ========================================================================= // // THESE ARE DEPRECATED VERSIONS -- DO NOT USE, just use the above and derive #if 0 /* . UART_SOFTWARE_RESET0( ) -> UART_RESET(0) . UART_SOFTWARE_RESET1( ) -> UART_RESET(0), setbit UCR1 EN . UART_SOFTWARE_RESET2( ) -> UART_RESET(0), clrbit UCR2 IRTS // 0x21E6 . UART_SOFTWARE_RESET3( ) -> UART_RESET(0), clrbit UCR2 STPB // 0x61A6 . UART_SOFTWARE_RESET4( ) -> UART_RESET(0), clrbit UCR2 CTSC // 0x41E6 . UART_SOFTWARE_RESET5( ) -> UART_RESET(0), setbit UCR1 EN (same as 1) . UART_SOFTWARE_RESET6( ) -> UART_RESET(0), setbit UCR1 EN, clrbit UCR2 ESCEN setbit UCR1 RRDYEN . UART_SOFTWARE_RESET7( ) -> UART_RESET(0), clrbit UCR2 IRTS, setbit UCR1 EN . UART_SOFTWARE_RESET8( ) -> UART_RESET(0), setbit UCR1 EN, RRDYEN . UART_SOFTWARE_RESET9( ) -> UART_RESET(0), setbit UCR1 EN (same as 1) . UART_SOFTWARE_RESET10( ) -> UART_RESET(0), setbit UCR1 EN, UCR4 WKEN */ #endif // ========================================================================= // // --- Access to the RxFIFO and TxFIFO (permits byte transfers) ------------ // // ========================================================================= // UINT08 UART_READ_BYTE( void ) { return (uart_read(URXD)); } void UART_WRITE_BYTE( UINT08 WriteValue ) { uart_write(UTXD, WriteValue); } void UART_WRITE_4BYTES( UINT08 Val1, UINT08 Val2, UINT08 Val3, UINT08 Val4 ) { uart_write(UTXD, Val1); uart_write(UTXD, Val2); uart_write(UTXD, Val3); uart_write(UTXD, Val4); } /*----------------------------------------------------------------------------*\ Setting the baud rate to one of the specific values NOTE: The values in this file are dependent on the clock rates for Tortola, and are based on the assumption that ipg_perclk is set to 66MHz (15.15 ns) and the RFDIV setting in UFCR is 5 (divide by 1). FORMULA: (UBMR + 1) / (UBIR + 1) = ipg_perclk / (baudrate * 16) \*----------------------------------------------------------------------------*/ //void SET_BAUDRATESLOW( unsigned short NewValue ) //{ // uart_write(UBIR, NewValue); // uart_write(UBMR, 0xC350); //} //void SET_BAUDRATE( unsigned short NewValue ) //{ // uart_write(UBIR, NewValue); // uart_write(UBMR, 0x2710); //} void HIGHEST_BAUDRATE( void ) // @ 66 MHz this is 4.125 Mbps { uart_write(UBIR, 0x0000); uart_write(UBMR, 0x0000); } void BAUDRATE_1875Kbps( void ) { uart_write(UBIR, 0x038c); uart_write(UBMR, 0x07cf); } void BAUDRATE_1152Kbps(void) { // For Tortola // uart_write(UBIR, 0x088c); // uart_write(UBMR, 0x1e9e); // For Argon 33.25MHZ uart_write(UBIR, 0x022a); uart_write(UBMR, 0x2710); } void BAUDRATE_920Kbps( void ) { uart_write(UBIR, 0x11fb); uart_write(UBMR, 0x50a4); } void BAUDRATE_812_5Kbps( void ) { uart_write(UBIR, 0x08e0); uart_write(UBMR, 0x2d14); } void BAUDRATE_460Kbps( void ) { uart_write(UBIR, 0x08fd); uart_write(UBMR, 0x50a4); } void BAUDRATE_230Kbps( void ) { uart_write(UBIR, 0x047e); uart_write(UBMR, 0x50a4); } void BAUDRATE_115_2Kbps( void ) // 115.2 Kbps @ 66 MHz { uart_write(UBIR, 0x01a6); uart_write(UBMR, 0x3b2b); } void BAUDRATE_57_6Kbps( void ) // 57.6 Kbps @ 66 MHz { uart_write(UBIR, 0x047e); uart_write(UBMR, 0x50a4); } void BAUDRATE_28_8Kbps( void ) // 28.8 Kbps @ 66 MHz { uart_write(UBIR, 0x0133); uart_write(UBMR, 0xac56); } void BAUDRATE_19_2Kbps( void ) // 19.2 Kbps @ 66 MHz { uart_write(UBIR, 0x8c); uart_write(UBMR, 0x7657); } void BAUDRATE_14_4Kbps( void ) // 14.4 Kbps @ 66 MHz { uart_write(UBIR, 0x99); uart_write(UBMR, 0xac56); } void BAUDRATE_9600bps( void ) // 9600 bps @ 66 MHz { uart_write(UBIR, 0x72); uart_write(UBMR, 0xc10a); } void BAUDRATE_4800bps( void ) // 4800 bps @ 66 MHz { uart_write(UBIR, 0xc); uart_write(UBMR, 0x2ba4); } void BAUDRATE_2400bps( void ) // 2400 bps @ 66 MHz { uart_write(UBIR, 0xc); uart_write(UBMR, 0x5749); } void BAUDRATE_1200bps( void ) // 1200 bps @ 66 MHz { uart_write(UBIR, 0x038c); uart_write(UBMR, 0x0c34); } void BAUDRATE_600bps( void ) // 600 bps @ 66 MHz { uart_write(UBIR, 0x02); uart_write(UBMR, 0x5092); } /*----------------------------------------------------------------------------*\ Useful macros/functions for often occuring functionality \*----------------------------------------------------------------------------*/ void WAIT_FOR_SET( unsigned long Addr, UART_REGSIZE ExpectedMask ) { UART_REGSIZE RegValue; do { RegValue = UART_READ_OP(Addr); } while ((RegValue & ExpectedMask) == 0); } void WAIT_FOR_CLR( unsigned long Addr, UART_REGSIZE ExpectedMask ) { UART_REGSIZE RegValue; do { RegValue = UART_READ_OP(Addr); } while ((RegValue & ExpectedMask) != ExpectedMask); } /*! Waits for the TXDC bit in USR2 being set. Performs a 'busy wait' until the TXDC bit in the USR2 register is being set. This bit indicates that the transmit buffer TxFIFO and shift register are both empty; therefor the transmission is complete. [NOTE: TXDC is automatically cleared when writing data to the TxFIFO] */ void UART_WAIT_FOR_TXDC_SET( void ) { UART_REGSIZE RegValue; do { RegValue = uart_read(USR2); } while ((RegValue & UART_USR2_TXDC) == 0); } /*! Waits for the RRDY bit in the USR1 register being set. Performs a 'busy wait' until the RRDY bit in the USR1 register is being set. This bit indicates that the RxFIFO data level is above the limit specified by the field RXFL in the UFCR register (a.k.a. a minimum of RXFL characters has been received and are available in the RxFIFO). [NOTE: RRDY is automatically cleared when the data level in the RxFIFO falls below the specified threshold] */ int UART_WAIT_FOR_RRDY_SET(void) { UART_REGSIZE RegValue; int rc = 0; int TimeOUT = RDY_TIMEOUT; do { RegValue = uart_read(USR1); } while ((RegValue & UART_USR1_RRDY) == 0 && TimeOUT-- > 0); if (TimeOUT <= 0) rc = 1; return rc; } /*! Waits for the RDR bit in USR2 being set. Performs a 'busy wait' until the RDR bit in the USR2 register is being set. This bit indicates that at least one character is received and written to the RxFIFO. [NOTE: RDR is automatically cleared when the last characters is being read from the RxFIFO] */ int UART_WAIT_FOR_RDR_SET( void ) { UART_REGSIZE RegValue; int rc = 0; int TimeOUT = RDY_TIMEOUT; do { RegValue = uart_read(USR2); // } // while ((RegValue & UART_USR2_RDR) == 0); } while ((RegValue & UART_USR2_RDR) == 0 && TimeOUT-- > 0); if (TimeOUT <= 0) rc = 1; return rc; } /*! Waits for the IDLE bit in USR2 being set. Performs a 'busy wait' until the IDLE bit in the USR2 register is being set. This bit indicates that an idle condition has existed for more than the amount of frames specified in the ICD field in the UCR1 register. [NOTE: IDLE is cleared by writing 1 to this status bit] */ int UART_WAIT_FOR_IDLE_SET( void ) { UART_REGSIZE RegValue; int TimeOUT = IDLE_TIMEOUT; int rc = 0; do { RegValue = uart_read(USR2); } while ((RegValue & UART_USR2_IDLE) == 0 && TimeOUT-- > 0); if (TimeOUT <= 0) rc = 1; return rc; } void uart_setup_iomux_original( void ) // Configure IOMUX { #ifdef SELECT_UART1 // UART1: 4-wire reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x13130000); // RTS/CTS func in/out reg32_write(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1, 0x00001313); //RXD/TXD func in/out #endif #ifdef SELECT_UART2 // UART2: functional reg32_write(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, 0x00000013); reg32_write(SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE, 0x13131300); #endif #ifdef SELECT_UART3 // UART3: ALT2 reg32_write(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1, 0x39393900); // RXD,TXD,RTS,__ reg32_write(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI, 0x39000000); // CTS,__,__,__ #endif #ifdef SELECT_UART4 // UART4: ALT // reg32_write(SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK,0x39000000 ); //RTS4,__,__,__ reg32_write(SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4, 0x00003939); // __,__,RXD,TXD reg32_write(SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0, 0x00000039); // __,__,__,CTS #endif #ifdef SELECT_UART5 // UART5: ALT1 (combined setting for RTS4 and RTS5) reg32_write(SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK, 0x39000025); // RTS4,__,__,RTS5 reg32_write(SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0, 0x25252500); // RXD,TXD,CTS,__ #endif } void uart_setup_iomux_connect_pad( void ) // Configure IOMUX { #ifdef SELECT_UART1 //if (RegValue==2) #ifdef RUN_DTE_TEST { reg32_write(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1, 0x00001313); // 0x43fa000+ 0x80 - RXD/TXD func in/out //reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1,0x13131313); - see conn_fulluart_uart2.c - iomux fore uart1 reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x13130000);//RTS CTS reg32_write(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, 0x13130000); //DCE RI DTE mode reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x00001313); //DSR DTR DTE mode } #else { // DCE mode // reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1,0x13131313 ); - see conn_fulluart_uart1.c reg32_write(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1, 0x00001313); //RXD/TXD func in/out reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x13130000); //DCD RI of DCE1 reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x13131313);//RTS CTS DSR DTR } #endif #endif #ifdef SELECT_UART2 #ifdef RUN_DTE_TEST //if (RegValue==2) { reg32_write(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, 0x25250013); //RXD2 reg32_write(SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE, 0x13131300);// RTS CTS2 TXD2 reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x00004025); //--/--/--/DSR_DTE2 DTR_DTE2 } #else { reg32_write(SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE, 0x13131300); reg32_write(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, 0x00001313);//DTR_DCE2/RXD2--func in/ reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x00000040);//DSR_DCE2 reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x40400000); //DCD_DCE2 RI_DCE2 } #endif #endif #ifdef SELECT_UART3 reg32_write(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1, 0x39390000);// RXD,TXD //reg32_write(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1, 0x39390000);//RTS CTS reg32_write(SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI, 0x00393900); #endif #ifdef SELECT_UART4 reg32_write(SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK,0x39000000 ); //RTS4,__,__,__ reg32_write(SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4, 0x00003939); // __,__,RXD,TXD reg32_write(SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0,0x00000039); // __,__,__,CTS #endif #ifdef SELECT_UART5 reg32_write(SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK, 0x00000025); // RTS4,__,__,RTS5 reg32_write(SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0,0x25252500); // RXD,TXD,CTS,__ #endif } // Config IOMUX by Eyal Liser&Zelda void uart_setup_iomux( void ) // Configure IOMUX { #ifdef SELECT_UART1 #ifdef DTE_MODE // UART1 func mode DTE - RXD,TXD, RTS CTS, RI, DCD, DSR DTR - in input/output mode { reg32_write(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1, 0x00001313); // 0x43fa000+ 0x80 - RXD/TXD func in/out reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x13130000);//RTS CTS reg32_write(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, 0x13130000); //RI DCD DTE mode reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x00001313); //DSR DTR DTE mode } #else { // UART1 func mode DCE - RXD,TXD, RTS CTS, RI, DCD, DSR DTR - in input/output mode reg32_write(SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1, 0x00001313); //RXD/TXD func in/out reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x13130000); //DCD RI of DCE1 reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x13131313);//RTS CTS DSR DTR } #endif #endif #ifdef SELECT_UART2 // UART2 DCE - RXD,TXD, RTS CTS,- func mode , RI, DCD, DSR - alt3 mode out mode;DTR - func mode // all of them in input/output mode reg32_write(SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE, 0x13131300);//TXD2 RTS2 CTS2 - func in/out reg32_write(SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, 0x00001313);//DTR_DCE2 RXD2--func in/out reg32_write(SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1, 0x00000040);//DSR_DCE2 - alt3 out reg32_write(SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1, 0x40400000); //DCD_DCE2 RI_DCE2 - alt3 out #endif #ifdef SELECT_UART3 // UART3 ALT1 mode , DTE mode , RXD TXD RTS CTS in/out //reg32_write(SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1, 0x39390000);// RXD,TXD reg32_write(SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI, 0x00000025);// RXD reg32_write(SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD, 0x25252500);// TXD RTS CTS #endif #ifdef SELECT_UART4 // UART3 ALT1 mode , DTE mode , RXD TXD RTS CTS in/out reg32_write(SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0,0x00000025); //RXD reg32_write(SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK, 0x25252500); // RTS TXD CTS #endif #ifdef SELECT_UART5 // UART3 ALT2 mode , DTE mode , RXD TXD RTS CTS in/out reg32_write(SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2, 0x00393939); // RXD TXD RTS reg32_write(SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE,0x39000000); // CTS #endif } void uart_setup_ccm(void) { //f 0 UINT32 upctl, ccmr, pdr0; // Configure CCM to generate 240MHz USB clock by setting USB PLL Control Register UPCTL // Fref (PLL reference clock) = 32kHz * 1024 // PD = 4 -> PD-field = 3 // MFD = 1024 -> MFD-field = 1023 // MFI = 14 -> MFI-field = 14 // MFN = 664 -> MFN-field = 664 // MFN/MFD = 0.64844 -> BRM-bit = 0 upctl = 0x0000 | (0 << 31) // BRM bit | (3 << 26) // PD field | (1023 << 16) // MFD field | (14 << 10) // MFI field | 664; // MFN field // Configure UART Baud clock: select USB clock as basis for UART Baud clock // UPE = 1 (USB PLL enabled - default) // PERCS = 0 (USB clock used as source for ipg_per_clk) // FPMF = 1 (pre-multiplier = 1024 ccmr = reg32read(CCM_CCMR); ccmr = ccmr & 0xfeffffff; // CCM.PDR0: Divide USB clock by 8 to get 30MHz baud clock // PER_PODF = 8 -> PER_PODF-field = 7 pdr0 = reg32read(CCM_PDR0); pdr0 = pdr0 & (7 << 16); // info_trigger(0xd1, upctl, ccmr); // info_trigger(0xd2, pdr0, upctl); reg32write(CCM_UPCTL, upctl); reg32write(CCM_CCMR, ccmr); reg32write(CCM_PDR0, pdr0); // info_trigger(0xd3, 0xd3, 0xd3); //#endif } //#endif /* #ifndef UART_FUNCTIONS_H__ */