//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2004-2007, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
//  File:  K9F2G08R0A.h
//
//  Contains definitions for FMD impletation of the Samsung K9F2G08R0A NAND
//  flash memory device.
//
//------------------------------------------------------------------------------
#ifndef __K9F2G08R0A_H__
#define __K9F2G08R0A_H__

#define NAND_LARGE_PAGE
#define SWAP_BBI_INFO

// In fact, each block of K9F2G08R0A consists of 64 pages and the page size 
// is 2k bytes. We simulate it as a small page size nand flash, so the sector
// size is still 512 bytes and each block has 64 * (2048 / 512) = 256 sectors.
// The simulation is necessary for Microsoft up layer(fal, mspart, file 
// system) does not support the 2k page size nand flash directly.

#define NAND_BLOCK_CNT          (2048)       // 2048 blocks
#define NAND_PAGE_CNT           (64)        // Each Block has 64 Pages
#define NAND_PAGE_SIZE          (2048)      // Each Page has 2048 Bytes
#define NAND_BLOCK_SIZE         (NAND_PAGE_CNT * NAND_PAGE_SIZE)
#define NAND_BBI_COL_OFFSET         0           // Bad block info spare offset
#define NAND_BUS_WIDTH          8           // 8-bit bus

#define NAND_MAKER_CODE         0xEC        // Samsung
#define NAND_DEVICE_CODE        0xAA

#define NAND_STATUS_MASK_ERROR  (1U << 0)   // Status Bit0 indicates error

#define NAND_ID_CODE            ((NAND_DEVICE_CODE << 8) | NAND_MAKER_CODE)

#define NAND_BBI_PAGE1_OFFSET       0           // Bad block info page addreess offset
#define NAND_BBI_PAGE2_OFFSET       1         // Bad block info page addreess offset
#define BBI_SWAP_ADDR				((NAND_PAGE_SIZE + NAND_BBI_COL_OFFSET) - NANDFC_SPARE_BUFFER_SIZE*(NANDFC_NUM_BUFFERS -1))

// K9F2G08R0A address is sent in 5-cycles
//      1st Cycle:  Column address A[7:0]
//      2nd Cycle:  Column address A[11:8]
//      3rd Cycle:  Page address A[19:12]
//      4th Cycle:  Page address A[27:20]
//      5th Cycle:  Page address A[28:28]

#define NF_ADDR_COL(addr)       { NF_ADDR((addr) & 0xFF);  \
                                 NF_ADDR(((addr) >> 8) & 0x07); }

#define NF_ADDR_PAGE(addr)      { NF_ADDR(((addr) >>  11) & 0xFF);    \
                                  NF_ADDR(((addr) >> 19) & 0xFF); \
                                  NF_ADDR(((addr) >> 27) & 0x01);}


// sequential read operation is not supported by K9F2G08R0A
#define NF_READ_SEQ(sectAddr)   (FALSE)

#endif    // __K9F2G08R0A_H__