//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004, Motorola Inc. All Rights Reserved
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2007, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//
//  File:  bspserial.c
//
//  Provides BSP-specific configuration routines for the UART peripheral.
//
//-----------------------------------------------------------------------------

#pragma warning(push)
#pragma warning(disable: 4115 4201 4204 4214)
#include <windows.h>
#pragma warning(pop)

#include "bsp.h"
#include "uart.h"

//-----------------------------------------------------------------------------
// External Functions

//-----------------------------------------------------------------------------
// External Variables

//-----------------------------------------------------------------------------
// Defines

#define UART_MAX_DIV            7

//-----------------------------------------------------------------------------
// Types

//-----------------------------------------------------------------------------
// Global Variables

//-----------------------------------------------------------------------------
// Local Variables

//-----------------------------------------------------------------------------
// Local Functions

//-----------------------------------------------------------------------------
//
// Function: BSPUartCalRFDIV
//
// This is a private function to calculate the data
// rate divider from input frequency.
//
// Parameters:
//      dwFrequency
//          [in] Frequency requested.
//
// Returns:
//      Data rate divisor for requested frequency.
//-----------------------------------------------------------------------------
UCHAR BSPUartCalRFDIV(ULONG* pRefFreq)
{
    UCHAR dwDivisor; // the data rate divisor
    UINT32 freq;
    *pRefFreq = UART_REF_FREQ;

    DDKClockGetFreq(DDK_CLOCK_SIGNAL_PER, &freq);
    dwDivisor = (UCHAR) (freq / *pRefFreq);

    if ( (freq / dwDivisor) < UART_REF_FREQ)
    {
       dwDivisor--; 
       if (dwDivisor < 0)
	   	dwDivisor = 0;
    }

    else if ((freq / dwDivisor) > UART_REF_FREQ)
		dwDivisor++;
	
    if (dwDivisor == 0)
    {
        dwDivisor = 1;
    }
    else if (dwDivisor > UART_MAX_DIV)
    {
        dwDivisor = UART_MAX_DIV;
    }

    *pRefFreq = freq /dwDivisor;

    return dwDivisor;
}

//-----------------------------------------------------------------------------
//
// Function: BSPUartGetType
//
// This is a private function to get the UART type with specified Uart
// IO address.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//      pType
//          [out] Serial device type (DCE/DTE).
//
// Returns:
//      corresponding uart type.
//-----------------------------------------------------------------------------
BOOL BSPUartGetType(ULONG HWAddr, uartType_c * pType)
{
    switch (HWAddr)
    {
        case CSP_BASE_REG_PA_UART1:
#if 0
            *pType = DCE;
#else
            *pType = DTE;
#endif
            return TRUE;
        case CSP_BASE_REG_PA_UART2:
            *pType = DTE;
            return TRUE;
        case CSP_BASE_REG_PA_UART3:
            *pType = DTE;
            return TRUE;
        case CSP_BASE_REG_PA_UART4:
            *pType = DTE;
            return TRUE;
        case CSP_BASE_REG_PA_UART5:
            *pType = DTE;
            return TRUE;
        default:
            return FALSE;
    }
}

//-----------------------------------------------------------------------------
//
// Function: BSPUartEnableClock
//
// This function is a wrapper for Uart to enable/disable its clock using a valid
// CRM handle.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//      bEnable
//          [in] TRUE if Uart Clock is to be enabled. FALSE if Uart Clock is
//                to be disabled.
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
BOOL BSPUartEnableClock(ULONG HWAddr, BOOL bEnable)
{
    BOOL result = FALSE;
    DDK_CLOCK_GATE_INDEX cgIndex;

    switch (HWAddr)
    {
        case CSP_BASE_REG_PA_UART1:
            cgIndex = DDK_CLOCK_GATE_INDEX_UART1;
            break;
        case CSP_BASE_REG_PA_UART2:
            cgIndex = DDK_CLOCK_GATE_INDEX_UART2;
            break;
        case CSP_BASE_REG_PA_UART3:
            cgIndex = DDK_CLOCK_GATE_INDEX_UART3;
            break;
        case CSP_BASE_REG_PA_UART4:
            cgIndex = DDK_CLOCK_GATE_INDEX_UART4;
            break;
        case CSP_BASE_REG_PA_UART5:
            cgIndex = DDK_CLOCK_GATE_INDEX_UART5;
            break;
        default:
            return result;
    }

    if (bEnable)
    {
        result = DDKClockSetGatingMode(cgIndex,
                                       DDK_CLOCK_GATE_MODE_ENABLED_ALL);
    }
    else
    {
        result = DDKClockSetGatingMode(cgIndex,
                                       DDK_CLOCK_GATE_MODE_DISABLED);
    }
    return result;
}

//-----------------------------------------------------------------------------
//
// Function: BSPUartConfigTranceiver
//
// This function is used to configure the Tranceiver.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//      bEnable
//          [in] TRUE if tranceiver is to be enabled,
//                FALSE if tranceiver is to be disabled.
//               
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
VOID BSPUartConfigTranceiver(ULONG HWAddr,BOOL bEnable)
{
    //PHYSICAL_ADDRESS phyAddr = {BSP_BASE_REG_PA_PBC_BASE, 0};
    //PCSP_PBC_REGS g_pPBC;

    // Map PBC registers to virtual address space
    //g_pPBC = (PCSP_PBC_REGS) MmMapIoSpace(phyAddr, sizeof(CSP_PBC_REGS), FALSE);
    //if (g_pPBC == NULL)
    //{
     //   return ;
    //}

    if(bEnable)
    {
        switch (HWAddr)
        {
            case CSP_BASE_REG_PA_UART1:

                //Map UART1 to UART C
                //OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELC_LSH));
                //Enable UART C
               // OUTREG16(&g_pPBC->BCTRL1_CLEAR,(1 << PBC_BCTRL1_CLEAR_UENCE_LSH));
                //Enable UART C MODEM
               // OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENC_LSH));

                /*
                //Map UART1 to UART A
                OUTREG16(&g_pPBC->BCTRL2_CLEAR,  (1 << PBC_BCTRL2_USELA_LSH));
                //Enable UART A
                OUTREG16 (&g_pPBC->BCTRL1_CLEAR,  (1 << PBC_BCTRL1_CLEAR_UENA_LSH));
                //Enable UART A MODEM
                OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENA_LSH));
                */

                break;

            case CSP_BASE_REG_PA_UART2:

                /*
                //Map UART2 to UART C
                OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_USELC_LSH));
                //Enable UARTC
                OUTREG16 (&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENCE_LSH));
                //Enable UART C MODEM
                OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENC_LSH));
                */
                break;

            case CSP_BASE_REG_PA_UART3:

                //Map UART3 to UART B
                //OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_USELB_LSH));
                //Enable UARTB
                //OUTREG16(&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENB_LSH));
                break;

            case CSP_BASE_REG_PA_UART4:

                //Map UART4 to UART B
                //OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_USELB_LSH));
                //Enable UART B
                //OUTREG16(&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENB_LSH));
                break;

            case CSP_BASE_REG_PA_UART5:

                //Map UART5 to UART A
                //OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELA_LSH));
                //Enable UART A
                //OUTREG16(&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENA_LSH));
                //Enable UART A MODEM
                //OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENA_LSH));
                break;
        }
    }
    else
    {
        switch (HWAddr)
        {
            case CSP_BASE_REG_PA_UART1:

                //Reset UART C
                //OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELC_LSH));
                //Disable UART C
                //OUTREG16(&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENCE_LSH));
                //Disable UART C MODEM
                //OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENC_LSH));

                /*
                //Reset UART A
                OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELA_LSH));
                //Disable UART A
                OUTREG16 (&g_pPBC->BCTRL1_SET,  (1 << PBC_BCTRL1_CLEAR_UENA_LSH));
                //Disable UART A MODEM
                OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_UMODENA_LSH));
                */
                break;

            case CSP_BASE_REG_PA_UART2:

                /*
                //Reset UART C
                OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_USELC_LSH));
                //Disable UARTC
                OUTREG16 (&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENCE_LSH));
                //Disable UART C MODEM
                OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENC_LSH));
                */
                break;

            case CSP_BASE_REG_PA_UART3:

                //Reset UART B
                //OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_USELB_LSH));
                //Disable UARTB
                //OUTREG16(&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENB_LSH));
                break;

                case CSP_BASE_REG_PA_UART4:

                //Reset UART B
                //OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_USELB_LSH));
                //Disable UARTB
                //OUTREG16(&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENB_LSH));
                break;

                case CSP_BASE_REG_PA_UART5:

                //Reset UART A
                //OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELA_LSH));
                //Disable UART A
                //OUTREG16(&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENA_LSH));
                //Disable UART A MODEM
                //OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_UMODENA_LSH));
                break;

        }
    }

    //MmUnmapIoSpace(g_pPBC,sizeof(CSP_PBC_REGS));
}

//-----------------------------------------------------------------------------
//
// Function: BSPUartConfigureGPIO
//
// This function is used to configure the GPIO.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------

BOOL BSPUartConfigureGPIO(ULONG HWAddr)
{
   BOOL result = FALSE;
   
   switch (HWAddr) {
      case CSP_BASE_REG_PA_UART1:
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_RXD1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_TXD1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_RTS1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_CTS1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
#if 0
         // Remove by Paul, Chao @ 2009/1/15 for USBHSH_nCS (MCU2_8)
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_DTR_DCE1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         // Remove by Paul, Chao @ 2009/1/15 for uP_SW_nRESET (MCU2_9)
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_DSR_DCE1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         // Remove by Paul, Chao @ 2009/1/15 for uP_GPIO_2 (MCU2_10)
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_RI_DCE1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         // Remove by Paul, Chao @ 2009/1/15 for uP_nIRQD (MCU2_11)
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_DCD_DCE1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
#else
         // Add by Paul, Chao @ 2009/1/15 for uP_UARTA_DTR (MCU2_12)
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_DTR_DTE1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         // Add by Paul, Chao @ 2009/1/15 for uP_UARTA_DSR (MCU2_13)
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_DSR_DTE1, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
#endif
         break;
      case CSP_BASE_REG_PA_UART2:
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_TXD2, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_RXD2, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_CTS2, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_RTS2, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
#if 0
         // Remove by Paul, Chao @ 2009/1/15 for USBOTG_nCS (MCU2_16)
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_DTR_DCE2, DDK_IOMUX_OUT_FUNC,
                           DDK_IOMUX_IN_FUNC);
#endif
         break;
      case CSP_BASE_REG_PA_UART3:
         // uP_UARTC_RX
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_CSPI3_MOSI, DDK_IOMUX_OUT_ALT1,
                           DDK_IOMUX_IN_ALT1);
         // uP_UARTC_TX
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_CSPI3_MISO, DDK_IOMUX_OUT_ALT1,
                           DDK_IOMUX_IN_ALT1);
         // uP_UARTC_CTS
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_CSPI3_SPI_RDY, DDK_IOMUX_OUT_ALT1,
                           DDK_IOMUX_IN_ALT1);
         // uP_UARTC_RTS
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_CSPI3_SCLK, DDK_IOMUX_OUT_ALT1,
                           DDK_IOMUX_IN_ALT1);
         break;
      case CSP_BASE_REG_PA_UART4:
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_ATA_CS0, DDK_IOMUX_OUT_ALT1,
                           DDK_IOMUX_IN_ALT1);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_ATA_CS1, DDK_IOMUX_OUT_ALT1,
                           DDK_IOMUX_IN_ALT1);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_ATA_DIOR, DDK_IOMUX_OUT_ALT1,
                           DDK_IOMUX_IN_ALT1);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_ATA_DIOW, DDK_IOMUX_OUT_ALT1,
                           DDK_IOMUX_IN_ALT1);
         break;
      case CSP_BASE_REG_PA_UART5:
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_PC_VS2, DDK_IOMUX_OUT_ALT2,
                           DDK_IOMUX_IN_ALT2);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_PC_BVD1, DDK_IOMUX_OUT_ALT2,
                           DDK_IOMUX_IN_ALT2);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_PC_BVD2, DDK_IOMUX_OUT_ALT2,
                           DDK_IOMUX_IN_ALT2);
         DDKIomuxSetPinMux(DDK_IOMUX_PIN_PC_RST, DDK_IOMUX_OUT_ALT2,
                           DDK_IOMUX_IN_ALT2);
         break;
      default:
         return result;
   }
   
   return TRUE;
}

//-----------------------------------------------------------------------------
//
// Function: BSPSerGetChannelPriority
//
// This function is a wrapper for Uart to find out the SDMA channel priority.
//
// Parameters:
//
// Returns:
//      SDMA channel priority for Serial.
//
//-----------------------------------------------------------------------------
UINT8 BSPSerGetChannelPriority()
{
    return BSP_SDMA_CHNPRI_SERIAL;
}

//-----------------------------------------------------------------------------
//
// Function: BSPSerGetDMAIsEnabled
//
// This function is a wrapper for Uart to find out if SDMA is to be used or not.
// The UARTs are identified based on the based address.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
// Returns:
//      TRUE if SDMA is to be used for this UART.
//
//-----------------------------------------------------------------------------
BOOL BSPSerGetDMAIsEnabled(ULONG HWAddr)
{
    BOOL useDMA = FALSE;
    switch (HWAddr) {
        case CSP_BASE_REG_PA_UART1:
#if BSP_SDMA_SUPPORT_UART1
            useDMA = TRUE;
#endif
            break;
        case CSP_BASE_REG_PA_UART2:
#if BSP_SDMA_SUPPORT_UART2
            useDMA = TRUE;
#endif
            break;
        case CSP_BASE_REG_PA_UART3:
#if BSP_SDMA_SUPPORT_UART3
            useDMA = TRUE;
#endif
            break;
        case CSP_BASE_REG_PA_UART4:
#if BSP_SDMA_SUPPORT_UART4
            useDMA = TRUE;
#endif
            break;
        case CSP_BASE_REG_PA_UART5:
#if BSP_SDMA_SUPPORT_UART5
            useDMA = TRUE;
#endif
            break;
        default:
            break;
    }
    return useDMA;
}

//-----------------------------------------------------------------------------
//
// Function: BSPSerGetDMARequest
//
// This function is a wrapper for Uart to find out the TX/RX SDMA request line.
// The UARTs are identified based on the based address.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//      reqRx
//          [out] the RX SDMA request line to be used for this UART.
//      reqTx
//          [out] the TX SDMA request line to be used for this UART.
// Returns:
//      TRUE if SDMA is to be used for this UART.
//
//-----------------------------------------------------------------------------
BOOL BSPSerGetDMARequest(ULONG HWAddr, int* reqRx, int* reqTx)
{
    switch (HWAddr)
    {
        case CSP_BASE_REG_PA_UART1:
            *reqRx = DDK_DMA_REQ_UART1_RX;
            *reqTx = DDK_DMA_REQ_UART1_TX;
            break;
        case CSP_BASE_REG_PA_UART2:
            *reqRx = DDK_DMA_REQ_UART2_RX;
            *reqTx = DDK_DMA_REQ_UART2_TX;
            break;
        case CSP_BASE_REG_PA_UART3:
            *reqRx = DDK_DMA_REQ_UART3_RX;
            *reqTx = DDK_DMA_REQ_UART3_TX;
            break;
        case CSP_BASE_REG_PA_UART4:
            *reqRx = DDK_DMA_REQ_UART4_RX;
            *reqTx = DDK_DMA_REQ_UART4_TX;
            break;
        case CSP_BASE_REG_PA_UART5:
            *reqRx = DDK_DMA_REQ_UART5_RX;
            *reqTx = DDK_DMA_REQ_UART5_TX;
            break;
        default:
            return FALSE;
    }
    return TRUE;
}

//-----------------------------------------------------------------------------
//
// Function: BSPSerSetDMAReqGpr
//
// This function is a wrapper for Uart to acquire a muxed SDMA request line.
// The UARTs are identified based on the based address.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
// Returns:
//      TRUE if success.
//
//-----------------------------------------------------------------------------
BOOL BSPSerAcquireDMAReqGpr(ULONG HWAddr)
{
    BOOL bRet = FALSE;

    // set the GPR bits to value that makes the corresponding UARTs work.
    switch (HWAddr)
    {
        case CSP_BASE_REG_PA_UART2:
            bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_FIRI_UART2, 0);
            break;
        case CSP_BASE_REG_PA_UART3:
            bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_CSPI1_UART3, 1);
            break;
        case CSP_BASE_REG_PA_UART5:
            bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_CSPI3_UART5, 1);
            break;
        default:
            break;
    }
    return bRet;
}

//-----------------------------------------------------------------------------
//
// Function: BSPSerRestoreDMAReqGpr
//
// This function is a wrapper for Uart to restore a muxed SDMA request line.
// The UARTs are identified based on the based address.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
// Returns:
//      TRUE if success.
//
//-----------------------------------------------------------------------------
BOOL BSPSerRestoreDMAReqGpr(ULONG HWAddr)
{
    BOOL bRet = TRUE;

    // restore the GPR bits to power-on values.
    switch (HWAddr)
    {
        case CSP_BASE_REG_PA_UART2:
            bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_FIRI_UART2, 0);
            break;
        case CSP_BASE_REG_PA_UART3:
            bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_CSPI1_UART3, 0);
            break;
        case CSP_BASE_REG_PA_UART5:
            bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_CSPI3_UART5, 0);
            break;
        default:
            break;
    }
    return bRet;
}

//-----------------------------------------------------------------------------
//
// Function: BSPGetDMABuffSize
//
// This function is a wrapper for Uart to find out the TX/RX SDMA.
// The UARTs are identified based on the based address.
//
// Parameters:
//      buffRx
//          [out] the RX SDMA buffer size.
//
//      buffTx
//          [out] the RX SDMA buffer size 
// Returns:
//      
//
//-----------------------------------------------------------------------------
VOID BSPGetDMABuffSize(UINT16* buffRx, UINT16 * buffTx)
{
    *buffRx = SERIAL_SDMA_RX_BUFFER_SIZE;
    *buffTx = SERIAL_SDMA_TX_BUFFER_SIZE;
}