//------------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//-----------------------------------------------------------------------------
//
//  Copyright (C) 2006-2007, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//-----------------------------------------------------------------------------
//
//  File:  bsp_cfg.h
//
//  This file contains system constant specific for MX31 3DS board.
//
//------------------------------------------------------------------------------
#ifndef __BSP_CFG_H
#define __BSP_CFG_H

//------------------------------------------------------------------------------
//
//  Define:  BSP_DEVICE_PREFIX
//
//  Prefix used to generate device name for bootload/KITL
//
//#define BSP_DEVICE_PREFIX       "MX31"                  // Device name prefix
#define BSP_DEVICE_PREFIX           "LoCE_"      // Device name prefix

//------------------------------------------------------------------------------
// CPU Configuration Settings
//------------------------------------------------------------------------------

// Define BSP_OAL_DISABLE_ALIGNMENT_FAULT if you want to disable strict 
// alignment fault checking (i.e. the ARM Control Register A-bit will be
// cleared during OALIoCtlHalPostInit).  Leave BSP_OAL_DISABLE_ALIGNMENT_FAULT
// undefined to keep strict alignment fault checking enabled.  
//
// #define BSP_OAL_DISABLE_ALIGNMENT_FAULT

//------------------------------------------------------------------------------
// Clock Configuration Settings
//------------------------------------------------------------------------------
#define BSP_MAX_CORE_CLK_FREQ   532000000       // AP Max CPU clock = 532 MHz
#define RESCHED_PERIOD          1               // Reschedule ms
#ifdef BSP_OAL_TIMER32K
#define BSP_SYSTIMER_PRESCALAR  (1-1)               // System timer prescalar
#define BSP_SYSTIMER_CLKSRC     EPIT_CR_CLKSRC_CKIL // CKIL system timer source
// If OS tick timer (EPIT1) is being sourced from CKIL, then
// we can update PERCLK without impacting the system
#define BSP_SYSTIMER_CGR_MASK   (0)
#else
#define BSP_SYSTIMER_PRESCALAR  (4-1)               // System timer prescalar
#define BSP_SYSTIMER_CLKSRC     EPIT_CR_CLKSRC_IPGCLK // CKIL system timer source
#define BSP_SYSTIMER_CGR_MASK   CCM_CGR0_EPIT1_MASK
#endif

//------------------------------------------------------------------------------
// SDHC configurations
//------------------------------------------------------------------------------
#define BSP_CLK_GATING_BETWEEN_CMDS_SDHC1   TRUE
#define BSP_CLK_GATING_BETWEEN_CMDS_SDHC2   TRUE
#define BSP_SDHC_SDMA_MIN_TRANSFER          256
#define BSP_SDHC_MAX_SDBUS_CLK_SUPPORTED    25000000U
#define BSP_SDHC_POLL_DATA_LENGTH           0x7FFFFFFF // should be always > 64

//------------------------------------------------------------------------------
// SDMA Configuration
//------------------------------------------------------------------------------
#define BSP_SDMA_MC0PTR         IMAGE_WINCE_DDKSDMA_IRAM_PA_START

#define BSP_SDMA_CHNPRI_AUDIO   (SDMA_CHNPRI_CHNPRI_HIGHEST)
#define BSP_SDMA_CHNPRI_ATA     (SDMA_CHNPRI_CHNPRI_HIGHEST-5)
#define BSP_SDMA_CHNPRI_FIRI    (SDMA_CHNPRI_CHNPRI_HIGHEST-1)
#define BSP_SDMA_CHNPRI_CSPI    (SDMA_CHNPRI_CHNPRI_HIGHEST-2)
#define BSP_SDMA_CHNPRI_SDHC1   (SDMA_CHNPRI_CHNPRI_HIGHEST-3)
#define BSP_SDMA_CHNPRI_SDHC2   (SDMA_CHNPRI_CHNPRI_HIGHEST-3)
#define BSP_SDMA_CHNPRI_SERIAL  (SDMA_CHNPRI_CHNPRI_HIGHEST-4)

#define BSP_SDMA_SUPPORT_ATA    TRUE
#define BSP_SDMA_SUPPORT_SSI1   TRUE
#define BSP_SDMA_SUPPORT_SSI2   TRUE
#define BSP_SDMA_SUPPORT_SDHC1  TRUE
#define BSP_SDMA_SUPPORT_SDHC2  TRUE
#define BSP_SDMA_SUPPORT_CSPI1  FALSE
#define BSP_SDMA_SUPPORT_CSPI2  FALSE
#define BSP_SDMA_SUPPORT_CSPI3  FALSE
#define BSP_SDMA_SUPPORT_UART1  FALSE
#define BSP_SDMA_SUPPORT_UART2  FALSE
#define BSP_SDMA_SUPPORT_UART3  FALSE
#define BSP_SDMA_SUPPORT_UART4  FALSE
#define BSP_SDMA_SUPPORT_UART5  FALSE
#define BSP_SDMA_SUPPORT_FIRI   FALSE
#define BSP_SDMA_SUPPORT_SIM    FALSE
#define BSP_SDMA_SUPPORT_NANDFC FALSE

//------------------------------------------------------------------------------
// Audio Configuration
//------------------------------------------------------------------------------

// Set BSP_AUDIO_DMA_BUF_ADDR to static DMA buffer physical address.  Comment
// out these two definitions to force the audio DMA buffers to be dynamically
// allocated by the audio driver from external RAM.
//#define BSP_AUDIO_DMA_BUF_ADDR  IMAGE_WINCE_AUDIO_IRAM_PA_START
//#define BSP_AUDIO_DMA_BUF_SIZE  IMAGE_WINCE_AUDIO_IRAM_SIZE

//------------------------------------------------------------------------------
// Ethernet Board Configuration
//------------------------------------------------------------------------------
#define BSP_CS8900_IRQ          IRQ_RESERVED1
#define BSP_LAN911x_IRQ        IRQ_RESERVED1

//------------------------------------------------------------------------------
// USB Board Configuration
//------------------------------------------------------------------------------
#define BSP_USB_IRQ             IRQ_RESERVED38

//------------------------------------------------------------------------------
// PBC Board Configuration
//------------------------------------------------------------------------------
#define BSP_PBC_IRQ             BSP_LAN911x_IRQ
#define BSP_PBC_GPIO_PORT       DDK_GPIO_PORT1
#define BSP_PBC_GPIO_PIN        1
#define BSP_PBC_GPIO_LEVEL      GPIO_ICR_LOW_LEVEL
#define BSP_PBC_GPIO_FALL_EDGE  GPIO_ICR_FALL_EDGE

//------------------------------------------------------------------------------
// PBC User Switch Definitions
//------------------------------------------------------------------------------
#define BSP_PBC_DSW_KITL        (1 << 0)    // SW3_8:  ON = ACTIVE, OFF = PASSIVE
#define BSP_PBC_DSW_L2          (1 << 1)    // SW3_7:  ON = L2 enabled, OFF = L2 disabled
#define BSP_PBC_DSW_AHB_CLK     (1 << 2)    // SW3_6:  ON = 133MHz, OFF = 66MHz
#define BSP_PBC_DSW_ARM_CLK     (1 << 3)    // SW3_5:  ON = 532MHz, OFF = 266MHz
#define BSP_PBC_DSW_ALT_CLK     (1 << 4)    // SW3_4:  ON = SW3[5:6] determine clocking
                                            //        OFF = Force alternate clocking

#define BSP_PBC_DSW_DPTC        (1 << 5)    // SW3_3:  ON = ACTIVE, OFF = PASSIVE 
#define BSP_PBC_DSW_DVFS        (1 << 6)    // SW3_2:  ON = ACTIVE, OFF = PASSIVE 
#define BSP_PBC_DSW_L2_WT       (1 << 7)    // SW3_1:  ON = L2 write through, OFF = L2 write back
#define BSP_PBC_DSW_DMA_REQ     (1 << 8)    // SW3_x:  DMA_REQ
#define BSP_PBC_DSW_PMX         (1 << 9)    // SW3_x:  ON = ACTIVE, OFF = PASSIVE  


//------------------------------------------------------------------------------
// PMIC Board Configuration
//------------------------------------------------------------------------------
#define BSP_PMIC_IRQ            GET_GPIOPINNAME_IRQ(PMIC_PRIINT)
#define BSP_PMIC_CSPI_FREQ      4000000 // 4 MHz (limited by ADS signal quality)
#define BSP_PMIC_CSPI_PORT      2
#define BSP_PMIC_CSPI_CHIPSEL   CSPI_CONREG_SS0
#define BSP_PMIC_IOMUX_PIN      GET_GPIOPINNAME_DDKIOMUX(PMIC_PRIINT, PIN)
#define BSP_PMIC_IOMUX_PAD      GET_GPIOPINNAME_DDKIOMUX(PMIC_PRIINT, PAD)
#define BSP_PMIC_GPIO_PORT      GET_GPIOPINNAME_DDKPORT(PMIC_PRIINT)
#define BSP_PMIC_GPIO_PIN       GET_GPIOPINNAME_PIN(PMIC_PRIINT)


#define BSP_PMIC_TURBO_mV       1600    // 1.6 V
#define BSP_PMIC_HIGH_mV        1200    // 1.2 V
#define BSP_PMIC_LOW_mV         1000    // 1.0 V
#define BSP_PMIC_STANDBY_mV     1000    // 1.0 V
#define BSP_PMIC_PLL_mV         1200    // 1.2 V


#define BSP_PMIC_CPU_REGULATOR  SW1A
#define BSP_PMIC_1V8_VOLT    0x24           // MC13783 code for 1.800V
#define BSP_PMIC_NORMAL_VOLT    0x1C    // MC13783 code for 1.600V
//#define BSP_PMIC_STANDBY_VOLT   0x1C    // MC13783 code for 1.60V
#define BSP_PMIC_STANDBY_VOLT   0x4     // MC13783 code for 1.0V
#define BSP_PMIC_LOWEST_VOLT    0x0           // MC13783 code for 0.9V

//------------------------------------------------------------------------------
// DVFC Configuration
//------------------------------------------------------------------------------
#define BSP_DVFC_EMI_DCG                // Define to enable EMI_DCG
#define BSP_DVFC_EMI_DCG_CNT    0x2     // 0x2 => 130 AHB clocks

//------------------------------------------------------------------------------
// LCD Panel Configuration to support IOCTL_HAL_QUERY_DISPLAYSETTINGS
//------------------------------------------------------------------------------
#define BSP_PREF_DISPLAY_WIDTH  240
#define BSP_PREF_DISPLAY_HEIGHT 320
#define BSP_PREF_DISPLAY_BPP    16

//------------------------------------------------------------------------------
// DirectDraw Display Driver Support for Screen Rotation
// Note: Windows CE documentation states that DirectDraw and screen rotation
// are incompatible.  Although modifications have been made to run DirectDraw
// with screen rotation, there may be unexpected failures in the GDI CETK suite.
//------------------------------------------------------------------------------
// Video Memory memory attributes
// The video memory region may be configured as cacheable, write-through (WT)
// or as non-cacheable, bufferable (NCB).  Although WT mode provides a small
// performance benefit, there is an ARM errata (#399234) which could cause video
// memory data to become corrupted when in this mode.  NCB mode provides a
// workaround for this errata.
//------------------------------------------------------------------------------
// ADC Tearing Prevention
// When using a smart display, which requires the IPU ADC driver, tearing
// can be enabled (TRUE) or disabled (FALSE).  If tearing is enabled, each ADC 
// update to the display will be synchronized to the panel VSYNC.
//------------------------------------------------------------------------------
// Frame Dropping
// Video frames can be dropped discreetly (i.e., without returning a notice to
// the calling application) by setting BSP_DROP_FRAMES_QUIETLY to TRUE.
// Windows Media Player does not respond well to Flip() calls that result in
// a dropped frame.  Setting this variable to TRUE will allow WMP to play
// smoother video.
//------------------------------------------------------------------------------
// TV OUT Configurations:
//
// For TV Out, please set BSP_DIRECTDRAW_SUPPORT_ROTATION = TRUE
//
// To support YCrCb as an input of FS45X TV Encoder, please set TV_YCRCB_INPUT = TRUE
//
// To support RGB an an input of FS45X TV Encoder, please set TV_YCRCB_INPUT = FALSE
//
// To support TV Out D1 resolution, set TV_D1 = TRUE, otherwise set TV D1 = FALSE 
// for 640x480
//
// To support TV Out NTSC, set TV_NTSC = TRUE, otherwise set TV_NTSC = FALSE for PAL
//------------------------------------------------------------------------------
#define BSP_DIRECTDRAW_SUPPORT_ROTATION TRUE
#define BSP_VID_MEM_CACHE_WRITETHROUGH  FALSE
#define BSP_ADC_ENABLE_TEARING_PREVENTION  TRUE
#define BSP_DROP_FRAMES_QUIETLY         TRUE
#define TV_YCRCB_INPUT                  TRUE
#define TV_D1                           TRUE
#define TV_NTSC                         TRUE

//------------------------------------------------------------------------------
// Debug OUTPUT
// DEBUG_PORT specifies which UART we use for debug serial port. It must be one
// of the following :
//     DBG_UART1
//     DBG_SC16C652_PORTA
//     DBG_SC16C652_PORTB
//------------------------------------------------------------------------------
#define DBG_UART1               1
#define DBG_UART3               3
#define DBG_SC16C652_PORTA      4
#define DBG_SC16C652_PORTB      5

// To disable debug port messages altogether, define DEBUG_PORT to 0
#define DEBUG_PORT          DBG_UART1

// Power management of the debug serial port is controlled as follows:
//
// BSP_DEBUG_SERIAL_PM = TRUE  => Power management enabled. UART will be
//                                clock gated when TX FIFO is empty.
//
// BSP_DEBUG_SERIAL_PM = FALSE => Power management disabled. UART clocks
//                                will remain enabled upon first call to
//                                OEMWriteDebugByte/OEMReadDebugByte.  This
//                                setting may be required when using the
//                                debug serial port for console input.
//
// NOTE:  These settings only apply for the OS image.  The UART clocks are
//        enabled and not managed for bootloaders.
//
#define BSP_DEBUG_SERIAL_PM             FALSE


//------------------------------------------------------------------------------
// Serial KITL Configurations
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
//  Define:  BSP_BASE_REG_PA_SERIALKITL
//
//  Specifies physical address of serial port used for serial KITL transport.
//
#define BSP_BASE_REG_PA_SERIALKITL              CSP_BASE_REG_PA_UART3
#define BSP_UART_KITL_SERIAL_BAUD				115200

//------------------------------------------------------------------------------
// I2C Port
// The I2C_PORT specifies the which I2C device will be used.  It must be
// one of the following :
//     CAM_I2C_PORT
//     USB_I2C_PORT
//------------------------------------------------------------------------------
#define CAM_I2C_PORT           L"I2C1:"
#define USB_I2C_PORT           L"I2C3:"

//------------------------------------------------------------------------------
// Boot configuration data storage
// BOOTCFG_STORAGE specifies what storage is used for storage boot configuration
// data.
// It must be one of the following :
//     BOOTCFG_STORAGE_NAND
//     BOOTCFG_STORAGE_EEPROM
//-----------------------------------------------------------------------------
#define BOOTCFG_STORAGE_NAND        0
#define BOOTCFG_STORAGE_EEPROM      1

//#define BOOTCFG_STORAGE             BOOTCFG_STORAGE_NAND
#define BOOTCFG_STORAGE             BOOTCFG_STORAGE_EEPROM

//------------------------------------------------------------------------------
#define SYSINTR_USBOTG          (SYSINTR_FIRMWARE+2)

//------------------------------------------------------------------------------
// UART Port
// Defines for UART Rx and Tx SDMA buffer size per SDMA buffer descriptor.  
//------------------------------------------------------------------------------
#define SERIAL_SDMA_RX_BUFFER_SIZE 0x200
#define SERIAL_SDMA_TX_BUFFER_SIZE 0x400

//------------------------------------------------------------------------------
// Defines the Maximum Baudrate and reference frequency for UART
//------------------------------------------------------------------------------
#define UART_MAX_BAUDRATE    2200000
#define UART_REF_FREQ    (16 * UART_MAX_BAUDRATE)

//------------------------------------------------------------------------------
// GPS module
// 
//------------------------------------------------------------------------------
#define BSP_GPIO_PWR_EN_GPS     2//MCU3_2
#define BSP_GPIO_GPS_RESET     15//MCU2_15

//------------------------------------------------------------------------------
// Running Status Indicator LED index
//------------------------------------------------------------------------------
#define RUNNING_INDICATOR_DLED_INDEX    32

//------------------------------------------------------------------------------
// Debug LED
// DEBUG_LED specifies which LED we use for debug LED port.
//------------------------------------------------------------------------------
#define DEBUG_LED_PINNAME               uP_GPIO_0

//------------------------------------------------------------------------------
// Notification LED
// NOTIFICATION_LED specifies which LED we use for Notification LED port.
//------------------------------------------------------------------------------
#define NOTIFICATION_LED_PINNAME        uP_GPIO_1

#endif   // __BSP_CFG_H