//------------------------------------------------------------------------------
//
//  Copyright (C) 2004-2007, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
//  File:  bsp_clocks.h
//
//  This file contains macros for the different clocks available on the 
//  MX31 chip.
//
//------------------------------------------------------------------------------
#ifndef __BSP_CLOCKS_H
#define __BSP_CLOCKS_H


//------------------------------------------------------------------------------
// Board clocks
//------------------------------------------------------------------------------

//
// Define the input clocks
//
#define BSP_CLK_CKIH_FREQ           (26000000U)  // CKIH clock is 26 MHz
#define BSP_CLK_CKIL_FREQ           (32768U)     // CKIL is 32.768 KHz
#define BSP_CLK_FPM_FREQ            (BSP_CLK_CKIL_FREQ*1024)

//
// Specify the PLL reference clock.  This value will be used
// to scale the DPTC threshold table 
//
#define BSP_CLK_PLL_REF             BSP_CLK_CKIH_FREQ

//
// Clocks after boot
//
#define BSP_CLK_UART_REF            66000000
#define BSP_CLK_USBPLL_FREQ         240000000U  // USB PLL = 240 MHz
#define BSP_CLK_SERPLL_FREQ         220147200U  // Serial PLL = 220.1472 MHz

#define BSP_CLK_MCUPLL_FREQ         532000000U  // MCU PLL setting
#define BSP_CLK_MCUPLL_FREQ_ALT     528000000U  // MCU PLL alternate setting

#define BSP_CLK_IPG_FREQ            66500000U   // IPG clock (high/low)
#define BSP_CLK_IPG_FREQ_ALT        66000000U   // IPG alternate setting

#define BSP_CLK_PERCK_FREQ          (BSP_CLK_USBPLL_FREQ /  4)


#endif  // __BSP_CLOCKS_H