//------------------------------------------------------------------------------ // // Copyright (C) 2004-2007, Freescale Semiconductor, Inc. All Rights Reserved. // THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS // AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT // //------------------------------------------------------------------------------ // // File: pmic.c // // This file contains the OAL support code for the PMIC interface. // //----------------------------------------------------------------------------- #include #include "regs.h" #include "regs_regulator.h" //----------------------------------------------------------------------------- // External Functions extern VOID OALClockSetGatingMode(DDK_CLOCK_GATE_INDEX index, DDK_CLOCK_GATE_MODE mode); //----------------------------------------------------------------------------- // External Variables extern PCSP_EPIT_REG g_pEPIT; extern PCSP_IOMUX_REGS g_pIOMUX; extern BOOL g_oalPostInit; extern CRITICAL_SECTION g_oalPmicMutex; //----------------------------------------------------------------------------- // Defines #define CSPI_MAX_DIV 9 // 2^9= 512 #define PMIC_SPI_DATA_LSH 0 #define PMIC_SPI_NULL_LSH 24 #define PMIC_SPI_ADDR_LSH 25 #define PMIC_SPI_RW_LSH 31 #define PMIC_SPI_DATA_WID 24 #define PMIC_SPI_NULL_WID 1 #define PMIC_SPI_ADDR_WID 6 #define PMIC_SPI_RW_WID 1 #define PMIC_SPI_RW_READ 0 #define PMIC_SPI_RW_WRITE 1 //----------------------------------------------------------------------------- // Types //----------------------------------------------------------------------------- // Global Variables //----------------------------------------------------------------------------- // Local Variables static PCSP_CSPI_REG g_pCSPI; static UINT32 g_INTREG; static DDK_CLOCK_GATE_INDEX g_CGI; //----------------------------------------------------------------------------- // Functions //----------------------------------------------------------------------------- // // Function: OALPmicLock // // Obtains a lock for the CSPI hardware so that the OAL and PMIC core driver // can safely share access. OALPmicUnlock() must be called upon completion // of the CSPI transaction. // // Parameters: // None. // // Returns: // None. // //----------------------------------------------------------------------------- static void OALPmicLock(void) { // There is no need to acquire a critical section before accessing the // CSPI bus if the OAL is still in the initialization stage since we // are guaranteed that no other PMIC device drivers will be running yet. if (g_oalPostInit) { // Must ensure exclusive access to the CSPI bus for the OAL until // the current CSPI transaction is completed. EnterCriticalSection(&g_oalPmicMutex); } OALClockSetGatingMode(g_CGI, DDK_CLOCK_GATE_MODE_ENABLED_ALL); INSREG32BF(&g_pCSPI->CONREG, CSPI_CONREG_EN, CSPI_CONREG_EN_ENABLE); // Store the current INTREG configuration and turn off all interrupts. g_INTREG = INREG32(&g_pCSPI->INTREG); OUTREG32(&g_pCSPI->INTREG, 0); } //----------------------------------------------------------------------------- // // Function: OALPmicUnlock // // Release the lock previously obtained by OALPmicLock. // // Parameters: // None. // // Returns: // None. // //----------------------------------------------------------------------------- static void OALPmicUnlock(void) { // Restore INTREG configuration. OUTREG32(&g_pCSPI->INTREG, g_INTREG); INSREG32BF(&g_pCSPI->CONREG, CSPI_CONREG_EN, CSPI_CONREG_EN_DISABLE); OALClockSetGatingMode(g_CGI, DDK_CLOCK_GATE_MODE_DISABLED); if (g_oalPostInit) { // The current CSPI transaction has been completed. Other PMIC // device drivers or the OAL may now access the CSPI bus. LeaveCriticalSection(&g_oalPmicMutex); } } //----------------------------------------------------------------------------- // // Function: OALPmicCalcDiv // // Calculates the CSPI data rate divider needed to obtain the specified // data transfer frequency. // // Parameters: // freq // [in] Target CSPI bit clock frequency. // // Returns: // Calculated divider for the CSPI DATARATE bits. // //----------------------------------------------------------------------------- static UINT32 OALPmicCalcDiv(UINT32 freq) { UINT32 div; UINT32 cspiClk; // CSPI uses IPG_CLK as clock input cspiClk = ((BSP_ARGS *)IMAGE_SHARE_ARGS_UA_START)->clockFreq[DDK_CLOCK_SIGNAL_IPG]; for (div = 2; (div < CSPI_MAX_DIV) && ((cspiClk >> div) > freq); div++); return div - 2; } //----------------------------------------------------------------------------- // // Function: OALPmicExchange // // Performs a data exchange with the PMIC. // // Parameters: // packet // [in] Read/Write packet sent to the PMIC // // data // [in] data read from the exchange // // Returns: // Returns TRUE if successful, otherwise returns FALSE. // //----------------------------------------------------------------------------- static BOOL OALPmicExchange(UINT32 packet, PUINT32 pData) { // Write the packet to the CSPI TXFIFO. OUTREG32(&g_pCSPI->TXDATA, packet); // Start the CSPI exchange. INSREG32BF(&g_pCSPI->CONREG, CSPI_CONREG_XCH, CSPI_CONREG_XCH_EN); // Poll until the CSPI transaction is complete. while (!(INREG32(&g_pCSPI->STATREG) & CSP_BITFMASK(CSPI_STATREG_RR))) { if (g_oalPostInit) { // WinCE 6.00 does not implement the SC_Sleep() API that was // available in WinCE 5.00 and there is no suitable alternative // API. Note that calling NKSleep(0) simply causes this thread // to hang. Therefore, we can only use a NO-OP here. ; } } // Read the data. *pData = INREG32(&g_pCSPI->RXDATA); return TRUE; } //----------------------------------------------------------------------------- // // Function: OALPmicWrite // // Writes data to the specified PMIC register address. // // Parameters: // addr // [in] PMIC register address // // data // [in] data to write // // Returns: // Returns TRUE if successful, otherwise returns FALSE. // //----------------------------------------------------------------------------- BOOL OALPmicWrite(UINT32 addr, UINT32 data) { BOOL rc; UINT32 temp; UINT32 packet = (UINT32) CSP_BITFVAL(PMIC_SPI_RW, PMIC_SPI_RW_WRITE); CSP_BITFINS(packet, PMIC_SPI_DATA, data); CSP_BITFINS(packet, PMIC_SPI_ADDR, addr); // Transfer the packet and discard the data OALPmicLock(); rc = OALPmicExchange(packet, &temp); OALPmicUnlock(); return rc; } //----------------------------------------------------------------------------- // // Function: OALPmicRead // // Reads data from the specified PMIC register address. // // Parameters: // addr // [in] PMIC register address // // data // [out] data read // // Returns: // Returns TRUE if successful, otherwise returns FALSE. // //----------------------------------------------------------------------------- BOOL OALPmicRead(UINT32 addr, PUINT32 pData) { BOOL rc; UINT32 packet = CSP_BITFVAL(PMIC_SPI_RW, PMIC_SPI_RW_READ); CSP_BITFINS(packet, PMIC_SPI_ADDR, addr); // Transfer the packet and read the data OALPmicLock(); rc = OALPmicExchange(packet, pData); OALPmicUnlock(); return rc; } //----------------------------------------------------------------------------- // // Function: OALPmicWriteMasked // // Writes data to particular set of bits within a specified PMIC register // address. // // Parameters: // addr // [in] PMIC register address // // mask // [in] Bit mask for specifying the bits to be written // // data // [in] data to write // // Returns: // Returns TRUE if successful, otherwise returns FALSE. // //----------------------------------------------------------------------------- BOOL OALPmicWriteMasked(UINT32 addr, UINT32 mask, UINT32 data) { BOOL rc = FALSE; UINT32 temp; UINT32 packet = CSP_BITFVAL(PMIC_SPI_RW, PMIC_SPI_RW_READ); CSP_BITFINS(packet, PMIC_SPI_ADDR, addr); // Transfer the packet and read the data OALPmicLock(); if (!OALPmicExchange(packet, &temp)) { ERRORMSG(TRUE, (_T("OALPmicExchange failed\r\n"))); goto cleanUp; } CSP_BITFINS(packet, PMIC_SPI_RW, PMIC_SPI_RW_WRITE); CSP_BITFINS(packet, PMIC_SPI_DATA, (temp & (~mask)) | (data & mask)); // Transfer the packet and discard the data. if (!OALPmicExchange(packet, &temp)) { ERRORMSG(TRUE, (_T("OALPmicExchange failed\r\n"))); goto cleanUp; } rc = TRUE; cleanUp: OALPmicUnlock(); return rc; } //----------------------------------------------------------------------------- // // Function: OALPmicSetSupplyVoltages // // Configures the normal and standby voltages for the CPU. // // Parameters: // mVnormal // [in] Voltage in mV for PMIC normal (non-DVS) voltage // // mVstandby // [in] Voltage in mV for PMIC standby voltage // // mVpll // [in] Voltage in mV for PLL voltage // // Returns: // Returns TRUE if successful, otherwise returns FALSE. // //----------------------------------------------------------------------------- BOOL OALPmicSetSupplyVoltages(UINT32 mVnormal, UINT32 mVstandby, UINT32 mVpll) { BOOL rc = FALSE; DWORD dwStart; UNREFERENCED_PARAMETER(mVpll); // Calculate MC13783 CPU voltage codes //UINT32 voltCodeNormal = (mVnormal - 900) / 25; //UINT32 voltCodeStandby = (mVstandby - 900) / 25; //UINT32 voltCodePll; // Update the voltage setpoints if (!OALPmicWriteMasked(MC13783_SW0_ADDR, CSP_BITFMASK(MC13783_SW0_SW1A) | CSP_BITFMASK(MC13783_SW0_SW1ASTBY), CSP_BITFVAL(MC13783_SW0_SW1A, mVnormal) | CSP_BITFVAL(MC13783_SW0_SW1ASTBY, mVstandby))) { OALMSG(OAL_ERROR, (_T("OALPmicWriteMasked: write to MC13783_SW0_ADDR failed\r\n"))); goto cleanUp; } /* // Calculate MC13783 PLL voltage code if (mVpll <= 1200) { voltCodePll = 0; } else if (mVpll <= 1300) { voltCodePll = 1; } else if (mVpll <= 1500) { voltCodePll = 2; } else { voltCodePll = 3; } // Update PLL voltage if (!OALPmicWriteMasked(MC13783_REG_SET0_ADDR, CSP_BITFMASK(MC13783_REG_SET0_VDIG), CSP_BITFVAL(MC13783_REG_SET0_VDIG, voltCodePll))) { OALMSG(OAL_ERROR, (_T("OALPmicWriteMasked: write to MC13783_REG_SET0_ADDR failed\r\n"))); goto cleanUp; } */ // Wait ~1 msec for the supply voltage to settle dwStart = INREG32(&g_pEPIT->CNT); while((INT32) (dwStart - INREG32(&g_pEPIT->CNT) - g_oalTimer.countsPerMSec) < 0); rc = TRUE; cleanUp: return rc; } //------------------------------------------------------------------------------ // // Function: OALPmicDumpRegister // // Dump all PMIC register data. // // Parameters: // None // // Returns: // Returns TRUE if successful, otherwise returns FALSE. // //------------------------------------------------------------------------------ BOOL OALPmicDumpRegister(void) { BOOL rc; DWORD dwRegisterIndex, pdwRegisterData[8]; DWORD ii; OALMSGS(OAL_FUNC, (__WFUNCTION__ L"+\r\n")); for (dwRegisterIndex=0; dwRegisterIndex<64; dwRegisterIndex+=ARRAYSIZE(pdwRegisterData)) { for (ii=0; iiCONREG, CSP_BITFVAL(CSPI_CONREG_EN, CSPI_CONREG_EN_ENABLE) | CSP_BITFVAL(CSPI_CONREG_MODE, CSPI_CONREG_MODE_MASTER) | CSP_BITFVAL(CSPI_CONREG_XCH, CSPI_CONREG_XCH_IDLE) | CSP_BITFVAL(CSPI_CONREG_SMC, CSPI_CONREG_SMC_XCH) | CSP_BITFVAL(CSPI_CONREG_POL, CSPI_CONREG_POL_ACTIVE_HIGH) | CSP_BITFVAL(CSPI_CONREG_PHA, CSPI_CONREG_PHA0) | CSP_BITFVAL(CSPI_CONREG_SSCTL, CSPI_CONREG_SSCTL_ASSERT) | CSP_BITFVAL(CSPI_CONREG_SSPOL, CSPI_CONREG_SSPOL_ACTIVE_HIGH) | CSP_BITFVAL(CSPI_CONREG_BITCOUNT, CSPI_CONREG_BITCOUNT_32BIT) | CSP_BITFVAL(CSPI_CONREG_DATARATE, OALPmicCalcDiv(BSP_PMIC_CSPI_FREQ)) | CSP_BITFVAL(CSPI_CONREG_DRCTL, CSPI_CONREG_DRCTL_DONTCARE) | CSP_BITFVAL(CSPI_CONREG_CHIPSELECT, BSP_PMIC_CSPI_CHIPSEL)); OUTREG32(&g_pCSPI->INTREG, 0); OUTREG32(&g_pCSPI->DMAREG, 0); OUTREG32(&g_pCSPI->TESTREG, 0); // Turn the CSPI module and clocks off to save power between transfers INSREG32BF(&g_pCSPI->CONREG, CSPI_CONREG_EN, CSPI_CONREG_EN_DISABLE); OALClockSetGatingMode(g_CGI, DDK_CLOCK_GATE_MODE_DISABLED); // Configure muxing for IPP_PMIC_INT (PWRREADY) pin #if (GET_GPIOPINNAME_PORT(PMIC_PWRRDY) == 1) && (GET_GPIOPINNAME_PIN(PMIC_PWRRDY) == 5) OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_GPIO1_5, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC); #else #error PMIC_PWRRDY must be MCU1_5 #endif // Configure muxing for PWGTx pin OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_VPG0, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_NONE); OAL_IOMUX_SET_MUX(g_pIOMUX, DDK_IOMUX_PIN_VPG1, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_NONE); #if 1 OALPmicDumpRegister(); #endif g_pBspArgs = (BSP_ARGS *) OALPAtoUA(IMAGE_SHARE_ARGS_RAM_PA_START); if (g_pBspArgs == NULL) { OALMSG(OAL_ERROR, (L"ERROR: OALPAtoUA failed for BSP_ARGS\r\n")); return FALSE; } //Check PmPowerPolicyEnable = ((g_pBspArgs->BSTAT2) & BSP_PBC_DSW_PMX)? FALSE: TRUE; if(PmPowerPolicyEnable == FALSE) { //OALMSGS(1, (_T("Power Policy disable !!!!\r\n"))); // // SW4 // //SW1AMODE = 0x01 on //SW1ASTBYMODE = 0x11 low power // //SW3(VBOOST) Standby OALPmicWriteMasked(MC13783_SW4_ADDR, CSP_BITFMASK(MC13783_SW4_SW1AMODE) | CSP_BITFMASK(MC13783_SW4_SW1ASTBYMODE), CSP_BITFVAL(MC13783_SW4_SW1AMODE, 0x1) | CSP_BITFVAL(MC13783_SW4_SW1ASTBYMODE, 0x3)); // // SW5 // //SW2AMODE = 0x01 on //SW2ASTBYMODE = 0x11 low power //SW2BMODE = 0x01 on //SW2BSTBYMODE = 0x00 off // //SW3(VBOOST) Standby OALPmicWriteMasked(MC13783_SW5_ADDR, CSP_BITFMASK(MC13783_SW5_SW2AMODE) | CSP_BITFMASK(MC13783_SW5_SW2ASTBYMODE) | CSP_BITFMASK(MC13783_SW5_SW2BMODE) | CSP_BITFMASK(MC13783_SW5_SW2BSTBYMODE) | CSP_BITFMASK(MC13783_SW5_SW3EN), CSP_BITFVAL(MC13783_SW5_SW2AMODE, 0x1) | CSP_BITFVAL(MC13783_SW5_SW2ASTBYMODE, 0x3) | CSP_BITFVAL(MC13783_SW5_SW2BMODE, 0x1) | CSP_BITFVAL(MC13783_SW5_SW2BSTBYMODE, 0x3) | CSP_BITFVAL(MC13783_SW5_SW3EN, TRUE)); //Close that no used regulator OALPmicWriteMasked(MC13783_REG_MOD0_ADDR, CSP_BITFMASK(MC13783_REG_MODE0_VAUDIOSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VAUDIOEN) | CSP_BITFMASK(MC13783_REG_MODE0_VIOHISTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VIOHIEN) | CSP_BITFMASK(MC13783_REG_MODE0_VIOLOSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VIOLOEN) | CSP_BITFMASK(MC13783_REG_MODE0_VDIGSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VDIGEN) | CSP_BITFMASK(MC13783_REG_MODE0_VGENSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VGENEN) | CSP_BITFMASK(MC13783_REG_MODE0_VRFDIGSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VRFDIGEN) | CSP_BITFMASK(MC13783_REG_MODE0_VRFREFSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VRFREFEN) | CSP_BITFMASK(MC13783_REG_MODE0_VRFCPSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VRFCPEN), CSP_BITFVAL(MC13783_REG_MODE0_VAUDIOEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VAUDIOSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VIOHIEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VIOHISTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VIOLOEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VIOLOSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VDIGEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VDIGSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VGENEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VGENSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFDIGEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFDIGSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFREFEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFREFSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFCPEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFCPSTBY, FALSE)); OALPmicWriteMasked(MC13783_REG_MOD1_ADDR, CSP_BITFMASK(MC13783_REG_MODE1_VSIMEN) | CSP_BITFMASK(MC13783_REG_MODE1_VSIMSTBY) | CSP_BITFMASK(MC13783_REG_MODE1_VESIMEN) | CSP_BITFMASK(MC13783_REG_MODE1_VESIMSTBY) | CSP_BITFMASK(MC13783_REG_MODE1_VCAMEN) | CSP_BITFMASK(MC13783_REG_MODE1_VCAMSTBY) | CSP_BITFMASK(MC13783_REG_MODE1_VRFBGEN) | CSP_BITFMASK(MC13783_REG_MODE1_VRFBGSTBY) | CSP_BITFMASK(MC13783_REG_MODE1_VVIBEN) | CSP_BITFMASK(MC13783_REG_MODE1_VRF1EN) | CSP_BITFMASK(MC13783_REG_MODE1_VRF1STBY) | CSP_BITFMASK(MC13783_REG_MODE1_VRF2EN) | CSP_BITFMASK(MC13783_REG_MODE1_VRF2STBY) | CSP_BITFMASK(MC13783_REG_MODE1_VMMC1EN)| CSP_BITFMASK(MC13783_REG_MODE1_VMMC1STBY) | CSP_BITFMASK(MC13783_REG_MODE1_VMMC2EN)| CSP_BITFMASK(MC13783_REG_MODE1_VMMC2STBY), CSP_BITFVAL(MC13783_REG_MODE1_VSIMEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VSIMSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VESIMEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VESIMSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VCAMEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VCAMSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VRFBGEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VRFBGSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VVIBEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VRF1EN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VRF1STBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VRF2EN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VRF2STBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VMMC1EN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VMMC1STBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VMMC2EN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VMMC2STBY, TRUE)); // //Reg34 Power Miscellaneous // //Enable GPO3 OALPmicWriteMasked(MC13783_PWR_MISC_ADDR, 0xFFFFFF, CSP_BITFVAL(MC13783_REG_MISC_GPO3EN,TRUE) | CSP_BITFVAL(MC13783_REG_MISC_GPO3STBY,TRUE)); for(i=0; i < 100; i++) { // Wait ~1 msec for MC13783_PWR_MISC_ADDR setting settle dwStart = INREG32(&g_pEPIT->CNT); while((INT32) (dwStart - INREG32(&g_pEPIT->CNT) - g_oalTimer.countsPerMSec) < 0); } //Enable GPO3,1 OALPmicWriteMasked(MC13783_PWR_MISC_ADDR, 0xFFFFFF, CSP_BITFVAL(MC13783_REG_MISC_GPO1EN,TRUE) | CSP_BITFVAL(MC13783_REG_MISC_GPO1STBY,TRUE) | CSP_BITFVAL(MC13783_REG_MISC_GPO3EN,TRUE) | CSP_BITFVAL(MC13783_REG_MISC_GPO3STBY,TRUE) | CSP_BITFVAL(MC13783_REG_MISC_GPO2EN,TRUE) | CSP_BITFVAL(MC13783_REG_MISC_GPO2STBY,TRUE)); } else { //OALMSGS(1, (_T("Power Police Enable !!!!!\r\n"))); // // SW4 // //SW1AMODE = 0x01 on //SW1ASTBYMODE = 0x11 low power // //SW3(VBOOST) Standby OALPmicWriteMasked(MC13783_SW4_ADDR, CSP_BITFMASK(MC13783_SW4_SW1AMODE) | CSP_BITFMASK(MC13783_SW4_SW1ASTBYMODE), CSP_BITFVAL(MC13783_SW4_SW1AMODE, 0x1) | CSP_BITFVAL(MC13783_SW4_SW1ASTBYMODE, 0x3)); // // SW5 // //SW2AMODE = 0x01 on //SW2ASTBYMODE = 0x3 low power //SW2BMODE = 0x01 on //SW2BSTBYMODE = 0x00 off // //SW3(VBOOST) Standby OALPmicWriteMasked(MC13783_SW5_ADDR, CSP_BITFMASK(MC13783_SW5_SW2AMODE) | CSP_BITFMASK(MC13783_SW5_SW2ASTBYMODE) | CSP_BITFMASK(MC13783_SW5_SW2BMODE) | CSP_BITFMASK(MC13783_SW5_SW2BSTBYMODE) | CSP_BITFMASK(MC13783_SW5_SW3EN), CSP_BITFVAL(MC13783_SW5_SW2AMODE, 0x1) | CSP_BITFVAL(MC13783_SW5_SW2ASTBYMODE, 0x3) | CSP_BITFVAL(MC13783_SW5_SW2BMODE, 0x1) | CSP_BITFVAL(MC13783_SW5_SW2BSTBYMODE, 0x3) | CSP_BITFVAL(MC13783_SW5_SW3EN, FALSE)); // All Regulators stby on //VCAM, VESIM, VSIM, VRFREF, VRF1, VRF2, VRFCP, VRFBG not useed in 3-stack board //VVIB only for CMOSE. //VGEN only for LCD, //VMMC2 only for SD1 //VIOLO must keep votage in suspend mode OALPmicWriteMasked(MC13783_REG_MOD0_ADDR, CSP_BITFMASK(MC13783_REG_MODE0_VAUDIOSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VAUDIOEN) | CSP_BITFMASK(MC13783_REG_MODE0_VIOHISTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VIOHIEN) | CSP_BITFMASK(MC13783_REG_MODE0_VIOLOSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VIOLOEN) | CSP_BITFMASK(MC13783_REG_MODE0_VDIGSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VDIGEN) | CSP_BITFMASK(MC13783_REG_MODE0_VGENSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VGENEN) | CSP_BITFMASK(MC13783_REG_MODE0_VRFDIGSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VRFDIGEN) | CSP_BITFMASK(MC13783_REG_MODE0_VRFREFSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VRFREFEN) | CSP_BITFMASK(MC13783_REG_MODE0_VRFCPSTBY) | CSP_BITFMASK(MC13783_REG_MODE0_VRFCPEN) , CSP_BITFVAL(MC13783_REG_MODE0_VAUDIOEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VAUDIOSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VIOHIEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VIOHISTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VIOLOEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VIOLOSTBY, FALSE) | //For Touch/PMIC suspend wakeup CSP_BITFVAL(MC13783_REG_MODE0_VDIGEN, TRUE) | //check if we can disable CSP_BITFVAL(MC13783_REG_MODE0_VDIGSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VGENEN, TRUE) | //check if we can disable CSP_BITFVAL(MC13783_REG_MODE0_VGENSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFDIGEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFDIGSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFREFEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFREFSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFCPEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE0_VRFCPSTBY, FALSE)); OALPmicWriteMasked(MC13783_REG_MOD1_ADDR, CSP_BITFMASK(MC13783_REG_MODE1_VSIMEN) | CSP_BITFMASK(MC13783_REG_MODE1_VSIMSTBY) | CSP_BITFMASK(MC13783_REG_MODE1_VESIMEN) | CSP_BITFMASK(MC13783_REG_MODE1_VESIMSTBY) | CSP_BITFMASK(MC13783_REG_MODE1_VCAMEN) | CSP_BITFMASK(MC13783_REG_MODE1_VCAMSTBY) | CSP_BITFMASK(MC13783_REG_MODE1_VRFBGEN) | CSP_BITFMASK(MC13783_REG_MODE1_VRFBGSTBY) | CSP_BITFMASK(MC13783_REG_MODE1_VVIBEN) | CSP_BITFMASK(MC13783_REG_MODE1_VRF1EN) | CSP_BITFMASK(MC13783_REG_MODE1_VRF1STBY) | CSP_BITFMASK(MC13783_REG_MODE1_VRF2EN) | CSP_BITFMASK(MC13783_REG_MODE1_VRF2STBY) | CSP_BITFMASK(MC13783_REG_MODE1_VMMC1EN) | CSP_BITFMASK(MC13783_REG_MODE1_VMMC1STBY) | CSP_BITFMASK(MC13783_REG_MODE1_VMMC2EN)| CSP_BITFMASK(MC13783_REG_MODE1_VMMC2STBY), CSP_BITFVAL(MC13783_REG_MODE1_VSIMEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VSIMSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VESIMEN, TRUE) | //check if we can disable CSP_BITFVAL(MC13783_REG_MODE1_VESIMSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VCAMEN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VCAMSTBY, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VRFBGEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VRFBGSTBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VVIBEN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VRF1EN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VRF1STBY, FALSE) | //For Touch/PMIC suspend wakeup CSP_BITFVAL(MC13783_REG_MODE1_VRF2EN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VRF2STBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VMMC1EN, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VMMC1STBY, FALSE) | CSP_BITFVAL(MC13783_REG_MODE1_VMMC2EN, TRUE) | CSP_BITFVAL(MC13783_REG_MODE1_VMMC2STBY, TRUE)); OALPmicWriteMasked(MC13783_PWR_MISC_ADDR, 0xFFFFFF, CSP_BITFVAL(MC13783_REG_MISC_GPO1EN,FALSE) | CSP_BITFVAL(MC13783_REG_MISC_GPO2EN,FALSE) | CSP_BITFVAL(MC13783_REG_MISC_GPO3EN,FALSE)); //REG 36, Audio RX0 OALPmicWriteMasked(MC13783_AUD_RX0_ADDR, CSP_BITFMASK(MC13783_REG_AUDIORX0_VAUDIOON), CSP_BITFVAL(MC13783_REG_AUDIORX0_VAUDIOON, 0)); } rc = OALPmicSetSupplyVoltages(mVnormal, mVstandby, mVpll); OALMSG(OAL_INFO, (L"\r\n")); OALMSG(OAL_INFO, (L" ----------------------------------------- \r\n")); OALMSG(OAL_INFO, (L" iMX31 PMIC Information \r\n")); OALMSG(OAL_INFO, (L" ....................................... \r\n")); #ifdef DEBUG OALPmicRead(MC13783_SW0_ADDR, &temp); OALMSGS(OAL_INFO, (_T(" SW1A voltages: 0x%x \r\n") _T(" (normal = %d, DVS = %d, standby = %d)\r\n"), temp, CSP_BITFEXT(temp, MC13783_SW0_SW1A), CSP_BITFEXT(temp, MC13783_SW0_SW1A), CSP_BITFEXT(temp, MC13783_SW0_SW1ASTBY))); OALPmicRead(MC13783_SW4_ADDR, &temp); OALMSGS(OAL_INFO, (_T(" SW1A configuration: 0x%x \r\n") _T(" (mode = %d, standby mode = %d, DVS speed = %d, \r\n") _T(" panic = %d, soft start = %d)\r\n"), temp, CSP_BITFEXT(temp, MC13783_SW4_SW1AMODE), CSP_BITFEXT(temp, MC13783_SW4_SW1ASTBYMODE), CSP_BITFEXT(temp, MC13783_SW4_SW1ADVSSPEED), CSP_BITFEXT(temp, MC13783_SW4_SW1APANIC), CSP_BITFEXT(temp, MC13783_SW4_SW1ASFST))); OALPmicRead(MC13783_REG_MOD0_ADDR, &temp); OALMSGS(OAL_INFO, (_T(" Linears1 configuration: 0x%08x \r\n"),temp)); OALMSGS(OAL_INFO, (_T(" VAUDIO en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE0_VAUDIOEN), CSP_BITFEXT(temp, MC13783_REG_MODE0_VAUDIOSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE0_VAUDIOMODE))); OALMSGS(OAL_INFO, (_T(" VIOHI en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE0_VIOHIEN), CSP_BITFEXT(temp, MC13783_REG_MODE0_VIOHISTBY), CSP_BITFEXT(temp, MC13783_REG_MODE0_VIOHIMODE))); OALMSGS(OAL_INFO, (_T(" VIOLO en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE0_VIOLOEN), CSP_BITFEXT(temp, MC13783_REG_MODE0_VIOLOSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE0_VIOLOMODE))); OALMSGS(OAL_INFO, (_T(" VDIG en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE0_VDIGEN), CSP_BITFEXT(temp, MC13783_REG_MODE0_VDIGSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE0_VDIGMODE))); OALMSGS(OAL_INFO, (_T(" VGEN en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE0_VGENEN), CSP_BITFEXT(temp, MC13783_REG_MODE0_VGENSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE0_VGENMODE))); OALMSGS(OAL_INFO, (_T(" VRFDIG en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFDIGEN), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFDIGSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFDIGMODE))); OALMSGS(OAL_INFO, (_T(" VRFREF en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFREFEN), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFREFSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFREFMODE))); OALMSGS(OAL_INFO, (_T(" VRFCP en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFCPEN), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFCPSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE0_VRFCPMODE))); OALPmicRead(MC13783_REG_MOD1_ADDR, &temp); OALMSGS(OAL_INFO, (_T(" Linears2 configuration: 0x%08x \r\n"),temp)); OALMSGS(OAL_INFO, (_T(" VSIM en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VSIMEN), CSP_BITFEXT(temp, MC13783_REG_MODE1_VSIMSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE1_VSIMMODE))); OALMSGS(OAL_INFO, (_T(" VESIM en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VESIMEN), CSP_BITFEXT(temp, MC13783_REG_MODE1_VESIMSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE1_VESIMMODE))); OALMSGS(OAL_INFO, (_T(" VCAM en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VCAMEN), CSP_BITFEXT(temp, MC13783_REG_MODE1_VCAMSTBY), CSP_BITFEXT(temp, MC13783_REG_MODE1_VCAMMODE))); OALMSGS(OAL_INFO, (_T(" VRFBG en = %d, standby mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VRFBGEN), CSP_BITFEXT(temp, MC13783_REG_MODE1_VRFBGSTBY))); OALMSGS(OAL_INFO, (_T(" VVIB en = %d,\r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VVIBEN))); OALMSGS(OAL_INFO, (_T(" VRF1 en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VRF1EN), CSP_BITFEXT(temp, MC13783_REG_MODE1_VRF1STBY), CSP_BITFEXT(temp, MC13783_REG_MODE1_VRF1MODE))); OALMSGS(OAL_INFO, (_T(" VRF2 en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VRF2EN), CSP_BITFEXT(temp, MC13783_REG_MODE1_VRF2STBY), CSP_BITFEXT(temp, MC13783_REG_MODE1_VRF2MODE))); OALMSGS(OAL_INFO, (_T(" VMMC1 en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VMMC1EN), CSP_BITFEXT(temp, MC13783_REG_MODE1_VMMC1STBY), CSP_BITFEXT(temp, MC13783_REG_MODE1_VMMC1MODE))); OALMSGS(OAL_INFO, (_T(" VMMC2 en = %d, standby mode = %d, mode = %d, \r\n"), CSP_BITFEXT(temp, MC13783_REG_MODE1_VMMC2EN), CSP_BITFEXT(temp, MC13783_REG_MODE1_VMMC2STBY), CSP_BITFEXT(temp, MC13783_REG_MODE1_VMMC2MODE))); #else OALMSG(OAL_INFO, (L" Information Available in Debug Build \r\n")); #endif //#ifdef DEBUG OALMSG(1, (L" ----------------------------------------- \r\n")); cleanUp: OALMSG(OAL_FUNC, (__WFUNCTION__ L"-\r\n")); return rc; }