 
cpldfit:  version E.32                              Xilinx Inc.
                                  Fitter Report
Design Name: q_decode                            Date: 12-27-2001,  4:11PM
Device Used: XCR3064XL-6-VQ44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
1  /64  (  1%) 2   /192  (  1%) 0  /64  (  0%) 6  /32  ( 18%) 5  /160 (  3%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    5           5    |  I/O              :     6       22
Output        :    1           1    |  GCK/IO           :     0        4
Bidirectional :    0           0    |  
GCK           :    0           0    |  
                 ----        ----
        Total      6           6  

MACROCELL RESOURCES:

Total Macrocells Available                    64
Registered Macrocells                          0
Non-registered Macrocell driving I/O           1

GLOBAL RESOURCES:

Global clock net(s) unused.
Universal Control Terms (Used/Available)                  : 0/4

BLOCK RESOURCES:

Total Function Block Local Control Terms (Used/Available) : 0/32
Total Foldback NANDs (Used/Available)                     : 0/32

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total Signals Loc     Slew Pin  Pin       Pin          
Name                Pt    Used            Rate #    Type      Use          
s3                  3       5     FB1_1   FAST 35   I/O       O

** INPUTS **
Signal                            Loc          Pin  Pin       Pin      I/O 
Name                                           #    Type      Use     Style
a                                 FB1_2        34   I/O       I                  
b                                 FB1_8        33   I/O       I                  
s1                                FB1_10       31   I/O       I                  
s2                                FB1_11       30   I/O       I                  
s4                                FB1_14       28   I/O       I                  

End of Resources Used by Successfully Mapped Logic

Legend: PU  - Pull Up
*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           1           5           5            2         1/0        7   
FB2           0           0           0            0         0/0        7   
FB3           0           0           0            0         0/0        7   
FB4           0           0           0            0         0/0        7   
            ----                                -----       -----     ----- 
              1                                    2         1/0       28   
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block:  5
Number of function block inputs used/remaining:               5/35
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   2/46
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
s3                                  3    FB1_1      35   I/O     O
(unused)                            0    FB1_2      34   I/O     I
(unused)                            0    FB1_3           (b)      
(unused)                            0    FB1_4           (b)      
(unused)                            0    FB1_5           (b)      
(unused)                            0    FB1_6           (b)      
(unused)                            0    FB1_7           (b)      
(unused)                            0    FB1_8      33   I/O     I
(unused)                            0    FB1_9      32TDO/I/O      
(unused)                            0    FB1_10     31   I/O     I
(unused)                            0    FB1_11     30   I/O     I
(unused)                            0    FB1_12          (b)      
(unused)                            0    FB1_13          (b)      
(unused)                            0    FB1_14     28   I/O     I
(unused)                            0    FB1_15     27   I/O      
(unused)                            0    FB1_16          (b)      

Signals Used by Logic in Function Block
  1: a                  3: s1                 5: s4 
  2: b                  4: s2               

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
s3                XXXXX................................... 5       5
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB2_1      42   I/O      
(unused)                            0    FB2_2      43   I/O      
(unused)                            0    FB2_3      44   I/O      
(unused)                            0    FB2_4           (b)      
(unused)                            0    FB2_5           (b)      
(unused)                            0    FB2_6           (b)      
(unused)                            0    FB2_7           (b)      
(unused)                            0    FB2_8           (b)      
(unused)                            0    FB2_9       1TDI/I/O      
(unused)                            0    FB2_10      2   I/O      
(unused)                            0    FB2_11      3   I/O      
(unused)                            0    FB2_12          (b)      
(unused)                            0    FB2_13          (b)      
(unused)                            0    FB2_14      5   I/O      
(unused)                            0    FB2_15      6   I/O      
(unused)                            0    FB2_16          (b)      
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB3_1      26TCK/I/O      
(unused)                            0    FB3_2      25   I/O      
(unused)                            0    FB3_3           (b)      
(unused)                            0    FB3_4      23   I/O      
(unused)                            0    FB3_5           (b)      
(unused)                            0    FB3_6           (b)      
(unused)                            0    FB3_7           (b)      
(unused)                            0    FB3_8           (b)      
(unused)                            0    FB3_9      22   I/O      
(unused)                            0    FB3_10     21   I/O      
(unused)                            0    FB3_11     20   I/O      
(unused)                            0    FB3_12     19   I/O      
(unused)                            0    FB3_13     18   I/O      
(unused)                            0    FB3_14          (b)      
(unused)                            0    FB3_15          (b)      
(unused)                            0    FB3_16          (b)      
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB4_1       7TMS/I/O      
(unused)                            0    FB4_2       8   I/O      
(unused)                            0    FB4_3           (b)      
(unused)                            0    FB4_4      10   I/O      
(unused)                            0    FB4_5      11   I/O      
(unused)                            0    FB4_6           (b)      
(unused)                            0    FB4_7           (b)      
(unused)                            0    FB4_8           (b)      
(unused)                            0    FB4_9      12   I/O      
(unused)                            0    FB4_10     13   I/O      
(unused)                            0    FB4_11     14   I/O      
(unused)                            0    FB4_12     15   I/O      
(unused)                            0    FB4_13          (b)      
(unused)                            0    FB4_14          (b)      
(unused)                            0    FB4_15          (b)      
(unused)                            0    FB4_16          (b)      
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.

 s3 = /a * /b * s1 * /s2 * /s4
	+ /a * /b * /s1 * s2 * s4

****************************  Device Pin Out ****************************

Device : XCR3064XL-6-VQ44


         T        V     W  T  W  G  W  
         D  s  s  C  s  P  C  P  N  P  
      b  O  1  2  C  4  U  K  U  D  U  
      --------------------------------  
     /33 32 31 30 29 28 27 26 25 24 23 \
  a | 34                            22 | WPU
 s3 | 35                            21 | WPU
GND | 36                            20 | WPU
WPU | 37                            19 | WPU
WPU | 38       XCR3064XL-6-VQ44     18 | WPU
WPU | 39                            17 | VCC
WPU | 40                            16 | GND
VCC | 41                            15 | WPU
WPU | 42                            14 | WPU
WPU | 43                            13 | WPU
WPU | 44                            12 | WPU
    \ 1  2  3  4  5  6  7  8  9  10 11 /
      --------------------------------  
      T  W  W  P  W  W  T  W  V  W  W  
      D  P  P  E  P  P  M  P  C  P  P  
      I  U  U     U  U  S  U  C  U  U  


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused Weak Pull Up
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XCR3064XL-6-VQ44
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Reserve JTAG Port Pins for ISP              : ON
Use Fast Input Registers                    : ON
Use Foldback NANDs                          : OFF
Default Register Initial State              : RESET
Output Slew Rate                            : FAST
Optimizing Method                           : DENSITY
Collapsing Pterm Limit                      : 28
Collapsing Input Limit                      : 32
Multi Level Logic Optimization              : ON
Enable WYSIWYG mode                         : OFF
Enable Exhaustive Fitting                   : OFF
