------------------------------------------------------------------
-- Translated VHDL Source File
-- Auto-Generated By Xilinx's Blf2lang.
-- Copyright (c) 2000. Xilinx, Inc.
------------------------------------------------------------------
--q_decode

library IEEE;
use IEEE.std_logic_1164.all;
library aim;
use aim.components.all;
library pls;
use pls.attributes.all;

entity q_decode is
port (
    S2 : in std_logic;
    S1 : in std_logic;
    B : in std_logic;
    A : in std_logic;
    S4 : in std_logic;
    S3 : out std_logic
     );
end q_decode;

architecture equation of q_decode is
    signal S3_xcBUF : std_logic;
    signal vcc : std_logic;
    signal gnd : std_logic;

begin
vcc <= '1';
gnd <= '0';
S3_xcBUF <= (( not(A) and  not(B) and  not(S1) and S2 and S4)
       or  ( not(A) and  not(B) and S1 and  not(S2) and  not(S4)));
S3 <= (S3_xcBUF);

end equation;