MODEL
MODEL_VERSION "v1998.8";
DESIGN "shutter_top";

/* port names and type */
INPUT S:PIN40 = clk;
INPUT S:PIN3 = lo_clear;
INPUT S:PIN2 = lo_read;
INPUT xPUP_0;
INPUT S:PIN35 = b_quad;
INPUT S:PIN34 = a_quad;
TRIOUT S:PIN33 = cpu_data<0>;
TRIOUT S:PIN31 = cpu_data<1>;
TRIOUT S:PIN30 = cpu_data<2>;
TRIOUT S:PIN28 = cpu_data<3>;
TRIOUT S:PIN27 = cpu_data<4>;
TRIOUT S:PIN42 = cpu_data<5>;
TRIOUT S:PIN43 = cpu_data<6>;
TRIOUT S:PIN44 = cpu_data<7>;

/* timing arc definitions */
clk_cpu_data<0>_delay: DELAY (ENABLE_HIGH) clk cpu_data<0>;
clk_cpu_data<1>_delay: DELAY (ENABLE_HIGH) clk cpu_data<1>;
clk_cpu_data<2>_delay: DELAY (ENABLE_HIGH) clk cpu_data<2>;
clk_cpu_data<3>_delay: DELAY (ENABLE_HIGH) clk cpu_data<3>;
clk_cpu_data<4>_delay: DELAY (ENABLE_HIGH) clk cpu_data<4>;
clk_cpu_data<5>_delay: DELAY (ENABLE_HIGH) clk cpu_data<5>;
clk_cpu_data<6>_delay: DELAY (ENABLE_HIGH) clk cpu_data<6>;
clk_cpu_data<7>_delay: DELAY (ENABLE_HIGH) clk cpu_data<7>;

/* timing check arc definitions */
ENDMODEL