Performance Summary Report
                           --------------------------

Design:     shutter_top
Device:     XCR3064XL-6-VQ44
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.32
Date:       Thu Dec 27 15:02:10 2001

Performance Summary: 

Clock net 'clk' path delays:

Clock Pad to Output Pad (tCO)             :         11.9ns (2 macrocell levels)
Clock Pad 'clk' to Output Pad 'cpu_data<0>'                               (GCK)


Setup to Clock at the Pad (tSU)           :          3.5ns (0 macrocell levels)
Data signal 'lo_read' to DFF D input Pin at 'N126.D'
Clock pad 'clk'                                                           (GCK)

                          Minimum Clock Period: 7.4ns
                     Maximum Internal Clock Speed: 135.1Mhz
                            (Limited by Cycle Time)

Clock net 'N109.Q' path delays:

                          Minimum Clock Period: 5.0ns
                     Maximum Internal Clock Speed: 200.0Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From          c
 \              l
  \             k
   \             
    \            
     \           
      \          
       \         
        \        
         \       
          \      
  To       \------

cpu_data<0>  11.9
cpu_data<1>  11.9
cpu_data<2>  11.9
cpu_data<3>  11.9
cpu_data<4>  11.9
cpu_data<5>  11.9
cpu_data<6>  11.9
cpu_data<7>  11.9

--------------------------------------------------------------------------------
                       Setup to Clock at Pad (tSU) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

a_quad    2.5
b_quad    2.5
lo_read   3.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                  (Clock: clk)

\ From            N     N     N     N     N     N     N     N     N     N     N
 \                1     1     1     1     1     1     1     1     1     9     9
  \               0     0     0     0     0     0     0     2     2     5     6
   \              0     1     3     4     5     6     7     6     7     .     .
    \             .     .     .     .     .     .     .     .     .     Q     Q
     \            Q     Q     Q     Q     Q     Q     Q     Q     Q            
      \                                                                        
       \                                                                       
        \                                                                      
         \                                                                     
          \                                                                    
           \                                                                   
            \                                                                  
  To         \------------------------------------------------------------------

FB1__ctinst/4                                                   7.4            
N100.D                                              6.9         6.9   6.9   6.9
N101.D          6.9                                 6.9         6.9   6.9   6.9
N102.D          6.9   6.9                           6.9         6.9   6.9   6.9
N103.D                                  6.4                                    
N104.D                                        6.4                              
N107.D                      6.9   6.9         6.9   6.9                        
N109.D                                                    6.4                  
N127.D                      6.9   6.9   6.9   6.9   6.9                        
N95.D                                                                 6.9      
N96.D                                               6.9         6.9   6.9      
N97.D                                               6.9         6.9   6.9   6.9
N98.D                                               6.9         6.9   6.9   6.9
N99.D                                               6.9         6.9   6.9   6.9

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                  (Clock: clk)

\ From            N     N     N
 \                9     9     9
  \               7     8     9
   \              .     .     .
    \             Q     Q     Q
     \                         
      \                        
       \                       
        \                      
         \                     
          \                    
           \                   
            \                  
  To         \------------------

FB1__ctinst/4                  
N100.D          6.9   6.9   6.9
N101.D          6.9   6.9   6.9
N102.D          6.9   6.9   6.9
N103.D                         
N104.D                         
N107.D                         
N109.D                         
N127.D                         
N95.D                          
N96.D                          
N97.D                          
N98.D           6.9            
N99.D           6.9   6.9      

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.