 
cpldfit:  version E.32                              Xilinx Inc.
                                  Fitter Report
Design Name: shutter_top                         Date:  5-27-2002, 11:21AM
Device Used: XCR3064XL-6-VQ44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
28 /64  ( 43%) 38  /192  ( 19%) 24 /64  ( 37%) 21 /32  ( 65%) 28 /160 ( 17%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    8           8    |  I/O              :    20        8
Output        :   12          12    |  GCK/IO           :     1        3
Bidirectional :    0           0    |  
GCK           :    1           1    |  
                 ----        ----
        Total      21          21 

MACROCELL RESOURCES:

Total Macrocells Available                    64
Registered Macrocells                         24
Non-registered Macrocell driving I/O           4

GLOBAL RESOURCES:

Signal 'clk' mapped onto global clock net GCK1.
Universal Control Terms (Used/Available)                  : 1/3

BLOCK RESOURCES:

Total Function Block Local Control Terms (Used/Available) : 1/32
Total Foldback NANDs (Used/Available)                     : 0/32

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total Signals Loc     Slew Pin  Pin       Pin          
Name                Pt    Used            Rate #    Type      Use          
N121                4       3     FB1_4             (b)       (b)
N122                4       4     FB1_5             (b)       (b)
N123                4       5     FB1_6             (b)       (b)
N124                4       6     FB1_7             (b)       (b)
N125                4       7     FB1_12            (b)       (b)
N126                4       8     FB1_9        32   TDO/I/O   (b)
N127                4       9     FB1_16            (b)       (b)
N128                4       10    FB1_13            (b)       (b)
N129                1       1     FB2_9        1    TDI/I/O   (b)
N130                1       1     FB2_13            (b)       (b)
N131                0       0     FB1_1        35   I/O       
N132                0       0     FB1_2        34   I/O       
N133                4       4     FB1_3             (b)       (b)
N135                1       1     FB2_12            (b)       (b)
N166                3       5     FB2_16            (b)       (b)
N167                1       1     FB2_8             (b)       (b)
a_out               1       2     FB2_10  FAST 2    I/O       O
b_out               1       2     FB2_11  FAST 3    I/O       O
c_out               1       2     FB2_14  FAST 5    I/O       O
cpu_data<0>         3       2     FB1_8   FAST 33   I/O       O
cpu_data<1>         3       2     FB1_10  FAST 31   I/O       O
cpu_data<2>         3       2     FB1_11  FAST 30   I/O       O
cpu_data<3>         3       2     FB1_14  FAST 28   I/O       O
cpu_data<4>         3       2     FB1_15  FAST 27   I/O       O
cpu_data<5>         3       1     FB2_1   FAST 42   I/O       O
cpu_data<6>         3       1     FB2_2   FAST 43   I/O       O
cpu_data<7>         3       1     FB2_3   FAST 44   I/O       O
d_out               1       2     FB2_15  FAST 6    I/O       O

** INPUTS **
Signal                            Loc          Pin  Pin       Pin      I/O 
Name                                           #    Type      Use     Style
a_in                              FB3_2        25   I/O       I                  
a_quad                            FB1_2        34   I/O                          
b_in                              FB3_9        22   I/O       I                  
b_quad                            FB1_1        35   I/O                          
c_in                              FB3_4        23   I/O       I                  
clear_n                           FB3_10       21   I/O       I                  
clk                                            40   GCK       GCK                
d_in                              FB3_11       20   I/O       I                  
read_n                            FB3_12       19   I/O       I                  

End of Resources Used by Successfully Mapped Logic

Legend: PU  - Pull Up
*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          16          14          14           25         5/0        7   
FB2          12          14          14           13         7/0        7   
FB3           0           0           0            0         0/0        7   
FB4           0           0           0            0         0/0        7   
            ----                                -----       -----     ----- 
             28                                   38        12/0       28   
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block:  14
Number of function block inputs used/remaining:               14/26
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  3/5
Number of PLA product terms used/remaining:                   25/23
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
N131                                0    FB1_1      35   I/O      
N132                                0    FB1_2      34   I/O      
N133                                4    FB1_3           (b)   (b)
N121                                4    FB1_4           (b)   (b)
N122                                4    FB1_5           (b)   (b)
N123                                4    FB1_6           (b)   (b)
N124                                4    FB1_7           (b)   (b)
cpu_data<0>                         3    FB1_8      33   I/O     O
N126                                4    FB1_9      32TDO/I/O   (b)
cpu_data<1>                         3    FB1_10     31   I/O     O
cpu_data<2>                         3    FB1_11     30   I/O     O
N125                                4    FB1_12          (b)   (b)
N128                                4    FB1_13          (b)   (b)
cpu_data<3>                         3    FB1_14     28   I/O     O
cpu_data<4>                         3    FB1_15     27   I/O     O
N127                                4    FB1_16          (b)   (b)

Signals Used by Logic in Function Block
  1: N121               6: N126              11: N133 
  2: N122               7: N127              12: N135 
  3: N123               8: N129              13: N166 
  4: N124               9: N130              14: clear_n 
  5: N125              10: N132             

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
N133              .......XXXX............................. 4       4
N121              X...........XX.......................... 3       3
N122              X.........X.XX.......................... 4       4
N123              XX........X.XX.......................... 5       5
N124              XXX.......X.XX.......................... 6       6
cpu_data<0>       X..........X............................ 2       2
N126              XXXXX.....X.XX.......................... 8       8
cpu_data<1>       .X.........X............................ 2       2
cpu_data<2>       ..X........X............................ 2       2
N125              XXXX......X.XX.......................... 7       7
N128              XXXXXXX...X.XX.......................... 10      10
cpu_data<3>       ...X.......X............................ 2       2
cpu_data<4>       ....X......X............................ 2       2
N127              XXXXXX....X.XX.......................... 9       9
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block:  14
Number of function block inputs used/remaining:               14/26
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   13/35
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
cpu_data<5>                         3    FB2_1      42   I/O     O
cpu_data<6>                         3    FB2_2      43   I/O     O
cpu_data<7>                         3    FB2_3      44   I/O     O
(unused)                            0    FB2_4           (b)      
(unused)                            0    FB2_5           (b)      
(unused)                            0    FB2_6           (b)      
(unused)                            0    FB2_7           (b)      
N167                                1    FB2_8           (b)   (b)
N129                                1    FB2_9       1TDI/I/O   (b)
a_out                               1    FB2_10      2   I/O     O
b_out                               1    FB2_11      3   I/O     O
N135                                1    FB2_12          (b)   (b)
N130                                1    FB2_13          (b)   (b)
c_out                               1    FB2_14      5   I/O     O
d_out                               1    FB2_15      6   I/O     O
N166                                3    FB2_16          (b)   (b)

Signals Used by Logic in Function Block
  1: N126               6: N131              11: b_in 
  2: N127               7: N132              12: c_in 
  3: N128               8: N133              13: d_in 
  4: N129               9: N167              14: read_n 
  5: N130              10: a_in             

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
cpu_data<5>       X....................................... 1       1
cpu_data<6>       .X...................................... 1       1
cpu_data<7>       ..X..................................... 1       1
N167              .............X.......................... 1       1
N129              .....X.................................. 1       1
a_out             .........XX............................. 2       2
b_out             .........XX............................. 2       2
N135              ........X............................... 1       1
N130              ......X................................. 1       1
c_out             ...........XX........................... 2       2
d_out             ...........XX........................... 2       2
N166              ...XXXXX................................ 5       5
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB3_1      26TCK/I/O      
(unused)                            0    FB3_2      25   I/O     I
(unused)                            0    FB3_3           (b)      
(unused)                            0    FB3_4      23   I/O     I
(unused)                            0    FB3_5           (b)      
(unused)                            0    FB3_6           (b)      
(unused)                            0    FB3_7           (b)      
(unused)                            0    FB3_8           (b)      
(unused)                            0    FB3_9      22   I/O     I
(unused)                            0    FB3_10     21   I/O     I
(unused)                            0    FB3_11     20   I/O     I
(unused)                            0    FB3_12     19   I/O     I
(unused)                            0    FB3_13     18   I/O      
(unused)                            0    FB3_14          (b)      
(unused)                            0    FB3_15          (b)      
(unused)                            0    FB3_16          (b)      
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block:  0
Number of function block inputs used/remaining:               0/40
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   0/48
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB4_1       7TMS/I/O      
(unused)                            0    FB4_2       8   I/O      
(unused)                            0    FB4_3           (b)      
(unused)                            0    FB4_4      10   I/O      
(unused)                            0    FB4_5      11   I/O      
(unused)                            0    FB4_6           (b)      
(unused)                            0    FB4_7           (b)      
(unused)                            0    FB4_8           (b)      
(unused)                            0    FB4_9      12   I/O      
(unused)                            0    FB4_10     13   I/O      
(unused)                            0    FB4_11     14   I/O      
(unused)                            0    FB4_12     15   I/O      
(unused)                            0    FB4_13          (b)      
(unused)                            0    FB4_14          (b)      
(unused)                            0    FB4_15          (b)      
(unused)                            0    FB4_16          (b)      
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.

/a_out = /b_in * a_in

/b_out = b_in * /a_in

 c_out = /d_in * c_in

 "cpu_data<0>" := N121
    "cpu_data<0>".TRST  =  N135
    "cpu_data<0>".CLKF  =  N135
    "cpu_data<0>".PRLD  =  Gnd

/N121 := N121
    N121.CLKF  =  clk	;GCK
    N121.CE  =  N166
   /N121.RSTF  =  clear_n
    N121.PRLD  =  Gnd

 N166 := N133 * N129 * /N131 * /N130 * /N132
	+ /N133 * /N129 * /N131 * N130 * /N132
    N166.CLKF  =  clk	;GCK
    N166.PRLD  =  Gnd

/N133 := /N133 * N129
	+ /N133 * N130
	+ /N129 * /N130 * /N132
    N133.CLKF  =  clk	;GCK
    N133.PRLD  =  Gnd

 N129 := N131
    N129.CLKF  =  clk	;GCK
    N129.PRLD  =  Gnd


; Input Register
 N131 := b_quad
    N131.CLKF  =  clk	;GCK
    N131.PRLD  =  Gnd

 N130 := N132
    N130.CLKF  =  clk	;GCK
    N130.PRLD  =  Gnd


; Input Register
 N132 := a_quad
    N132.CLKF  =  clk	;GCK
    N132.PRLD  =  Gnd

 N135 := N167
    N135.CLKF  =  /clk	;GCK
    N135.PRLD  =  Gnd

/N167 := read_n
    N167.CLKF  =  clk	;GCK
    N167.PRLD  =  Gnd

 "cpu_data<1>" := N122
    "cpu_data<1>".TRST  =  N135
    "cpu_data<1>".CLKF  =  N135
    "cpu_data<1>".PRLD  =  Gnd

 N122.T := N121 * N166 * N133
	+ /N121 * N166 * /N133
    N122.CLKF  =  clk	;GCK
   /N122.RSTF  =  clear_n
    N122.PRLD  =  Gnd

 "cpu_data<2>" := N123
    "cpu_data<2>".TRST  =  N135
    "cpu_data<2>".CLKF  =  N135
    "cpu_data<2>".PRLD  =  Gnd

 N123.T := N121 * N166 * N133 * N122
	+ /N121 * N166 * /N133 * /N122
    N123.CLKF  =  clk	;GCK
   /N123.RSTF  =  clear_n
    N123.PRLD  =  Gnd

 "cpu_data<3>" := N124
    "cpu_data<3>".TRST  =  N135
    "cpu_data<3>".CLKF  =  N135
    "cpu_data<3>".PRLD  =  Gnd

 N124.T := N121 * N166 * N133 * N122 * N123
	+ /N121 * N166 * /N133 * /N122 * /N123
    N124.CLKF  =  clk	;GCK
   /N124.RSTF  =  clear_n
    N124.PRLD  =  Gnd

 "cpu_data<4>" := N125
    "cpu_data<4>".TRST  =  N135
    "cpu_data<4>".CLKF  =  N135
    "cpu_data<4>".PRLD  =  Gnd

 N125.T := N121 * N166 * N133 * N122 * N123 * N124
	+ /N121 * N166 * /N133 * /N122 * /N123 * /N124
    N125.CLKF  =  clk	;GCK
   /N125.RSTF  =  clear_n
    N125.PRLD  =  Gnd

 "cpu_data<5>" := N126
    "cpu_data<5>".TRST  =  N135
    "cpu_data<5>".CLKF  =  N135
    "cpu_data<5>".PRLD  =  Gnd

 N126.T := N121 * N166 * N133 * N122 * N123 * N124 * 
	N125
	+ /N121 * N166 * /N133 * /N122 * /N123 * /N124 * 
	/N125
    N126.CLKF  =  clk	;GCK
   /N126.RSTF  =  clear_n
    N126.PRLD  =  Gnd

 "cpu_data<6>" := N127
    "cpu_data<6>".TRST  =  N135
    "cpu_data<6>".CLKF  =  N135
    "cpu_data<6>".PRLD  =  Gnd

 N127.T := N121 * N166 * N133 * N122 * N123 * N124 * 
	N125 * N126
	+ /N121 * N166 * /N133 * /N122 * /N123 * /N124 * 
	/N125 * /N126
    N127.CLKF  =  clk	;GCK
   /N127.RSTF  =  clear_n
    N127.PRLD  =  Gnd

 "cpu_data<7>" := N128
    "cpu_data<7>".TRST  =  N135
    "cpu_data<7>".CLKF  =  N135
    "cpu_data<7>".PRLD  =  Gnd

 N128.T := N121 * N166 * N133 * N122 * N123 * N124 * 
	N125 * N126 * N127
	+ /N121 * N166 * /N133 * /N122 * /N123 * /N124 * 
	/N125 * /N126 * /N127
    N128.CLKF  =  clk	;GCK
   /N128.RSTF  =  clear_n
    N128.PRLD  =  Gnd

 d_out = d_in * /c_in

****************************  Device Pin Out ****************************

Device : XCR3064XL-6-VQ44


              c     c  c     c  c              
              p     p  p     p  p              
              u     u  u     u  u              
              _     _  _     _  _              
              d     d  d     d  d              
              a     a  a     a  a              
              t     t  t     t  t              
              a     a  a     a  a     a     c  
              <  T  <  <  V  <  <  T  _  G  _  
              0  D  1  2  C  3  4  C  i  N  i  
              >  O  >  >  C  >  >  K  n  D  n  
              --------------------------------  
             /33 32 31 30 29 28 27 26 25 24 23 \
     a_quad | 34                            22 | b_in
     b_quad | 35                            21 | clear_n
        GND | 36                            20 | d_in
        WPU | 37                            19 | read_n
        WPU | 38       XCR3064XL-6-VQ44     18 | WPU
        WPU | 39                            17 | VCC
        clk | 40                            16 | GND
        VCC | 41                            15 | WPU
cpu_data<5> | 42                            14 | WPU
cpu_data<6> | 43                            13 | WPU
cpu_data<7> | 44                            12 | WPU
            \ 1  2  3  4  5  6  7  8  9  10 11 /
              --------------------------------  
              T  a  b  P  c  d  T  W  V  W  W  
              D  _  _  E  _  _  M  P  C  P  P  
              I  o  o     o  o  S  U  C  U  U  
                 u  u     u  u                 
                 t  t     t  t                 


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused Weak Pull Up
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XCR3064XL-6-VQ44
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Reserve JTAG Port Pins for ISP              : ON
Use Fast Input Registers                    : ON
Use Foldback NANDs                          : OFF
Default Register Initial State              : RESET
Output Slew Rate                            : FAST
Optimizing Method                           : DENSITY
Collapsing Pterm Limit                      : 28
Collapsing Input Limit                      : 32
Multi Level Logic Optimization              : ON
Enable WYSIWYG mode                         : OFF
Enable Exhaustive Fitting                   : OFF
