-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\obuf4.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY OBUF4_MXILINX IS
   PORT ( I0	:	IN	STD_LOGIC; 
          I1	:	IN	STD_LOGIC; 
          I2	:	IN	STD_LOGIC; 
          I3	:	IN	STD_LOGIC; 
          O0	:	OUT	STD_LOGIC; 
          O1	:	OUT	STD_LOGIC; 
          O2	:	OUT	STD_LOGIC; 
          O3	:	OUT	STD_LOGIC);

end OBUF4_MXILINX;

ARCHITECTURE SCHEMATIC OF OBUF4_MXILINX IS

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF I_36_33 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_32 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_31 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_30 : LABEL IS "true";

BEGIN

   I_36_33 : OBUF
      PORT MAP (I=>I3, O=>O3);

   I_36_32 : OBUF
      PORT MAP (I=>I2, O=>O2);

   I_36_31 : OBUF
      PORT MAP (I=>I1, O=>O1);

   I_36_30 : OBUF
      PORT MAP (I=>I0, O=>O0);

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\ibuf4.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY IBUF4_MXILINX IS
   PORT ( I0	:	IN	STD_LOGIC; 
          I1	:	IN	STD_LOGIC; 
          I2	:	IN	STD_LOGIC; 
          I3	:	IN	STD_LOGIC; 
          O0	:	OUT	STD_LOGIC; 
          O1	:	OUT	STD_LOGIC; 
          O2	:	OUT	STD_LOGIC; 
          O3	:	OUT	STD_LOGIC);

end IBUF4_MXILINX;

ARCHITECTURE SCHEMATIC OF IBUF4_MXILINX IS

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF I_36_37 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_38 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_39 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_40 : LABEL IS "true";

BEGIN

   I_36_37 : IBUF
      PORT MAP (I=>I3, O=>O3);

   I_36_38 : IBUF
      PORT MAP (I=>I2, O=>O2);

   I_36_39 : IBUF
      PORT MAP (I=>I1, O=>O1);

   I_36_40 : IBUF
      PORT MAP (I=>I0, O=>O0);

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\fd.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY FD_MXILINX IS
   PORT ( C	:	IN	STD_LOGIC; 
          D	:	IN	STD_LOGIC; 
          Q	:	OUT	STD_LOGIC);

end FD_MXILINX;

ARCHITECTURE SCHEMATIC OF FD_MXILINX IS
   SIGNAL XLXN_4	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF U0 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_43 : LABEL IS "true";

BEGIN

   U0 : FDCP
      PORT MAP (C=>C, CLR=>XLXN_4, D=>D, PRE=>XLXN_4, Q=>Q);

   I_36_43 : GND
      PORT MAP (G=>XLXN_4);

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\obufe.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY OBUFE_MXILINX IS
   PORT ( E	:	IN	STD_LOGIC; 
          I	:	IN	STD_LOGIC; 
          O	:	OUT	STD_LOGIC);

end OBUFE_MXILINX;

ARCHITECTURE SCHEMATIC OF OBUFE_MXILINX IS
   SIGNAL T	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF I_36_12 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_10 : LABEL IS "true";

BEGIN

   I_36_12 : INV
      PORT MAP (I=>E, O=>T);

   I_36_10 : OBUFT
      PORT MAP (I=>I, T=>T, O=>O);

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\obufe8.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY OBUFE8_MXILINX IS
   PORT ( E	:	IN	STD_LOGIC; 
          I	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          O	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0));

end OBUFE8_MXILINX;

ARCHITECTURE SCHEMATIC OF OBUFE8_MXILINX IS

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE KEEP_HIERARCHY : STRING ;
   ATTRIBUTE KEEP_HIERARCHY OF I_36_35 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I_36_36 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I_36_37 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I_36_33 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I_36_32 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I_36_31 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I_36_30 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I_36_34 : LABEL IS "TRUE";

   COMPONENT OBUFE_MXILINX
      PORT ( E	:	IN	STD_LOGIC; 
             I	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

BEGIN

   I_36_35 : OBUFE_MXILINX
      PORT MAP (E=>E, I=>I(6), O=>O(6));

   I_36_36 : OBUFE_MXILINX
      PORT MAP (E=>E, I=>I(5), O=>O(5));

   I_36_37 : OBUFE_MXILINX
      PORT MAP (E=>E, I=>I(4), O=>O(4));

   I_36_33 : OBUFE_MXILINX
      PORT MAP (E=>E, I=>I(3), O=>O(3));

   I_36_32 : OBUFE_MXILINX
      PORT MAP (E=>E, I=>I(2), O=>O(2));

   I_36_31 : OBUFE_MXILINX
      PORT MAP (E=>E, I=>I(1), O=>O(1));

   I_36_30 : OBUFE_MXILINX
      PORT MAP (E=>E, I=>I(0), O=>O(0));

   I_36_34 : OBUFE_MXILINX
      PORT MAP (E=>E, I=>I(7), O=>O(7));

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\fd8.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY FD8_MXILINX IS
   PORT ( C	:	IN	STD_LOGIC; 
          D	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          Q	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0));

end FD8_MXILINX;

ARCHITECTURE SCHEMATIC OF FD8_MXILINX IS

   ATTRIBUTE fpga_dont_touch : STRING ;

   COMPONENT FD_MXILINX
      PORT ( C	:	IN	STD_LOGIC; 
             D	:	IN	STD_LOGIC; 
             Q	:	OUT	STD_LOGIC);
   END COMPONENT;

BEGIN

   Q7 : FD_MXILINX
      PORT MAP (C=>C, D=>D(7), Q=>Q(7));

   Q6 : FD_MXILINX
      PORT MAP (C=>C, D=>D(6), Q=>Q(6));

   Q4 : FD_MXILINX
      PORT MAP (C=>C, D=>D(4), Q=>Q(4));

   Q5 : FD_MXILINX
      PORT MAP (C=>C, D=>D(5), Q=>Q(5));

   Q0 : FD_MXILINX
      PORT MAP (C=>C, D=>D(0), Q=>Q(0));

   Q1 : FD_MXILINX
      PORT MAP (C=>C, D=>D(1), Q=>Q(1));

   Q2 : FD_MXILINX
      PORT MAP (C=>C, D=>D(2), Q=>Q(2));

   Q3 : FD_MXILINX
      PORT MAP (C=>C, D=>D(3), Q=>Q(3));

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\m2_1.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY M2_1_MXILINX IS
   PORT ( D0	:	IN	STD_LOGIC; 
          D1	:	IN	STD_LOGIC; 
          S0	:	IN	STD_LOGIC; 
          O	:	OUT	STD_LOGIC);

end M2_1_MXILINX;

ARCHITECTURE SCHEMATIC OF M2_1_MXILINX IS
   SIGNAL M0	:	STD_LOGIC;
   SIGNAL M1	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF I_36_9 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_7 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_8 : LABEL IS "true";

BEGIN

   I_36_9 : AND2
      PORT MAP (I0=>D1, I1=>S0, O=>M1);

   I_36_7 : AND2B1
      PORT MAP (I0=>S0, I1=>D0, O=>M0);

   I_36_8 : OR2
      PORT MAP (I0=>M1, I1=>M0, O=>O);

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\m2_1b1.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY M2_1B1_MXILINX IS
   PORT ( D0	:	IN	STD_LOGIC; 
          D1	:	IN	STD_LOGIC; 
          S0	:	IN	STD_LOGIC; 
          O	:	OUT	STD_LOGIC);

end M2_1B1_MXILINX;

ARCHITECTURE SCHEMATIC OF M2_1B1_MXILINX IS
   SIGNAL M0	:	STD_LOGIC;
   SIGNAL M1	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF I_36_9 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_7 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_8 : LABEL IS "true";

BEGIN

   I_36_9 : AND2
      PORT MAP (I0=>D1, I1=>S0, O=>M1);

   I_36_7 : AND2B2
      PORT MAP (I0=>S0, I1=>D0, O=>M0);

   I_36_8 : OR2
      PORT MAP (I0=>M1, I1=>M0, O=>O);

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\ftcle.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY FTCLE_MXILINX IS
   PORT ( C	:	IN	STD_LOGIC; 
          CE	:	IN	STD_LOGIC; 
          CLR	:	IN	STD_LOGIC; 
          D	:	IN	STD_LOGIC; 
          L	:	IN	STD_LOGIC; 
          T	:	IN	STD_LOGIC; 
          Q	:	OUT	STD_LOGIC);

end FTCLE_MXILINX;

ARCHITECTURE SCHEMATIC OF FTCLE_MXILINX IS
   SIGNAL L_CE	:	STD_LOGIC;
   SIGNAL MD	:	STD_LOGIC;
   SIGNAL Q_DUMMY	:	STD_LOGIC;
   SIGNAL TQ	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF I_36_35 : LABEL IS "true";
   ATTRIBUTE KEEP_HIERARCHY : STRING ;
   ATTRIBUTE KEEP_HIERARCHY OF I_36_30 : LABEL IS "TRUE";
   ATTRIBUTE fpga_dont_touch OF I_36_71 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_32 : LABEL IS "true";

   COMPONENT M2_1_MXILINX
      PORT ( D0	:	IN	STD_LOGIC; 
             D1	:	IN	STD_LOGIC; 
             S0	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

BEGIN
   Q <= Q_DUMMY;

   I_36_35 : FDCE
      PORT MAP (C=>C, CE=>L_CE, CLR=>CLR, D=>MD, Q=>Q_DUMMY);

   I_36_30 : M2_1_MXILINX
      PORT MAP (D0=>TQ, D1=>D, S0=>L, O=>MD);

   I_36_71 : OR2
      PORT MAP (I0=>CE, I1=>L, O=>L_CE);

   I_36_32 : XOR2
      PORT MAP (I0=>T, I1=>Q_DUMMY, O=>TQ);

END SCHEMATIC;



-- Vhdl model created from schematic C:\xilinx_webpack\cpld\data\drawing\cb8cled.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY CB8CLED_MXILINX IS
   PORT ( C	:	IN	STD_LOGIC; 
          CE	:	IN	STD_LOGIC; 
          CLR	:	IN	STD_LOGIC; 
          D	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          L	:	IN	STD_LOGIC; 
          UP	:	IN	STD_LOGIC; 
          CEO	:	OUT	STD_LOGIC; 
          Q	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          TC	:	OUT	STD_LOGIC);

end CB8CLED_MXILINX;

ARCHITECTURE SCHEMATIC OF CB8CLED_MXILINX IS
   SIGNAL OR_CE_L	:	STD_LOGIC;
   SIGNAL Q_DUMMY	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   SIGNAL T1	:	STD_LOGIC;
   SIGNAL T2	:	STD_LOGIC;
   SIGNAL T2_DN	:	STD_LOGIC;
   SIGNAL T2_UP	:	STD_LOGIC;
   SIGNAL T3	:	STD_LOGIC;
   SIGNAL T3_DN	:	STD_LOGIC;
   SIGNAL T3_UP	:	STD_LOGIC;
   SIGNAL T4	:	STD_LOGIC;
   SIGNAL T4_DN	:	STD_LOGIC;
   SIGNAL T4_UP	:	STD_LOGIC;
   SIGNAL T5	:	STD_LOGIC;
   SIGNAL T5_DN	:	STD_LOGIC;
   SIGNAL T5_UP	:	STD_LOGIC;
   SIGNAL T6	:	STD_LOGIC;
   SIGNAL T6_DN	:	STD_LOGIC;
   SIGNAL T6_UP	:	STD_LOGIC;
   SIGNAL T7	:	STD_LOGIC;
   SIGNAL T7_DN	:	STD_LOGIC;
   SIGNAL T7_UP	:	STD_LOGIC;
   SIGNAL TC_DN	:	STD_LOGIC;
   SIGNAL TC_DUMMY	:	STD_LOGIC;
   SIGNAL TC_UP	:	STD_LOGIC;
   SIGNAL XLXN_1	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF I_36_63 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_52 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_50 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_40 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_36 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_51 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_41 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_42 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_46 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_48 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_33 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_34 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_47 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_31 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_55 : LABEL IS "true";
   ATTRIBUTE KEEP_HIERARCHY : STRING ;
   ATTRIBUTE KEEP_HIERARCHY OF I3 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I10 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I4 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I9 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I8 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I7 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I6 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF I5 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF U2 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF U3 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF U6 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF U7 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF U_TC : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF U5 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF U4 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF U1 : LABEL IS "TRUE";
   ATTRIBUTE fpga_dont_touch OF I_36_74 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF I_36_38 : LABEL IS "true";

   COMPONENT FTCLE_MXILINX
      PORT ( C	:	IN	STD_LOGIC; 
             CE	:	IN	STD_LOGIC; 
             CLR	:	IN	STD_LOGIC; 
             D	:	IN	STD_LOGIC; 
             L	:	IN	STD_LOGIC; 
             T	:	IN	STD_LOGIC; 
             Q	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT M2_1_MXILINX
      PORT ( D0	:	IN	STD_LOGIC; 
             D1	:	IN	STD_LOGIC; 
             S0	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT M2_1B1_MXILINX
      PORT ( D0	:	IN	STD_LOGIC; 
             D1	:	IN	STD_LOGIC; 
             S0	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

BEGIN
   Q <= Q_DUMMY;
   TC <= TC_DUMMY;

   I_36_63 : AND2
      PORT MAP (I0=>CE, I1=>TC_DUMMY, O=>CEO);

   I_36_52 : AND2
      PORT MAP (I0=>Q_DUMMY(4), I1=>T4, O=>T5_UP);

   I_36_50 : AND2
      PORT MAP (I0=>Q_DUMMY(1), I1=>Q_DUMMY(0), O=>T2_UP);

   I_36_40 : AND2B1
      PORT MAP (I0=>Q_DUMMY(4), I1=>T4, O=>T5_DN);

   I_36_36 : AND2B2
      PORT MAP (I0=>Q_DUMMY(1), I1=>Q_DUMMY(0), O=>T2_DN);

   I_36_51 : AND3
      PORT MAP (I0=>Q_DUMMY(2), I1=>Q_DUMMY(1), I2=>Q_DUMMY(0), O=>T3_UP);

   I_36_41 : AND3
      PORT MAP (I0=>Q_DUMMY(5), I1=>Q_DUMMY(4), I2=>T4, O=>T6_UP);

   I_36_42 : AND3B2
      PORT MAP (I0=>Q_DUMMY(5), I1=>Q_DUMMY(4), I2=>T4, O=>T6_DN);

   I_36_46 : AND3B3
      PORT MAP (I0=>Q_DUMMY(2), I1=>Q_DUMMY(1), I2=>Q_DUMMY(0), O=>T3_DN);

   I_36_48 : AND4
      PORT MAP (I0=>Q_DUMMY(3), I1=>Q_DUMMY(2), I2=>Q_DUMMY(1), I3=>Q_DUMMY(0),
      O=>T4_UP);

   I_36_33 : AND4
      PORT MAP (I0=>Q_DUMMY(6), I1=>Q_DUMMY(5), I2=>Q_DUMMY(4), I3=>T4,
      O=>T7_UP);

   I_36_34 : AND4B3
      PORT MAP (I0=>Q_DUMMY(6), I1=>Q_DUMMY(5), I2=>Q_DUMMY(4), I3=>T4,
      O=>T7_DN);

   I_36_47 : AND4B4
      PORT MAP (I0=>Q_DUMMY(3), I1=>Q_DUMMY(2), I2=>Q_DUMMY(1), I3=>Q_DUMMY(0),
      O=>T4_DN);

   I_36_31 : AND5
      PORT MAP (I0=>Q_DUMMY(7), I1=>Q_DUMMY(6), I2=>Q_DUMMY(5), I3=>Q_DUMMY(4),
      I4=>T4, O=>TC_UP);

   I_36_55 : AND5B4
      PORT MAP (I0=>Q_DUMMY(7), I1=>Q_DUMMY(6), I2=>Q_DUMMY(5), I3=>Q_DUMMY(4),
      I4=>T4, O=>TC_DN);

   I3 : FTCLE_MXILINX
      PORT MAP (C=>C, CE=>OR_CE_L, CLR=>CLR, D=>D(7), L=>L, T=>T7,
      Q=>Q_DUMMY(7));

   I10 : FTCLE_MXILINX
      PORT MAP (C=>C, CE=>OR_CE_L, CLR=>CLR, D=>D(0), L=>L, T=>XLXN_1,
      Q=>Q_DUMMY(0));

   I4 : FTCLE_MXILINX
      PORT MAP (C=>C, CE=>OR_CE_L, CLR=>CLR, D=>D(6), L=>L, T=>T6,
      Q=>Q_DUMMY(6));

   I9 : FTCLE_MXILINX
      PORT MAP (C=>C, CE=>OR_CE_L, CLR=>CLR, D=>D(1), L=>L, T=>T1,
      Q=>Q_DUMMY(1));

   I8 : FTCLE_MXILINX
      PORT MAP (C=>C, CE=>OR_CE_L, CLR=>CLR, D=>D(2), L=>L, T=>T2,
      Q=>Q_DUMMY(2));

   I7 : FTCLE_MXILINX
      PORT MAP (C=>C, CE=>OR_CE_L, CLR=>CLR, D=>D(3), L=>L, T=>T3,
      Q=>Q_DUMMY(3));

   I6 : FTCLE_MXILINX
      PORT MAP (C=>C, CE=>OR_CE_L, CLR=>CLR, D=>D(4), L=>L, T=>T4,
      Q=>Q_DUMMY(4));

   I5 : FTCLE_MXILINX
      PORT MAP (C=>C, CE=>OR_CE_L, CLR=>CLR, D=>D(5), L=>L, T=>T5,
      Q=>Q_DUMMY(5));

   U2 : M2_1_MXILINX
      PORT MAP (D0=>T2_DN, D1=>T2_UP, S0=>UP, O=>T2);

   U3 : M2_1_MXILINX
      PORT MAP (D0=>T3_DN, D1=>T3_UP, S0=>UP, O=>T3);

   U6 : M2_1_MXILINX
      PORT MAP (D0=>T6_DN, D1=>T6_UP, S0=>UP, O=>T6);

   U7 : M2_1_MXILINX
      PORT MAP (D0=>T7_DN, D1=>T7_UP, S0=>UP, O=>T7);

   U_TC : M2_1_MXILINX
      PORT MAP (D0=>TC_DN, D1=>TC_UP, S0=>UP, O=>TC_DUMMY);

   U5 : M2_1_MXILINX
      PORT MAP (D0=>T5_DN, D1=>T5_UP, S0=>UP, O=>T5);

   U4 : M2_1_MXILINX
      PORT MAP (D0=>T4_DN, D1=>T4_UP, S0=>UP, O=>T4);

   U1 : M2_1B1_MXILINX
      PORT MAP (D0=>Q_DUMMY(0), D1=>Q_DUMMY(0), S0=>UP, O=>T1);

   I_36_74 : OR2
      PORT MAP (I0=>CE, I1=>L, O=>OR_CE_L);

   I_36_38 : VCC
      PORT MAP (P=>XLXN_1);

END SCHEMATIC;



-- Vhdl model created from schematic shutter_top.sch - Mon May 27 11:20:56 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY shutter_top IS
   PORT ( A_IN	:	IN	STD_LOGIC; 
          A_QUAD	:	IN	STD_LOGIC; 
          B_IN	:	IN	STD_LOGIC; 
          B_QUAD	:	IN	STD_LOGIC; 
          CLEAR_N	:	IN	STD_LOGIC; 
          CLK	:	IN	STD_LOGIC; 
          C_IN	:	IN	STD_LOGIC; 
          D_IN	:	IN	STD_LOGIC; 
          READ_N	:	IN	STD_LOGIC; 
          A_OUT	:	OUT	STD_LOGIC; 
          B_OUT	:	OUT	STD_LOGIC; 
          CPU_DATA	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          C_OUT	:	OUT	STD_LOGIC; 
          D_OUT	:	OUT	STD_LOGIC);

end shutter_top;

ARCHITECTURE SCHEMATIC OF shutter_top IS
   SIGNAL D	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   SIGNAL XLXN_13	:	STD_LOGIC;
   SIGNAL XLXN_14	:	STD_LOGIC;
   SIGNAL XLXN_19	:	STD_LOGIC;
   SIGNAL XLXN_20	:	STD_LOGIC;
   SIGNAL XLXN_21	:	STD_LOGIC;
   SIGNAL XLXN_23	:	STD_LOGIC;
   SIGNAL XLXN_25	:	STD_LOGIC;
   SIGNAL XLXN_27	:	STD_LOGIC;
   SIGNAL XLXN_31	:	STD_LOGIC;
   SIGNAL XLXN_33	:	STD_LOGIC;
   SIGNAL XLXN_34	:	STD_LOGIC;
   SIGNAL XLXN_36	:	STD_LOGIC;
   SIGNAL XLXN_37	:	STD_LOGIC;
   SIGNAL XLXN_41	:	STD_LOGIC;
   SIGNAL XLXN_42	:	STD_LOGIC;
   SIGNAL XLXN_43	:	STD_LOGIC;
   SIGNAL XLXN_44	:	STD_LOGIC;
   SIGNAL XLXN_45	:	STD_LOGIC;
   SIGNAL XLXN_46	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   SIGNAL XLXN_47	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   SIGNAL XLXN_49	:	STD_LOGIC;
   SIGNAL XLXN_53	:	STD_LOGIC;
   SIGNAL XLXN_65	:	STD_LOGIC;
   SIGNAL XLXN_67	:	STD_LOGIC;
   SIGNAL XLXN_69	:	STD_LOGIC;
   SIGNAL XLXN_70	:	STD_LOGIC;
   SIGNAL XLXN_75	:	STD_LOGIC;
   SIGNAL XLXN_76	:	STD_LOGIC;
   SIGNAL XLXN_77	:	STD_LOGIC;
   SIGNAL XLXN_78	:	STD_LOGIC;
   SIGNAL XLXN_79	:	STD_LOGIC;
   SIGNAL XLXN_80	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;
   ATTRIBUTE fpga_dont_touch OF XLXI_40 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_42 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_39 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_43 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_18 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_23 : LABEL IS "true";
   ATTRIBUTE KEEP_HIERARCHY : STRING ;
   ATTRIBUTE KEEP_HIERARCHY OF XLXI_16 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF XLXI_19 : LABEL IS "TRUE";
   ATTRIBUTE fpga_dont_touch OF XLXI_38 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_28 : LABEL IS "true";
   ATTRIBUTE KEEP_HIERARCHY OF XLXI_24 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF XLXI_33 : LABEL IS "TRUE";
   ATTRIBUTE fpga_dont_touch OF XLXI_48 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_49 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_29 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_27 : LABEL IS "true";
   ATTRIBUTE fpga_dont_touch OF XLXI_26 : LABEL IS "true";
   ATTRIBUTE KEEP_HIERARCHY OF XLXI_17 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF XLXI_34 : LABEL IS "TRUE";
   ATTRIBUTE KEEP_HIERARCHY OF XLXI_20 : LABEL IS "TRUE";

   COMPONENT CB8CLED_MXILINX
      PORT ( C	:	IN	STD_LOGIC; 
             CE	:	IN	STD_LOGIC; 
             CLR	:	IN	STD_LOGIC; 
             D	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             L	:	IN	STD_LOGIC; 
             UP	:	IN	STD_LOGIC; 
             CEO	:	OUT	STD_LOGIC; 
             Q	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             TC	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT FD_MXILINX
      PORT ( C	:	IN	STD_LOGIC; 
             D	:	IN	STD_LOGIC; 
             Q	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT FD8_MXILINX
      PORT ( C	:	IN	STD_LOGIC; 
             D	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             Q	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0));
   END COMPONENT;

   COMPONENT IBUF4_MXILINX
      PORT ( I0	:	IN	STD_LOGIC; 
             I1	:	IN	STD_LOGIC; 
             I2	:	IN	STD_LOGIC; 
             I3	:	IN	STD_LOGIC; 
             O0	:	OUT	STD_LOGIC; 
             O1	:	OUT	STD_LOGIC; 
             O2	:	OUT	STD_LOGIC; 
             O3	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT M2_1_MXILINX
      PORT ( D0	:	IN	STD_LOGIC; 
             D1	:	IN	STD_LOGIC; 
             S0	:	IN	STD_LOGIC; 
             O	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT OBUF4_MXILINX
      PORT ( I0	:	IN	STD_LOGIC; 
             I1	:	IN	STD_LOGIC; 
             I2	:	IN	STD_LOGIC; 
             I3	:	IN	STD_LOGIC; 
             O0	:	OUT	STD_LOGIC; 
             O1	:	OUT	STD_LOGIC; 
             O2	:	OUT	STD_LOGIC; 
             O3	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT OBUFE8_MXILINX
      PORT ( E	:	IN	STD_LOGIC; 
             I	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             O	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0));
   END COMPONENT;

   COMPONENT q_decode
      PORT ( S2	:	IN	STD_LOGIC; 
             S1	:	IN	STD_LOGIC; 
             B	:	IN	STD_LOGIC; 
             A	:	IN	STD_LOGIC; 
             S4	:	IN	STD_LOGIC; 
             S3	:	OUT	STD_LOGIC);
   END COMPONENT;

BEGIN

   XLXI_40 : AND2B1
      PORT MAP (I0=>XLXN_70, I1=>XLXN_65, O=>XLXN_78);

   XLXI_42 : AND2B1
      PORT MAP (I0=>XLXN_67, I1=>XLXN_69, O=>XLXN_75);

   XLXI_39 : AND2B1
      PORT MAP (I0=>XLXN_65, I1=>XLXN_70, O=>XLXN_77);

   XLXI_43 : AND2B1
      PORT MAP (I0=>XLXN_69, I1=>XLXN_67, O=>XLXN_76);

   XLXI_18 : AND2B2
      PORT MAP (I0=>XLXN_27, I1=>XLXN_25, O=>XLXN_23);

   XLXI_23 : BUFG
      PORT MAP (I=>CLK, O=>XLXN_53);

   XLXI_16 : CB8CLED_MXILINX
      PORT MAP (C=>XLXN_53, CE=>XLXN_33, CLR=>XLXN_43, D(7)=>D(7), D(6)=>D(6),
      D(5)=>D(5), D(4)=>D(4), D(3)=>D(3), D(2)=>D(2), D(1)=>D(1), D(0)=>D(0),
      L=>XLXN_49, UP=>XLXN_34, CEO=>open, Q(7)=>XLXN_47(7), Q(6)=>XLXN_47(6),
      Q(5)=>XLXN_47(5), Q(4)=>XLXN_47(4), Q(3)=>XLXN_47(3), Q(2)=>XLXN_47(2),
      Q(1)=>XLXN_47(1), Q(0)=>XLXN_47(0), TC=>open);

   XLXI_10 : FD_MXILINX
      PORT MAP (C=>XLXN_53, D=>XLXN_14, Q=>XLXN_20);

   XLXI_9 : FD_MXILINX
      PORT MAP (C=>XLXN_53, D=>XLXN_13, Q=>XLXN_19);

   XLXI_30 : FD_MXILINX
      PORT MAP (C=>XLXN_53, D=>XLXN_44, Q=>XLXN_36);

   XLXI_7 : FD_MXILINX
      PORT MAP (C=>XLXN_37, D=>XLXN_36, Q=>XLXN_45);

   XLXI_6 : FD_MXILINX
      PORT MAP (C=>XLXN_53, D=>XLXN_31, Q=>XLXN_34);

   XLXI_5 : FD_MXILINX
      PORT MAP (C=>XLXN_53, D=>XLXN_21, Q=>XLXN_33);

   XLXI_4 : FD_MXILINX
      PORT MAP (C=>XLXN_53, D=>XLXN_20, Q=>XLXN_25);

   XLXI_3 : FD_MXILINX
      PORT MAP (C=>XLXN_53, D=>XLXN_19, Q=>XLXN_27);

   XLXI_19 : FD8_MXILINX
      PORT MAP (C=>XLXN_45, D(7)=>XLXN_47(7), D(6)=>XLXN_47(6),
      D(5)=>XLXN_47(5), D(4)=>XLXN_47(4), D(3)=>XLXN_47(3), D(2)=>XLXN_47(2),
      D(1)=>XLXN_47(1), D(0)=>XLXN_47(0), Q(7)=>XLXN_46(7), Q(6)=>XLXN_46(6),
      Q(5)=>XLXN_46(5), Q(4)=>XLXN_46(4), Q(3)=>XLXN_46(3), Q(2)=>XLXN_46(2),
      Q(1)=>XLXN_46(1), Q(0)=>XLXN_46(0));

   XLXI_38 : GND
      PORT MAP (G=>D(7));

   XLXI_28 : GND
      PORT MAP (G=>XLXN_49);

   XLXI_24 : IBUF4_MXILINX
      PORT MAP (I0=>A_QUAD, I1=>B_QUAD, I2=>READ_N, I3=>CLEAR_N, O0=>XLXN_13,
      O1=>XLXN_14, O2=>XLXN_41, O3=>XLXN_42);

   XLXI_33 : IBUF4_MXILINX
      PORT MAP (I0=>A_IN, I1=>B_IN, I2=>C_IN, I3=>D_IN, O0=>XLXN_70,
      O1=>XLXN_65, O2=>XLXN_69, O3=>XLXN_67);

   XLXI_48 : INV
      PORT MAP (I=>XLXN_77, O=>XLXN_79);

   XLXI_49 : INV
      PORT MAP (I=>XLXN_78, O=>XLXN_80);

   XLXI_29 : INV
      PORT MAP (I=>XLXN_53, O=>XLXN_37);

   XLXI_27 : INV
      PORT MAP (I=>XLXN_42, O=>XLXN_43);

   XLXI_26 : INV
      PORT MAP (I=>XLXN_41, O=>XLXN_44);

   XLXI_17 : M2_1_MXILINX
      PORT MAP (D0=>XLXN_34, D1=>XLXN_19, S0=>XLXN_23, O=>XLXN_31);

   XLXI_34 : OBUF4_MXILINX
      PORT MAP (I0=>XLXN_79, I1=>XLXN_80, I2=>XLXN_75, I3=>XLXN_76, O0=>A_OUT,
      O1=>B_OUT, O2=>C_OUT, O3=>D_OUT);

   XLXI_20 : OBUFE8_MXILINX
      PORT MAP (E=>XLXN_45, I(7)=>XLXN_46(7), I(6)=>XLXN_46(6),
      I(5)=>XLXN_46(5), I(4)=>XLXN_46(4), I(3)=>XLXN_46(3), I(2)=>XLXN_46(2),
      I(1)=>XLXN_46(1), I(0)=>XLXN_46(0), O(7)=>CPU_DATA(7), O(6)=>CPU_DATA(6),
      O(5)=>CPU_DATA(5), O(4)=>CPU_DATA(4), O(3)=>CPU_DATA(3),
      O(2)=>CPU_DATA(2), O(1)=>CPU_DATA(1), O(0)=>CPU_DATA(0));

   XLXI_1 : q_decode
      PORT MAP (S2=>XLXN_25, S1=>XLXN_27, B=>XLXN_20, A=>XLXN_19, S4=>XLXN_34,
      S3=>XLXN_21);

END SCHEMATIC;