-- Xilinx Vhdl produced by program ngd2vhdl E.32 -- Command: -rpw 100 -tpw 1 -ar Structure -xon true -w shutter_top.nga shutter_top_timesim.vhd -- Input file: shutter_top.nga -- Output file: shutter_top_timesim.vhd -- Design name: shutter_top -- Xilinx: C:/xilinx_webpack -- # of Entities: 1 -- Device: XCR3064XL-6-VQ44 -- The output of ngd2vhdl is a simulation model. This file cannot be synthesized, -- or used in any other manner other than simulation. This netlist uses simulation -- primitives which may not represent the true implementation of the device, however -- the netlist is functionally correct. Do not modify this file. -- Model for ROC (Reset-On-Configuration) Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity ROC is generic (InstancePath: STRING := "*"; WIDTH : Time := 100 ns); port(O : out std_ulogic := '1') ; attribute VITAL_LEVEL0 of ROC : entity is TRUE; end ROC; architecture ROC_V of ROC is attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE; begin ONE_SHOT : process begin if (WIDTH <= 0 ns) then assert FALSE report "*** Error: a positive value of WIDTH must be specified ***" severity failure; else wait for WIDTH; O <= '0'; end if; wait; end process ONE_SHOT; end ROC_V; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity shutter_top is port ( a_in : in STD_LOGIC := 'X'; a_out : out STD_LOGIC; b_in : in STD_LOGIC := 'X'; b_out : out STD_LOGIC; c_in : in STD_LOGIC := 'X'; c_out : out STD_LOGIC; clear_n : in STD_LOGIC := 'X'; clk : in STD_LOGIC := 'X'; read_n : in STD_LOGIC := 'X'; d_in : in STD_LOGIC := 'X'; d_out : out STD_LOGIC; b_quad : in STD_LOGIC := 'X'; a_quad : in STD_LOGIC := 'X'; cpu_data : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); end shutter_top; architecture Structure of shutter_top is component ROC generic (InstancePath: STRING := "*"; WIDTH : Time := 100 ns); port (O : out STD_ULOGIC := '1'); end component; signal a_out_MC_Q : STD_LOGIC; signal a_out_MC_D : STD_LOGIC; signal a_in_II_UIM : STD_LOGIC; signal a_out_MC_D1_PT_0 : STD_LOGIC; signal a_out_MC_D1 : STD_LOGIC; signal a_out_MC_D2 : STD_LOGIC; signal b_out_MC_Q : STD_LOGIC; signal b_out_MC_D : STD_LOGIC; signal b_in_II_UIM : STD_LOGIC; signal b_out_MC_D1_PT_0 : STD_LOGIC; signal b_out_MC_D1 : STD_LOGIC; signal b_out_MC_D2 : STD_LOGIC; signal c_out_MC_Q : STD_LOGIC; signal c_out_MC_D : STD_LOGIC; signal c_in_II_UIM : STD_LOGIC; signal c_out_MC_D1_PT_0 : STD_LOGIC; signal c_out_MC_D1 : STD_LOGIC; signal c_out_MC_D2 : STD_LOGIC; signal cpu_data_0_MC_Q : STD_LOGIC; signal cpu_data_0_MC_OE : STD_LOGIC; signal cpu_data_0_MC_D : STD_LOGIC; signal FOOBAR1_ctinst_7 : STD_LOGIC; signal clear_n_II_UIM : STD_LOGIC; signal FOOBAR1_ctinst_0 : STD_LOGIC; signal N159 : STD_LOGIC; signal FOOBAR1_ctinst_4 : STD_LOGIC; signal N131 : STD_LOGIC; signal N159_MC_Q : STD_LOGIC; signal N159_MC_D : STD_LOGIC; signal clk_II_FCLK : STD_LOGIC; signal N159_MC_D1 : STD_LOGIC; signal N129 : STD_LOGIC; signal N125 : STD_LOGIC; signal N127 : STD_LOGIC; signal N126 : STD_LOGIC; signal N128 : STD_LOGIC; signal N159_MC_D2_PT_0 : STD_LOGIC; signal N159_MC_D2_PT_1 : STD_LOGIC; signal N159_MC_D2 : STD_LOGIC; signal N129_MC_Q : STD_LOGIC; signal N129_MC_D : STD_LOGIC; signal N129_MC_D1 : STD_LOGIC; signal N129_MC_D2_PT_0 : STD_LOGIC; signal N129_MC_D2_PT_1 : STD_LOGIC; signal N129_MC_D2_PT_2 : STD_LOGIC; signal N129_MC_D2 : STD_LOGIC; signal N125_MC_Q : STD_LOGIC; signal N125_MC_D : STD_LOGIC; signal N125_MC_D1_PT_0 : STD_LOGIC; signal N125_MC_D1 : STD_LOGIC; signal N125_MC_D2 : STD_LOGIC; signal N127_MC_Q : STD_LOGIC; signal b_quad_II_IREG : STD_LOGIC; signal N126_MC_Q : STD_LOGIC; signal N126_MC_D : STD_LOGIC; signal N126_MC_D1_PT_0 : STD_LOGIC; signal N126_MC_D1 : STD_LOGIC; signal N126_MC_D2 : STD_LOGIC; signal N128_MC_Q : STD_LOGIC; signal a_quad_II_IREG : STD_LOGIC; signal N131_MC_Q : STD_LOGIC; signal N131_MC_D : STD_LOGIC; signal N158 : STD_LOGIC; signal N131_MC_D1_PT_0 : STD_LOGIC; signal N131_MC_D1 : STD_LOGIC; signal N131_MC_D2 : STD_LOGIC; signal N158_MC_Q : STD_LOGIC; signal N158_MC_D : STD_LOGIC; signal read_n_II_UIM : STD_LOGIC; signal N158_MC_D1_PT_0 : STD_LOGIC; signal N158_MC_D1 : STD_LOGIC; signal N158_MC_D2 : STD_LOGIC; signal N117 : STD_LOGIC; signal cpu_data_0_MC_D1_PT_0 : STD_LOGIC; signal cpu_data_0_MC_D1 : STD_LOGIC; signal cpu_data_0_MC_D2 : STD_LOGIC; signal cpu_data_0_MC_BUFOE_OUT : STD_LOGIC; signal N117_MC_Q : STD_LOGIC; signal N117_MC_R_OR_PRLD : STD_LOGIC; signal N117_MC_D : STD_LOGIC; signal N117_MC_D1 : STD_LOGIC; signal N117_MC_D2_PT_0 : STD_LOGIC; signal N117_MC_D2 : STD_LOGIC; signal cpu_data_1_MC_Q : STD_LOGIC; signal cpu_data_1_MC_OE : STD_LOGIC; signal cpu_data_1_MC_D : STD_LOGIC; signal N118 : STD_LOGIC; signal cpu_data_1_MC_D1_PT_0 : STD_LOGIC; signal cpu_data_1_MC_D1 : STD_LOGIC; signal cpu_data_1_MC_D2 : STD_LOGIC; signal cpu_data_1_MC_BUFOE_OUT : STD_LOGIC; signal N118_MC_Q : STD_LOGIC; signal N118_MC_R_OR_PRLD : STD_LOGIC; signal N118_MC_D : STD_LOGIC; signal N118_MC_D1 : STD_LOGIC; signal N118_MC_D2_PT_0 : STD_LOGIC; signal N118_MC_D2_PT_1 : STD_LOGIC; signal N118_MC_D2 : STD_LOGIC; signal N118_MC_D_TFF : STD_LOGIC; signal cpu_data_2_MC_Q : STD_LOGIC; signal cpu_data_2_MC_OE : STD_LOGIC; signal cpu_data_2_MC_D : STD_LOGIC; signal N119 : STD_LOGIC; signal cpu_data_2_MC_D1_PT_0 : STD_LOGIC; signal cpu_data_2_MC_D1 : STD_LOGIC; signal cpu_data_2_MC_D2 : STD_LOGIC; signal cpu_data_2_MC_BUFOE_OUT : STD_LOGIC; signal N119_MC_Q : STD_LOGIC; signal N119_MC_R_OR_PRLD : STD_LOGIC; signal N119_MC_D : STD_LOGIC; signal N119_MC_D1 : STD_LOGIC; signal N119_MC_D2_PT_0 : STD_LOGIC; signal N119_MC_D2_PT_1 : STD_LOGIC; signal N119_MC_D2 : STD_LOGIC; signal N119_MC_D_TFF : STD_LOGIC; signal cpu_data_3_MC_Q : STD_LOGIC; signal cpu_data_3_MC_OE : STD_LOGIC; signal cpu_data_3_MC_D : STD_LOGIC; signal N120 : STD_LOGIC; signal cpu_data_3_MC_D1_PT_0 : STD_LOGIC; signal cpu_data_3_MC_D1 : STD_LOGIC; signal cpu_data_3_MC_D2 : STD_LOGIC; signal cpu_data_3_MC_BUFOE_OUT : STD_LOGIC; signal N120_MC_Q : STD_LOGIC; signal N120_MC_R_OR_PRLD : STD_LOGIC; signal N120_MC_D : STD_LOGIC; signal N120_MC_D1 : STD_LOGIC; signal N120_MC_D2_PT_0 : STD_LOGIC; signal N120_MC_D2_PT_1 : STD_LOGIC; signal N120_MC_D2 : STD_LOGIC; signal N120_MC_D_TFF : STD_LOGIC; signal cpu_data_4_MC_Q : STD_LOGIC; signal cpu_data_4_MC_OE : STD_LOGIC; signal cpu_data_4_MC_D : STD_LOGIC; signal N121 : STD_LOGIC; signal cpu_data_4_MC_D1_PT_0 : STD_LOGIC; signal cpu_data_4_MC_D1 : STD_LOGIC; signal cpu_data_4_MC_D2 : STD_LOGIC; signal cpu_data_4_MC_BUFOE_OUT : STD_LOGIC; signal N121_MC_Q : STD_LOGIC; signal N121_MC_R_OR_PRLD : STD_LOGIC; signal N121_MC_D : STD_LOGIC; signal N121_MC_D1 : STD_LOGIC; signal N121_MC_D2_PT_0 : STD_LOGIC; signal N121_MC_D2_PT_1 : STD_LOGIC; signal N121_MC_D2 : STD_LOGIC; signal N121_MC_D_TFF : STD_LOGIC; signal cpu_data_5_MC_Q : STD_LOGIC; signal cpu_data_5_MC_OE : STD_LOGIC; signal cpu_data_5_MC_D : STD_LOGIC; signal N122 : STD_LOGIC; signal cpu_data_5_MC_D1_PT_0 : STD_LOGIC; signal cpu_data_5_MC_D1 : STD_LOGIC; signal cpu_data_5_MC_D2 : STD_LOGIC; signal cpu_data_5_MC_BUFOE_OUT : STD_LOGIC; signal N122_MC_Q : STD_LOGIC; signal N122_MC_R_OR_PRLD : STD_LOGIC; signal N122_MC_D : STD_LOGIC; signal N122_MC_D1 : STD_LOGIC; signal N122_MC_D2_PT_0 : STD_LOGIC; signal N122_MC_D2_PT_1 : STD_LOGIC; signal N122_MC_D2 : STD_LOGIC; signal N122_MC_D_TFF : STD_LOGIC; signal cpu_data_6_MC_Q : STD_LOGIC; signal cpu_data_6_MC_OE : STD_LOGIC; signal cpu_data_6_MC_D : STD_LOGIC; signal N123 : STD_LOGIC; signal cpu_data_6_MC_D1_PT_0 : STD_LOGIC; signal cpu_data_6_MC_D1 : STD_LOGIC; signal cpu_data_6_MC_D2 : STD_LOGIC; signal cpu_data_6_MC_BUFOE_OUT : STD_LOGIC; signal N123_MC_Q : STD_LOGIC; signal N123_MC_R_OR_PRLD : STD_LOGIC; signal N123_MC_D : STD_LOGIC; signal N123_MC_D1 : STD_LOGIC; signal N123_MC_D2_PT_0 : STD_LOGIC; signal N123_MC_D2_PT_1 : STD_LOGIC; signal N123_MC_D2 : STD_LOGIC; signal N123_MC_D_TFF : STD_LOGIC; signal cpu_data_7_MC_Q : STD_LOGIC; signal cpu_data_7_MC_OE : STD_LOGIC; signal cpu_data_7_MC_D : STD_LOGIC; signal N124 : STD_LOGIC; signal cpu_data_7_MC_D1_PT_0 : STD_LOGIC; signal cpu_data_7_MC_D1 : STD_LOGIC; signal cpu_data_7_MC_D2 : STD_LOGIC; signal cpu_data_7_MC_BUFOE_OUT : STD_LOGIC; signal N124_MC_Q : STD_LOGIC; signal N124_MC_R_OR_PRLD : STD_LOGIC; signal N124_MC_D : STD_LOGIC; signal N124_MC_D1 : STD_LOGIC; signal N124_MC_D2_PT_0 : STD_LOGIC; signal N124_MC_D2_PT_1 : STD_LOGIC; signal N124_MC_D2 : STD_LOGIC; signal N124_MC_D_TFF : STD_LOGIC; signal d_out_MC_Q : STD_LOGIC; signal d_out_MC_D : STD_LOGIC; signal d_in_II_UIM : STD_LOGIC; signal d_out_MC_D1_PT_0 : STD_LOGIC; signal d_out_MC_D1 : STD_LOGIC; signal d_out_MC_D2 : STD_LOGIC; signal GND : STD_LOGIC; signal VCC : STD_LOGIC; signal PRLD : STD_LOGIC; signal NlwInverterSignal_b_out_MC_D1_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_FOOBAR1_ctinst_0_OUT : STD_LOGIC; signal NlwInverterSignal_N159_MC_D2_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_N159_MC_D2_PT_0_IN3 : STD_LOGIC; signal NlwInverterSignal_N159_MC_D2_PT_0_IN4 : STD_LOGIC; signal NlwInverterSignal_N159_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N159_MC_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_N159_MC_D2_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_N159_MC_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_N129_MC_D2_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_N129_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N129_MC_D2_PT_2_IN0 : STD_LOGIC; signal NlwInverterSignal_N129_MC_D2_PT_2_IN1 : STD_LOGIC; signal NlwInverterSignal_N129_MC_D2_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_N129_MC_XOR_IN0 : STD_LOGIC; signal NlwInverterSignal_N158_MC_XOR_IN0 : STD_LOGIC; signal NlwInverterSignal_N117_MC_XOR_IN0 : STD_LOGIC; signal NlwInverterSignal_N118_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N118_MC_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_N119_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N119_MC_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_N119_MC_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_N120_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N120_MC_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_N120_MC_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_N120_MC_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_N121_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N121_MC_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_N121_MC_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_N121_MC_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_N121_MC_D2_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_N122_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N122_MC_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_N122_MC_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_N122_MC_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_N122_MC_D2_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_N122_MC_D2_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_N123_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N123_MC_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_N123_MC_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_N123_MC_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_N123_MC_D2_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_N123_MC_D2_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_N123_MC_D2_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_N124_MC_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_N124_MC_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_N124_MC_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_N124_MC_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_N124_MC_D2_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_N124_MC_D2_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_N124_MC_D2_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_N124_MC_D2_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_d_out_MC_D1_PT_0_IN0 : STD_LOGIC; begin a_out_0 : X_BUF port map ( I => a_out_MC_Q, O => a_out ); a_out_MC_REG : X_BUF port map ( I => a_out_MC_D, O => a_out_MC_Q ); a_out_MC_D1_PT_0_1 : X_AND2 port map ( I0 => a_in_II_UIM, I1 => a_in_II_UIM, O => a_out_MC_D1_PT_0 ); a_out_MC_D1_2 : X_OR2 port map ( I0 => a_out_MC_D1_PT_0, I1 => a_out_MC_D1_PT_0, O => a_out_MC_D1 ); GND_ZERO : X_ZERO port map ( O => GND ); a_out_MC_D2_3 : X_OR2 port map ( I0 => GND, I1 => GND, O => a_out_MC_D2 ); a_out_MC_XOR : X_XOR2 port map ( I0 => a_out_MC_D1, I1 => a_out_MC_D2, O => a_out_MC_D ); a_in_II_UIM_4 : X_BUF port map ( I => a_in, O => a_in_II_UIM ); b_out_5 : X_BUF port map ( I => b_out_MC_Q, O => b_out ); b_out_MC_REG : X_BUF port map ( I => b_out_MC_D, O => b_out_MC_Q ); b_out_MC_D1_PT_0_6 : X_AND2 port map ( I0 => NlwInverterSignal_b_out_MC_D1_PT_0_IN0, I1 => b_in_II_UIM, O => b_out_MC_D1_PT_0 ); b_out_MC_D1_7 : X_OR2 port map ( I0 => b_out_MC_D1_PT_0, I1 => b_out_MC_D1_PT_0, O => b_out_MC_D1 ); b_out_MC_D2_8 : X_OR2 port map ( I0 => GND, I1 => GND, O => b_out_MC_D2 ); b_out_MC_XOR : X_XOR2 port map ( I0 => b_out_MC_D1, I1 => b_out_MC_D2, O => b_out_MC_D ); b_in_II_UIM_9 : X_BUF port map ( I => b_in, O => b_in_II_UIM ); c_out_10 : X_BUF port map ( I => c_out_MC_Q, O => c_out ); c_out_MC_REG : X_BUF port map ( I => c_out_MC_D, O => c_out_MC_Q ); c_out_MC_D1_PT_0_11 : X_AND2 port map ( I0 => c_in_II_UIM, I1 => c_in_II_UIM, O => c_out_MC_D1_PT_0 ); c_out_MC_D1_12 : X_OR2 port map ( I0 => c_out_MC_D1_PT_0, I1 => c_out_MC_D1_PT_0, O => c_out_MC_D1 ); c_out_MC_D2_13 : X_OR2 port map ( I0 => GND, I1 => GND, O => c_out_MC_D2 ); c_out_MC_XOR : X_XOR2 port map ( I0 => c_out_MC_D1, I1 => c_out_MC_D2, O => c_out_MC_D ); c_in_II_UIM_14 : X_BUF port map ( I => c_in, O => c_in_II_UIM ); cpu_data_0_Q : X_TRI port map ( I => cpu_data_0_MC_Q, CTL => cpu_data_0_MC_OE, O => cpu_data(0) ); cpu_data_0_MC_REG : X_FF port map ( I => cpu_data_0_MC_D, CE => VCC, CLK => FOOBAR1_ctinst_7, SET => GND, RST => PRLD, O => cpu_data_0_MC_Q ); VCC_ONE : X_ONE port map ( O => VCC ); FOOBAR1_ctinst_0_15 : X_AND2 port map ( I0 => clear_n_II_UIM, I1 => clear_n_II_UIM, O => NlwInverterSignal_FOOBAR1_ctinst_0_OUT ); FOOBAR1_ctinst_4_16 : X_AND2 port map ( I0 => N159, I1 => N159, O => FOOBAR1_ctinst_4 ); FOOBAR1_ctinst_7_17 : X_AND2 port map ( I0 => N131, I1 => N131, O => FOOBAR1_ctinst_7 ); clear_n_II_UIM_18 : X_BUF port map ( I => clear_n, O => clear_n_II_UIM ); N159_19 : X_BUF port map ( I => N159_MC_Q, O => N159 ); N159_MC_REG : X_FF port map ( I => N159_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => PRLD, O => N159_MC_Q ); N159_MC_D1_20 : X_OR2 port map ( I0 => GND, I1 => GND, O => N159_MC_D1 ); N159_MC_D2_PT_0_21 : X_AND5 port map ( I0 => N129, I1 => N125, I2 => NlwInverterSignal_N159_MC_D2_PT_0_IN2, I3 => NlwInverterSignal_N159_MC_D2_PT_0_IN3, I4 => NlwInverterSignal_N159_MC_D2_PT_0_IN4, O => N159_MC_D2_PT_0 ); N159_MC_D2_PT_1_22 : X_AND5 port map ( I0 => NlwInverterSignal_N159_MC_D2_PT_1_IN0, I1 => NlwInverterSignal_N159_MC_D2_PT_1_IN1, I2 => NlwInverterSignal_N159_MC_D2_PT_1_IN2, I3 => N126, I4 => NlwInverterSignal_N159_MC_D2_PT_1_IN4, O => N159_MC_D2_PT_1 ); N159_MC_D2_23 : X_OR2 port map ( I0 => N159_MC_D2_PT_0, I1 => N159_MC_D2_PT_1, O => N159_MC_D2 ); N159_MC_XOR : X_XOR2 port map ( I0 => N159_MC_D1, I1 => N159_MC_D2, O => N159_MC_D ); N129_24 : X_BUF port map ( I => N129_MC_Q, O => N129 ); N129_MC_REG : X_FF port map ( I => N129_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => PRLD, O => N129_MC_Q ); N129_MC_D1_25 : X_OR2 port map ( I0 => GND, I1 => GND, O => N129_MC_D1 ); N129_MC_D2_PT_0_26 : X_AND2 port map ( I0 => NlwInverterSignal_N129_MC_D2_PT_0_IN0, I1 => N125, O => N129_MC_D2_PT_0 ); N129_MC_D2_PT_1_27 : X_AND2 port map ( I0 => NlwInverterSignal_N129_MC_D2_PT_1_IN0, I1 => N126, O => N129_MC_D2_PT_1 ); N129_MC_D2_PT_2_28 : X_AND3 port map ( I0 => NlwInverterSignal_N129_MC_D2_PT_2_IN0, I1 => NlwInverterSignal_N129_MC_D2_PT_2_IN1, I2 => NlwInverterSignal_N129_MC_D2_PT_2_IN2, O => N129_MC_D2_PT_2 ); N129_MC_D2_29 : X_OR3 port map ( I0 => N129_MC_D2_PT_0, I1 => N129_MC_D2_PT_1, I2 => N129_MC_D2_PT_2, O => N129_MC_D2 ); N129_MC_XOR : X_XOR2 port map ( I0 => NlwInverterSignal_N129_MC_XOR_IN0, I1 => N129_MC_D2, O => N129_MC_D ); N125_30 : X_BUF port map ( I => N125_MC_Q, O => N125 ); N125_MC_REG : X_FF port map ( I => N125_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => PRLD, O => N125_MC_Q ); N125_MC_D1_PT_0_31 : X_AND2 port map ( I0 => N127, I1 => N127, O => N125_MC_D1_PT_0 ); N125_MC_D1_32 : X_OR2 port map ( I0 => N125_MC_D1_PT_0, I1 => N125_MC_D1_PT_0, O => N125_MC_D1 ); N125_MC_D2_33 : X_OR2 port map ( I0 => GND, I1 => GND, O => N125_MC_D2 ); N125_MC_XOR : X_XOR2 port map ( I0 => N125_MC_D1, I1 => N125_MC_D2, O => N125_MC_D ); N127_34 : X_BUF port map ( I => N127_MC_Q, O => N127 ); N127_MC_REG : X_FF port map ( I => b_quad_II_IREG, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => PRLD, O => N127_MC_Q ); b_quad_II_IREG_35 : X_BUF port map ( I => b_quad, O => b_quad_II_IREG ); clk_II_FCLK_36 : X_BUF port map ( I => clk, O => clk_II_FCLK ); N126_37 : X_BUF port map ( I => N126_MC_Q, O => N126 ); N126_MC_REG : X_FF port map ( I => N126_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => PRLD, O => N126_MC_Q ); N126_MC_D1_PT_0_38 : X_AND2 port map ( I0 => N128, I1 => N128, O => N126_MC_D1_PT_0 ); N126_MC_D1_39 : X_OR2 port map ( I0 => N126_MC_D1_PT_0, I1 => N126_MC_D1_PT_0, O => N126_MC_D1 ); N126_MC_D2_40 : X_OR2 port map ( I0 => GND, I1 => GND, O => N126_MC_D2 ); N126_MC_XOR : X_XOR2 port map ( I0 => N126_MC_D1, I1 => N126_MC_D2, O => N126_MC_D ); N128_41 : X_BUF port map ( I => N128_MC_Q, O => N128 ); N128_MC_REG : X_FF port map ( I => a_quad_II_IREG, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => PRLD, O => N128_MC_Q ); a_quad_II_IREG_42 : X_BUF port map ( I => a_quad, O => a_quad_II_IREG ); N131_43 : X_BUF port map ( I => N131_MC_Q, O => N131 ); N131_MC_REG : X_FF port map ( I => N131_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => PRLD, O => N131_MC_Q ); N131_MC_D1_PT_0_44 : X_AND2 port map ( I0 => N158, I1 => N158, O => N131_MC_D1_PT_0 ); N131_MC_D1_45 : X_OR2 port map ( I0 => N131_MC_D1_PT_0, I1 => N131_MC_D1_PT_0, O => N131_MC_D1 ); N131_MC_D2_46 : X_OR2 port map ( I0 => GND, I1 => GND, O => N131_MC_D2 ); N131_MC_XOR : X_XOR2 port map ( I0 => N131_MC_D1, I1 => N131_MC_D2, O => N131_MC_D ); N158_47 : X_BUF port map ( I => N158_MC_Q, O => N158 ); N158_MC_REG : X_FF port map ( I => N158_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => PRLD, O => N158_MC_Q ); N158_MC_D1_PT_0_48 : X_AND2 port map ( I0 => read_n_II_UIM, I1 => read_n_II_UIM, O => N158_MC_D1_PT_0 ); N158_MC_D1_49 : X_OR2 port map ( I0 => N158_MC_D1_PT_0, I1 => N158_MC_D1_PT_0, O => N158_MC_D1 ); N158_MC_D2_50 : X_OR2 port map ( I0 => GND, I1 => GND, O => N158_MC_D2 ); N158_MC_XOR : X_XOR2 port map ( I0 => NlwInverterSignal_N158_MC_XOR_IN0, I1 => N158_MC_D2, O => N158_MC_D ); read_n_II_UIM_51 : X_BUF port map ( I => read_n, O => read_n_II_UIM ); cpu_data_0_MC_D1_PT_0_52 : X_AND2 port map ( I0 => N117, I1 => N117, O => cpu_data_0_MC_D1_PT_0 ); cpu_data_0_MC_D1_53 : X_OR2 port map ( I0 => cpu_data_0_MC_D1_PT_0, I1 => cpu_data_0_MC_D1_PT_0, O => cpu_data_0_MC_D1 ); cpu_data_0_MC_D2_54 : X_OR2 port map ( I0 => GND, I1 => GND, O => cpu_data_0_MC_D2 ); cpu_data_0_MC_XOR : X_XOR2 port map ( I0 => cpu_data_0_MC_D1, I1 => cpu_data_0_MC_D2, O => cpu_data_0_MC_D ); cpu_data_0_MC_OE_55 : X_BUF port map ( I => cpu_data_0_MC_BUFOE_OUT, O => cpu_data_0_MC_OE ); cpu_data_0_MC_BUFOE : X_BUF port map ( I => FOOBAR1_ctinst_7, O => cpu_data_0_MC_BUFOE_OUT ); N117_56 : X_BUF port map ( I => N117_MC_Q, O => N117 ); N117_MC_R_OR_PRLD_57 : X_OR2 port map ( I0 => FOOBAR1_ctinst_0, I1 => PRLD, O => N117_MC_R_OR_PRLD ); N117_MC_REG : X_FF port map ( I => N117_MC_D, CE => FOOBAR1_ctinst_4, CLK => clk_II_FCLK, SET => GND, RST => N117_MC_R_OR_PRLD, O => N117_MC_Q ); N117_MC_D1_58 : X_OR2 port map ( I0 => GND, I1 => GND, O => N117_MC_D1 ); N117_MC_D2_PT_0_59 : X_AND2 port map ( I0 => N117, I1 => N117, O => N117_MC_D2_PT_0 ); N117_MC_D2_60 : X_OR2 port map ( I0 => N117_MC_D2_PT_0, I1 => N117_MC_D2_PT_0, O => N117_MC_D2 ); N117_MC_XOR : X_XOR2 port map ( I0 => NlwInverterSignal_N117_MC_XOR_IN0, I1 => N117_MC_D2, O => N117_MC_D ); cpu_data_1_Q : X_TRI port map ( I => cpu_data_1_MC_Q, CTL => cpu_data_1_MC_OE, O => cpu_data(1) ); cpu_data_1_MC_REG : X_FF port map ( I => cpu_data_1_MC_D, CE => VCC, CLK => FOOBAR1_ctinst_7, SET => GND, RST => PRLD, O => cpu_data_1_MC_Q ); cpu_data_1_MC_D1_PT_0_61 : X_AND2 port map ( I0 => N118, I1 => N118, O => cpu_data_1_MC_D1_PT_0 ); cpu_data_1_MC_D1_62 : X_OR2 port map ( I0 => cpu_data_1_MC_D1_PT_0, I1 => cpu_data_1_MC_D1_PT_0, O => cpu_data_1_MC_D1 ); cpu_data_1_MC_D2_63 : X_OR2 port map ( I0 => GND, I1 => GND, O => cpu_data_1_MC_D2 ); cpu_data_1_MC_XOR : X_XOR2 port map ( I0 => cpu_data_1_MC_D1, I1 => cpu_data_1_MC_D2, O => cpu_data_1_MC_D ); cpu_data_1_MC_OE_64 : X_BUF port map ( I => cpu_data_1_MC_BUFOE_OUT, O => cpu_data_1_MC_OE ); cpu_data_1_MC_BUFOE : X_BUF port map ( I => FOOBAR1_ctinst_7, O => cpu_data_1_MC_BUFOE_OUT ); N118_65 : X_BUF port map ( I => N118_MC_Q, O => N118 ); N118_MC_R_OR_PRLD_66 : X_OR2 port map ( I0 => FOOBAR1_ctinst_0, I1 => PRLD, O => N118_MC_R_OR_PRLD ); N118_MC_REG : X_FF port map ( I => N118_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => N118_MC_R_OR_PRLD, O => N118_MC_Q ); N118_MC_D1_67 : X_OR2 port map ( I0 => GND, I1 => GND, O => N118_MC_D1 ); N118_MC_D2_PT_0_68 : X_AND3 port map ( I0 => N117, I1 => N129, I2 => N159, O => N118_MC_D2_PT_0 ); N118_MC_D2_PT_1_69 : X_AND3 port map ( I0 => NlwInverterSignal_N118_MC_D2_PT_1_IN0, I1 => NlwInverterSignal_N118_MC_D2_PT_1_IN1, I2 => N159, O => N118_MC_D2_PT_1 ); N118_MC_D2_70 : X_OR2 port map ( I0 => N118_MC_D2_PT_0, I1 => N118_MC_D2_PT_1, O => N118_MC_D2 ); N118_MC_D_71 : X_XOR2 port map ( I0 => N118_MC_D_TFF, I1 => N118_MC_Q, O => N118_MC_D ); N118_MC_XOR : X_XOR2 port map ( I0 => N118_MC_D1, I1 => N118_MC_D2, O => N118_MC_D_TFF ); cpu_data_2_Q : X_TRI port map ( I => cpu_data_2_MC_Q, CTL => cpu_data_2_MC_OE, O => cpu_data(2) ); cpu_data_2_MC_REG : X_FF port map ( I => cpu_data_2_MC_D, CE => VCC, CLK => FOOBAR1_ctinst_7, SET => GND, RST => PRLD, O => cpu_data_2_MC_Q ); cpu_data_2_MC_D1_PT_0_72 : X_AND2 port map ( I0 => N119, I1 => N119, O => cpu_data_2_MC_D1_PT_0 ); cpu_data_2_MC_D1_73 : X_OR2 port map ( I0 => cpu_data_2_MC_D1_PT_0, I1 => cpu_data_2_MC_D1_PT_0, O => cpu_data_2_MC_D1 ); cpu_data_2_MC_D2_74 : X_OR2 port map ( I0 => GND, I1 => GND, O => cpu_data_2_MC_D2 ); cpu_data_2_MC_XOR : X_XOR2 port map ( I0 => cpu_data_2_MC_D1, I1 => cpu_data_2_MC_D2, O => cpu_data_2_MC_D ); cpu_data_2_MC_OE_75 : X_BUF port map ( I => cpu_data_2_MC_BUFOE_OUT, O => cpu_data_2_MC_OE ); cpu_data_2_MC_BUFOE : X_BUF port map ( I => FOOBAR1_ctinst_7, O => cpu_data_2_MC_BUFOE_OUT ); N119_76 : X_BUF port map ( I => N119_MC_Q, O => N119 ); N119_MC_R_OR_PRLD_77 : X_OR2 port map ( I0 => FOOBAR1_ctinst_0, I1 => PRLD, O => N119_MC_R_OR_PRLD ); N119_MC_REG : X_FF port map ( I => N119_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => N119_MC_R_OR_PRLD, O => N119_MC_Q ); N119_MC_D1_78 : X_OR2 port map ( I0 => GND, I1 => GND, O => N119_MC_D1 ); N119_MC_D2_PT_0_79 : X_AND4 port map ( I0 => N117, I1 => N129, I2 => N159, I3 => N118, O => N119_MC_D2_PT_0 ); N119_MC_D2_PT_1_80 : X_AND4 port map ( I0 => NlwInverterSignal_N119_MC_D2_PT_1_IN0, I1 => NlwInverterSignal_N119_MC_D2_PT_1_IN1, I2 => N159, I3 => NlwInverterSignal_N119_MC_D2_PT_1_IN3, O => N119_MC_D2_PT_1 ); N119_MC_D2_81 : X_OR2 port map ( I0 => N119_MC_D2_PT_0, I1 => N119_MC_D2_PT_1, O => N119_MC_D2 ); N119_MC_D_82 : X_XOR2 port map ( I0 => N119_MC_D_TFF, I1 => N119_MC_Q, O => N119_MC_D ); N119_MC_XOR : X_XOR2 port map ( I0 => N119_MC_D1, I1 => N119_MC_D2, O => N119_MC_D_TFF ); cpu_data_3_Q : X_TRI port map ( I => cpu_data_3_MC_Q, CTL => cpu_data_3_MC_OE, O => cpu_data(3) ); cpu_data_3_MC_REG : X_FF port map ( I => cpu_data_3_MC_D, CE => VCC, CLK => FOOBAR1_ctinst_7, SET => GND, RST => PRLD, O => cpu_data_3_MC_Q ); cpu_data_3_MC_D1_PT_0_83 : X_AND2 port map ( I0 => N120, I1 => N120, O => cpu_data_3_MC_D1_PT_0 ); cpu_data_3_MC_D1_84 : X_OR2 port map ( I0 => cpu_data_3_MC_D1_PT_0, I1 => cpu_data_3_MC_D1_PT_0, O => cpu_data_3_MC_D1 ); cpu_data_3_MC_D2_85 : X_OR2 port map ( I0 => GND, I1 => GND, O => cpu_data_3_MC_D2 ); cpu_data_3_MC_XOR : X_XOR2 port map ( I0 => cpu_data_3_MC_D1, I1 => cpu_data_3_MC_D2, O => cpu_data_3_MC_D ); cpu_data_3_MC_OE_86 : X_BUF port map ( I => cpu_data_3_MC_BUFOE_OUT, O => cpu_data_3_MC_OE ); cpu_data_3_MC_BUFOE : X_BUF port map ( I => FOOBAR1_ctinst_7, O => cpu_data_3_MC_BUFOE_OUT ); N120_87 : X_BUF port map ( I => N120_MC_Q, O => N120 ); N120_MC_R_OR_PRLD_88 : X_OR2 port map ( I0 => FOOBAR1_ctinst_0, I1 => PRLD, O => N120_MC_R_OR_PRLD ); N120_MC_REG : X_FF port map ( I => N120_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => N120_MC_R_OR_PRLD, O => N120_MC_Q ); N120_MC_D1_89 : X_OR2 port map ( I0 => GND, I1 => GND, O => N120_MC_D1 ); N120_MC_D2_PT_0_90 : X_AND5 port map ( I0 => N117, I1 => N129, I2 => N159, I3 => N118, I4 => N119, O => N120_MC_D2_PT_0 ); N120_MC_D2_PT_1_91 : X_AND5 port map ( I0 => NlwInverterSignal_N120_MC_D2_PT_1_IN0, I1 => NlwInverterSignal_N120_MC_D2_PT_1_IN1, I2 => N159, I3 => NlwInverterSignal_N120_MC_D2_PT_1_IN3, I4 => NlwInverterSignal_N120_MC_D2_PT_1_IN4, O => N120_MC_D2_PT_1 ); N120_MC_D2_92 : X_OR2 port map ( I0 => N120_MC_D2_PT_0, I1 => N120_MC_D2_PT_1, O => N120_MC_D2 ); N120_MC_D_93 : X_XOR2 port map ( I0 => N120_MC_D_TFF, I1 => N120_MC_Q, O => N120_MC_D ); N120_MC_XOR : X_XOR2 port map ( I0 => N120_MC_D1, I1 => N120_MC_D2, O => N120_MC_D_TFF ); cpu_data_4_Q : X_TRI port map ( I => cpu_data_4_MC_Q, CTL => cpu_data_4_MC_OE, O => cpu_data(4) ); cpu_data_4_MC_REG : X_FF port map ( I => cpu_data_4_MC_D, CE => VCC, CLK => FOOBAR1_ctinst_7, SET => GND, RST => PRLD, O => cpu_data_4_MC_Q ); cpu_data_4_MC_D1_PT_0_94 : X_AND2 port map ( I0 => N121, I1 => N121, O => cpu_data_4_MC_D1_PT_0 ); cpu_data_4_MC_D1_95 : X_OR2 port map ( I0 => cpu_data_4_MC_D1_PT_0, I1 => cpu_data_4_MC_D1_PT_0, O => cpu_data_4_MC_D1 ); cpu_data_4_MC_D2_96 : X_OR2 port map ( I0 => GND, I1 => GND, O => cpu_data_4_MC_D2 ); cpu_data_4_MC_XOR : X_XOR2 port map ( I0 => cpu_data_4_MC_D1, I1 => cpu_data_4_MC_D2, O => cpu_data_4_MC_D ); cpu_data_4_MC_OE_97 : X_BUF port map ( I => cpu_data_4_MC_BUFOE_OUT, O => cpu_data_4_MC_OE ); cpu_data_4_MC_BUFOE : X_BUF port map ( I => FOOBAR1_ctinst_7, O => cpu_data_4_MC_BUFOE_OUT ); N121_98 : X_BUF port map ( I => N121_MC_Q, O => N121 ); N121_MC_R_OR_PRLD_99 : X_OR2 port map ( I0 => FOOBAR1_ctinst_0, I1 => PRLD, O => N121_MC_R_OR_PRLD ); N121_MC_REG : X_FF port map ( I => N121_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => N121_MC_R_OR_PRLD, O => N121_MC_Q ); N121_MC_D1_100 : X_OR2 port map ( I0 => GND, I1 => GND, O => N121_MC_D1 ); N121_MC_D2_PT_0_101 : X_AND6 port map ( I0 => N117, I1 => N129, I2 => N159, I3 => N118, I4 => N119, I5 => N120, O => N121_MC_D2_PT_0 ); N121_MC_D2_PT_1_102 : X_AND6 port map ( I0 => NlwInverterSignal_N121_MC_D2_PT_1_IN0, I1 => NlwInverterSignal_N121_MC_D2_PT_1_IN1, I2 => N159, I3 => NlwInverterSignal_N121_MC_D2_PT_1_IN3, I4 => NlwInverterSignal_N121_MC_D2_PT_1_IN4, I5 => NlwInverterSignal_N121_MC_D2_PT_1_IN5, O => N121_MC_D2_PT_1 ); N121_MC_D2_103 : X_OR2 port map ( I0 => N121_MC_D2_PT_0, I1 => N121_MC_D2_PT_1, O => N121_MC_D2 ); N121_MC_D_104 : X_XOR2 port map ( I0 => N121_MC_D_TFF, I1 => N121_MC_Q, O => N121_MC_D ); N121_MC_XOR : X_XOR2 port map ( I0 => N121_MC_D1, I1 => N121_MC_D2, O => N121_MC_D_TFF ); cpu_data_5_Q : X_TRI port map ( I => cpu_data_5_MC_Q, CTL => cpu_data_5_MC_OE, O => cpu_data(5) ); cpu_data_5_MC_REG : X_FF port map ( I => cpu_data_5_MC_D, CE => VCC, CLK => FOOBAR1_ctinst_7, SET => GND, RST => PRLD, O => cpu_data_5_MC_Q ); cpu_data_5_MC_D1_PT_0_105 : X_AND2 port map ( I0 => N122, I1 => N122, O => cpu_data_5_MC_D1_PT_0 ); cpu_data_5_MC_D1_106 : X_OR2 port map ( I0 => cpu_data_5_MC_D1_PT_0, I1 => cpu_data_5_MC_D1_PT_0, O => cpu_data_5_MC_D1 ); cpu_data_5_MC_D2_107 : X_OR2 port map ( I0 => GND, I1 => GND, O => cpu_data_5_MC_D2 ); cpu_data_5_MC_XOR : X_XOR2 port map ( I0 => cpu_data_5_MC_D1, I1 => cpu_data_5_MC_D2, O => cpu_data_5_MC_D ); cpu_data_5_MC_OE_108 : X_BUF port map ( I => cpu_data_5_MC_BUFOE_OUT, O => cpu_data_5_MC_OE ); cpu_data_5_MC_BUFOE : X_BUF port map ( I => FOOBAR1_ctinst_7, O => cpu_data_5_MC_BUFOE_OUT ); N122_109 : X_BUF port map ( I => N122_MC_Q, O => N122 ); N122_MC_R_OR_PRLD_110 : X_OR2 port map ( I0 => FOOBAR1_ctinst_0, I1 => PRLD, O => N122_MC_R_OR_PRLD ); N122_MC_REG : X_FF port map ( I => N122_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => N122_MC_R_OR_PRLD, O => N122_MC_Q ); N122_MC_D1_111 : X_OR2 port map ( I0 => GND, I1 => GND, O => N122_MC_D1 ); N122_MC_D2_PT_0_112 : X_AND7 port map ( I0 => N117, I1 => N129, I2 => N159, I3 => N118, I4 => N119, I5 => N120, I6 => N121, O => N122_MC_D2_PT_0 ); N122_MC_D2_PT_1_113 : X_AND7 port map ( I0 => NlwInverterSignal_N122_MC_D2_PT_1_IN0, I1 => NlwInverterSignal_N122_MC_D2_PT_1_IN1, I2 => N159, I3 => NlwInverterSignal_N122_MC_D2_PT_1_IN3, I4 => NlwInverterSignal_N122_MC_D2_PT_1_IN4, I5 => NlwInverterSignal_N122_MC_D2_PT_1_IN5, I6 => NlwInverterSignal_N122_MC_D2_PT_1_IN6, O => N122_MC_D2_PT_1 ); N122_MC_D2_114 : X_OR2 port map ( I0 => N122_MC_D2_PT_0, I1 => N122_MC_D2_PT_1, O => N122_MC_D2 ); N122_MC_D_115 : X_XOR2 port map ( I0 => N122_MC_D_TFF, I1 => N122_MC_Q, O => N122_MC_D ); N122_MC_XOR : X_XOR2 port map ( I0 => N122_MC_D1, I1 => N122_MC_D2, O => N122_MC_D_TFF ); cpu_data_6_Q : X_TRI port map ( I => cpu_data_6_MC_Q, CTL => cpu_data_6_MC_OE, O => cpu_data(6) ); cpu_data_6_MC_REG : X_FF port map ( I => cpu_data_6_MC_D, CE => VCC, CLK => FOOBAR1_ctinst_7, SET => GND, RST => PRLD, O => cpu_data_6_MC_Q ); cpu_data_6_MC_D1_PT_0_116 : X_AND2 port map ( I0 => N123, I1 => N123, O => cpu_data_6_MC_D1_PT_0 ); cpu_data_6_MC_D1_117 : X_OR2 port map ( I0 => cpu_data_6_MC_D1_PT_0, I1 => cpu_data_6_MC_D1_PT_0, O => cpu_data_6_MC_D1 ); cpu_data_6_MC_D2_118 : X_OR2 port map ( I0 => GND, I1 => GND, O => cpu_data_6_MC_D2 ); cpu_data_6_MC_XOR : X_XOR2 port map ( I0 => cpu_data_6_MC_D1, I1 => cpu_data_6_MC_D2, O => cpu_data_6_MC_D ); cpu_data_6_MC_OE_119 : X_BUF port map ( I => cpu_data_6_MC_BUFOE_OUT, O => cpu_data_6_MC_OE ); cpu_data_6_MC_BUFOE : X_BUF port map ( I => FOOBAR1_ctinst_7, O => cpu_data_6_MC_BUFOE_OUT ); N123_120 : X_BUF port map ( I => N123_MC_Q, O => N123 ); N123_MC_R_OR_PRLD_121 : X_OR2 port map ( I0 => FOOBAR1_ctinst_0, I1 => PRLD, O => N123_MC_R_OR_PRLD ); N123_MC_REG : X_FF port map ( I => N123_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => N123_MC_R_OR_PRLD, O => N123_MC_Q ); N123_MC_D1_122 : X_OR2 port map ( I0 => GND, I1 => GND, O => N123_MC_D1 ); N123_MC_D2_PT_0_123 : X_AND8 port map ( I0 => N117, I1 => N129, I2 => N159, I3 => N118, I4 => N119, I5 => N120, I6 => N121, I7 => N122, O => N123_MC_D2_PT_0 ); N123_MC_D2_PT_1_124 : X_AND8 port map ( I0 => NlwInverterSignal_N123_MC_D2_PT_1_IN0, I1 => NlwInverterSignal_N123_MC_D2_PT_1_IN1, I2 => N159, I3 => NlwInverterSignal_N123_MC_D2_PT_1_IN3, I4 => NlwInverterSignal_N123_MC_D2_PT_1_IN4, I5 => NlwInverterSignal_N123_MC_D2_PT_1_IN5, I6 => NlwInverterSignal_N123_MC_D2_PT_1_IN6, I7 => NlwInverterSignal_N123_MC_D2_PT_1_IN7, O => N123_MC_D2_PT_1 ); N123_MC_D2_125 : X_OR2 port map ( I0 => N123_MC_D2_PT_0, I1 => N123_MC_D2_PT_1, O => N123_MC_D2 ); N123_MC_D_126 : X_XOR2 port map ( I0 => N123_MC_D_TFF, I1 => N123_MC_Q, O => N123_MC_D ); N123_MC_XOR : X_XOR2 port map ( I0 => N123_MC_D1, I1 => N123_MC_D2, O => N123_MC_D_TFF ); cpu_data_7_Q : X_TRI port map ( I => cpu_data_7_MC_Q, CTL => cpu_data_7_MC_OE, O => cpu_data(7) ); cpu_data_7_MC_REG : X_FF port map ( I => cpu_data_7_MC_D, CE => VCC, CLK => FOOBAR1_ctinst_7, SET => GND, RST => PRLD, O => cpu_data_7_MC_Q ); cpu_data_7_MC_D1_PT_0_127 : X_AND2 port map ( I0 => N124, I1 => N124, O => cpu_data_7_MC_D1_PT_0 ); cpu_data_7_MC_D1_128 : X_OR2 port map ( I0 => cpu_data_7_MC_D1_PT_0, I1 => cpu_data_7_MC_D1_PT_0, O => cpu_data_7_MC_D1 ); cpu_data_7_MC_D2_129 : X_OR2 port map ( I0 => GND, I1 => GND, O => cpu_data_7_MC_D2 ); cpu_data_7_MC_XOR : X_XOR2 port map ( I0 => cpu_data_7_MC_D1, I1 => cpu_data_7_MC_D2, O => cpu_data_7_MC_D ); cpu_data_7_MC_OE_130 : X_BUF port map ( I => cpu_data_7_MC_BUFOE_OUT, O => cpu_data_7_MC_OE ); cpu_data_7_MC_BUFOE : X_BUF port map ( I => FOOBAR1_ctinst_7, O => cpu_data_7_MC_BUFOE_OUT ); N124_131 : X_BUF port map ( I => N124_MC_Q, O => N124 ); N124_MC_R_OR_PRLD_132 : X_OR2 port map ( I0 => FOOBAR1_ctinst_0, I1 => PRLD, O => N124_MC_R_OR_PRLD ); N124_MC_REG : X_FF port map ( I => N124_MC_D, CE => VCC, CLK => clk_II_FCLK, SET => GND, RST => N124_MC_R_OR_PRLD, O => N124_MC_Q ); N124_MC_D1_133 : X_OR2 port map ( I0 => GND, I1 => GND, O => N124_MC_D1 ); N124_MC_D2_PT_0_134 : X_AND16 port map ( I0 => N117, I1 => N129, I2 => N159, I3 => N118, I4 => N119, I5 => N120, I6 => N121, I7 => N122, I8 => N123, I9 => VCC, I10 => VCC, I11 => VCC, I12 => VCC, I13 => VCC, I14 => VCC, I15 => VCC, O => N124_MC_D2_PT_0 ); N124_MC_D2_PT_1_135 : X_AND16 port map ( I0 => NlwInverterSignal_N124_MC_D2_PT_1_IN0, I1 => NlwInverterSignal_N124_MC_D2_PT_1_IN1, I2 => N159, I3 => NlwInverterSignal_N124_MC_D2_PT_1_IN3, I4 => NlwInverterSignal_N124_MC_D2_PT_1_IN4, I5 => NlwInverterSignal_N124_MC_D2_PT_1_IN5, I6 => NlwInverterSignal_N124_MC_D2_PT_1_IN6, I7 => NlwInverterSignal_N124_MC_D2_PT_1_IN7, I8 => NlwInverterSignal_N124_MC_D2_PT_1_IN8, I9 => VCC, I10 => VCC, I11 => VCC, I12 => VCC, I13 => VCC, I14 => VCC, I15 => VCC, O => N124_MC_D2_PT_1 ); N124_MC_D2_136 : X_OR2 port map ( I0 => N124_MC_D2_PT_0, I1 => N124_MC_D2_PT_1, O => N124_MC_D2 ); N124_MC_D_137 : X_XOR2 port map ( I0 => N124_MC_D_TFF, I1 => N124_MC_Q, O => N124_MC_D ); N124_MC_XOR : X_XOR2 port map ( I0 => N124_MC_D1, I1 => N124_MC_D2, O => N124_MC_D_TFF ); d_out_138 : X_BUF port map ( I => d_out_MC_Q, O => d_out ); d_out_MC_REG : X_BUF port map ( I => d_out_MC_D, O => d_out_MC_Q ); d_out_MC_D1_PT_0_139 : X_AND2 port map ( I0 => NlwInverterSignal_d_out_MC_D1_PT_0_IN0, I1 => d_in_II_UIM, O => d_out_MC_D1_PT_0 ); d_out_MC_D1_140 : X_OR2 port map ( I0 => d_out_MC_D1_PT_0, I1 => d_out_MC_D1_PT_0, O => d_out_MC_D1 ); d_out_MC_D2_141 : X_OR2 port map ( I0 => GND, I1 => GND, O => d_out_MC_D2 ); d_out_MC_XOR : X_XOR2 port map ( I0 => d_out_MC_D1, I1 => d_out_MC_D2, O => d_out_MC_D ); d_in_II_UIM_142 : X_BUF port map ( I => d_in, O => d_in_II_UIM ); NlwInverterBlock_b_out_MC_D1_PT_0_IN0 : X_INV port map ( I => a_in_II_UIM, O => NlwInverterSignal_b_out_MC_D1_PT_0_IN0 ); NlwInverterBlock_FOOBAR1_ctinst_0_OUT : X_INV port map ( I => NlwInverterSignal_FOOBAR1_ctinst_0_OUT, O => FOOBAR1_ctinst_0 ); NlwInverterBlock_N159_MC_D2_PT_0_IN2 : X_INV port map ( I => N127, O => NlwInverterSignal_N159_MC_D2_PT_0_IN2 ); NlwInverterBlock_N159_MC_D2_PT_0_IN3 : X_INV port map ( I => N126, O => NlwInverterSignal_N159_MC_D2_PT_0_IN3 ); NlwInverterBlock_N159_MC_D2_PT_0_IN4 : X_INV port map ( I => N128, O => NlwInverterSignal_N159_MC_D2_PT_0_IN4 ); NlwInverterBlock_N159_MC_D2_PT_1_IN0 : X_INV port map ( I => N129, O => NlwInverterSignal_N159_MC_D2_PT_1_IN0 ); NlwInverterBlock_N159_MC_D2_PT_1_IN1 : X_INV port map ( I => N125, O => NlwInverterSignal_N159_MC_D2_PT_1_IN1 ); NlwInverterBlock_N159_MC_D2_PT_1_IN2 : X_INV port map ( I => N127, O => NlwInverterSignal_N159_MC_D2_PT_1_IN2 ); NlwInverterBlock_N159_MC_D2_PT_1_IN4 : X_INV port map ( I => N128, O => NlwInverterSignal_N159_MC_D2_PT_1_IN4 ); NlwInverterBlock_N129_MC_D2_PT_0_IN0 : X_INV port map ( I => N129, O => NlwInverterSignal_N129_MC_D2_PT_0_IN0 ); NlwInverterBlock_N129_MC_D2_PT_1_IN0 : X_INV port map ( I => N129, O => NlwInverterSignal_N129_MC_D2_PT_1_IN0 ); NlwInverterBlock_N129_MC_D2_PT_2_IN0 : X_INV port map ( I => N125, O => NlwInverterSignal_N129_MC_D2_PT_2_IN0 ); NlwInverterBlock_N129_MC_D2_PT_2_IN1 : X_INV port map ( I => N126, O => NlwInverterSignal_N129_MC_D2_PT_2_IN1 ); NlwInverterBlock_N129_MC_D2_PT_2_IN2 : X_INV port map ( I => N128, O => NlwInverterSignal_N129_MC_D2_PT_2_IN2 ); NlwInverterBlock_N129_MC_XOR_IN0 : X_INV port map ( I => N129_MC_D1, O => NlwInverterSignal_N129_MC_XOR_IN0 ); NlwInverterBlock_N158_MC_XOR_IN0 : X_INV port map ( I => N158_MC_D1, O => NlwInverterSignal_N158_MC_XOR_IN0 ); NlwInverterBlock_N117_MC_XOR_IN0 : X_INV port map ( I => N117_MC_D1, O => NlwInverterSignal_N117_MC_XOR_IN0 ); NlwInverterBlock_N118_MC_D2_PT_1_IN0 : X_INV port map ( I => N117, O => NlwInverterSignal_N118_MC_D2_PT_1_IN0 ); NlwInverterBlock_N118_MC_D2_PT_1_IN1 : X_INV port map ( I => N129, O => NlwInverterSignal_N118_MC_D2_PT_1_IN1 ); NlwInverterBlock_N119_MC_D2_PT_1_IN0 : X_INV port map ( I => N117, O => NlwInverterSignal_N119_MC_D2_PT_1_IN0 ); NlwInverterBlock_N119_MC_D2_PT_1_IN1 : X_INV port map ( I => N129, O => NlwInverterSignal_N119_MC_D2_PT_1_IN1 ); NlwInverterBlock_N119_MC_D2_PT_1_IN3 : X_INV port map ( I => N118, O => NlwInverterSignal_N119_MC_D2_PT_1_IN3 ); NlwInverterBlock_N120_MC_D2_PT_1_IN0 : X_INV port map ( I => N117, O => NlwInverterSignal_N120_MC_D2_PT_1_IN0 ); NlwInverterBlock_N120_MC_D2_PT_1_IN1 : X_INV port map ( I => N129, O => NlwInverterSignal_N120_MC_D2_PT_1_IN1 ); NlwInverterBlock_N120_MC_D2_PT_1_IN3 : X_INV port map ( I => N118, O => NlwInverterSignal_N120_MC_D2_PT_1_IN3 ); NlwInverterBlock_N120_MC_D2_PT_1_IN4 : X_INV port map ( I => N119, O => NlwInverterSignal_N120_MC_D2_PT_1_IN4 ); NlwInverterBlock_N121_MC_D2_PT_1_IN0 : X_INV port map ( I => N117, O => NlwInverterSignal_N121_MC_D2_PT_1_IN0 ); NlwInverterBlock_N121_MC_D2_PT_1_IN1 : X_INV port map ( I => N129, O => NlwInverterSignal_N121_MC_D2_PT_1_IN1 ); NlwInverterBlock_N121_MC_D2_PT_1_IN3 : X_INV port map ( I => N118, O => NlwInverterSignal_N121_MC_D2_PT_1_IN3 ); NlwInverterBlock_N121_MC_D2_PT_1_IN4 : X_INV port map ( I => N119, O => NlwInverterSignal_N121_MC_D2_PT_1_IN4 ); NlwInverterBlock_N121_MC_D2_PT_1_IN5 : X_INV port map ( I => N120, O => NlwInverterSignal_N121_MC_D2_PT_1_IN5 ); NlwInverterBlock_N122_MC_D2_PT_1_IN0 : X_INV port map ( I => N117, O => NlwInverterSignal_N122_MC_D2_PT_1_IN0 ); NlwInverterBlock_N122_MC_D2_PT_1_IN1 : X_INV port map ( I => N129, O => NlwInverterSignal_N122_MC_D2_PT_1_IN1 ); NlwInverterBlock_N122_MC_D2_PT_1_IN3 : X_INV port map ( I => N118, O => NlwInverterSignal_N122_MC_D2_PT_1_IN3 ); NlwInverterBlock_N122_MC_D2_PT_1_IN4 : X_INV port map ( I => N119, O => NlwInverterSignal_N122_MC_D2_PT_1_IN4 ); NlwInverterBlock_N122_MC_D2_PT_1_IN5 : X_INV port map ( I => N120, O => NlwInverterSignal_N122_MC_D2_PT_1_IN5 ); NlwInverterBlock_N122_MC_D2_PT_1_IN6 : X_INV port map ( I => N121, O => NlwInverterSignal_N122_MC_D2_PT_1_IN6 ); NlwInverterBlock_N123_MC_D2_PT_1_IN0 : X_INV port map ( I => N117, O => NlwInverterSignal_N123_MC_D2_PT_1_IN0 ); NlwInverterBlock_N123_MC_D2_PT_1_IN1 : X_INV port map ( I => N129, O => NlwInverterSignal_N123_MC_D2_PT_1_IN1 ); NlwInverterBlock_N123_MC_D2_PT_1_IN3 : X_INV port map ( I => N118, O => NlwInverterSignal_N123_MC_D2_PT_1_IN3 ); NlwInverterBlock_N123_MC_D2_PT_1_IN4 : X_INV port map ( I => N119, O => NlwInverterSignal_N123_MC_D2_PT_1_IN4 ); NlwInverterBlock_N123_MC_D2_PT_1_IN5 : X_INV port map ( I => N120, O => NlwInverterSignal_N123_MC_D2_PT_1_IN5 ); NlwInverterBlock_N123_MC_D2_PT_1_IN6 : X_INV port map ( I => N121, O => NlwInverterSignal_N123_MC_D2_PT_1_IN6 ); NlwInverterBlock_N123_MC_D2_PT_1_IN7 : X_INV port map ( I => N122, O => NlwInverterSignal_N123_MC_D2_PT_1_IN7 ); NlwInverterBlock_N124_MC_D2_PT_1_IN0 : X_INV port map ( I => N117, O => NlwInverterSignal_N124_MC_D2_PT_1_IN0 ); NlwInverterBlock_N124_MC_D2_PT_1_IN1 : X_INV port map ( I => N129, O => NlwInverterSignal_N124_MC_D2_PT_1_IN1 ); NlwInverterBlock_N124_MC_D2_PT_1_IN3 : X_INV port map ( I => N118, O => NlwInverterSignal_N124_MC_D2_PT_1_IN3 ); NlwInverterBlock_N124_MC_D2_PT_1_IN4 : X_INV port map ( I => N119, O => NlwInverterSignal_N124_MC_D2_PT_1_IN4 ); NlwInverterBlock_N124_MC_D2_PT_1_IN5 : X_INV port map ( I => N120, O => NlwInverterSignal_N124_MC_D2_PT_1_IN5 ); NlwInverterBlock_N124_MC_D2_PT_1_IN6 : X_INV port map ( I => N121, O => NlwInverterSignal_N124_MC_D2_PT_1_IN6 ); NlwInverterBlock_N124_MC_D2_PT_1_IN7 : X_INV port map ( I => N122, O => NlwInverterSignal_N124_MC_D2_PT_1_IN7 ); NlwInverterBlock_N124_MC_D2_PT_1_IN8 : X_INV port map ( I => N123, O => NlwInverterSignal_N124_MC_D2_PT_1_IN8 ); NlwInverterBlock_d_out_MC_D1_PT_0_IN0 : X_INV port map ( I => c_in_II_UIM, O => NlwInverterSignal_d_out_MC_D1_PT_0_IN0 ); NlwBlockROC : ROC generic map ( WIDTH => 100 ns) port map (O => PRLD); end Structure;