\t (00:00:00) allegro 16.6-2015 S051 (v16-6-112EA) Windows 32
\t (00:00:00)     Journal start - Wed Dec 16 10:44:59 2015
\t (00:00:00)         Host=LONO3 User=craig Pid=6296 CPUs=8
\t (00:00:00) CmdLine= C:\Cadence\SPB_16.6\tools\pcb\bin\allegro.exe
\t (00:00:00) 
\t (00:00:02) Opening existing design...
\d (00:00:03) Design opened: C:/AA project data/orcaddata/oasis5/multi processor version play n learn/6 port expansion board/O5 6 port expander.brd
\i (00:00:03) trapsize 4164
\i (00:00:03) trapsize 4107
\i (00:00:03) trapsize 4173
\i (00:00:03) trapsize 4173
\i (00:00:04) placementedit 
\i (00:00:13) opencd 'C:/AA project data/orcaddata/oasis5/O5 boards MX470/O5 daughter board/O5 daughter board.brd' 
\t (00:00:14) Opening existing design...
\i (00:00:14) trapsize 4173
\t (00:00:14)     Journal end - Wed Dec 16 10:45:13 2015