SERIAL INPUT / OUTPUT PORT TPU FUNCTION (SIOP) ============================================== FUNCTION DESCRIPTION --------------------- The Serial Input/Output Port (SIOP) TPU function uses two or three TPU channels to form a uni or bi-directional synchronous serial port that can be used to communicate with a wide variety of devices. Features such as baud rate and transfer size are user programmable. The function can also produce a clock only, when it uses just one channel. The SIOP TPU function has been designed to closely resemble the SIOP hardware port found on some Motorola MCUs and can be used to add serial capabilities to a device without a serial port, or extend the capabilities of one with a hardware synchronous port. The function operates in master mode (i.e. the TPU always generates the clock) and the following features are programmable by the user:- i) Choice of clock only (1 channel), clock + transmit (2 channels), clock + receive (2 channels) or clock + transmit + receive (3 channels) operating modes. ii) Baud rate period is freely programmable by the user over a 15 bit range of TCR1 counts. iii) Selection of msb or lsb first shift direction. iv) Variable transfer size from 1 to 16 bits. v) Clock polarity is programmable. When a transfer of data is complete the SIOP function notifies the host CPU by issuing an interrupt request. The arrangement of the multiple SIOP channels is fixed:- the data out channel is the channel above the clock channel and the data in channel is the channel below the clock channel. In clock only or a uni-directional mode, the unused TPU channels are free to run other TPU functions. FUNCTION CODE SIZE ------------------- The code size of a TPU function is important when assessing which combination of functions can fit into a given microcode space in ROM or emulation memory. The code size of the SIOP function is:- 31 æinstructions + 8 entries = 39 long words total. CONTROL BITS ------------ Host Sequence Bits:- HSQ1 HSQ0 ACTION ---- ---- ------ 0 0 Clock only active. 0 1 Clock + Transmit channels active. 1 0 Clock + Receive channels active. 1 1 Clock + Transmit + Receive channels active. Host Service Requests:- HSR1 HSR0 ACTION ---- ---- ------ X 0 No Action 0 1 No Action 1 1 Initialise Clock and start XFER. PARAMETERS ----------- The following sections describe the parameters used in the SIOP function. The location and size of each parameter is given after the name. Note that only the clock channel requires any programming by the user - the data in and out channels are controlled entirely by the TPU under microcode control. CHAN_CONTROL Parameter0, bits 0..9 This 9 bit CPU written parameter is used to setup the clock polarity for the SIOP data transfer. The valid values for CHAN_CONTROL for this function are given below. CHAN_CONTROL must be written by the host prior to issuing the host service request (HSR) to initialise the function. CHAN_CONTROL 8 7 6 5 4 3 2 1 0 RESULTING ACTION ------------------ -------------------------- 0 1 0 0 0 1 1 0 1 Data valid on clock Falling edge. 0 1 0 0 0 1 1 1 0 Data valid on clock Rising edge. NOTE: Other values of CHAN_CONTROL may result in indeterminate operation. BIT_D Parameter0, bit 15 BIT_D is a CPU written bit that determines the direction of shift of the SIOP data. If BIT_D is zero then SIOP_DATA is right shifted (lsb first) and if BIT_D is one then SIOP_DATA is left shifted (msb first). HALF_PERIOD Parameter1, bits 0..15 This CPU written parameter defines the baud rate of the SIOP function. The value contained in HALF_PERIOD is the number of TCR1 counts for a half SIOP clock period. E.g. for a 50KHz baud rate, with a TCR1 period of 240nS, the value [(1/50KHz)/2]/240ns = 42 should be written to HALF_PERIOD. The range for HALF_PERIOD is 1 to $8000, although the minimum value in practice will be limited by other system conditions - see notes on use and performance of SIOP function. BIT_COUNT Parameter2, bits 0..15 This parameter is used by the TPU to count down the number bits remaining while a transfer is in progress. During the SIOP initialisation state, BIT_COUNT is loaded with the value contained in XFER_SIZE. It is then decremented as the data is transferred and when it reaches zero, the transfer is complete and the TPU issues an interrupt request to the CPU. XFER_SIZE Parameter3, bits 0..4 This CPU written parameter determines the number of bits that make up a data transfer. During initialisation XFER_SIZE is copied into BIT_COUNT. XFER_SIZE is shown as a five bit parameter to match the maximum size of 16 bits in SIOP_DATA, although the TPU uses the whole word location. For normal use, XFER_SIZE should be in the range 1 to 16. SIOP_DATA Parameter4, bits 0..15 This parameter is the data register for all SIOP transfers. Data is shifted out of one end of SIOP_DATA and shifted in at the other end, the shift direction being determined by the value of BIT_D. In output only mode, zero will be shifted into SIOP_DATA and in input only mode, the data shifted out is ignored. In clock only mode SIOP_DATA is still shifted. Note that no 'justifying' of SIOP_DATA is performed by the TPU - e.g. if an 8 bit bi- directional transfer is made, shifting lsb first, then the bottom byte of SIOP_DATA will be shifted out and the input data will be shifted into the upper byte of SIOP_DATA. SIOP_DATA is not buffered: the CPU should only access it between completion of one transfer and the start of the next. HOST CPU INITIALISATION OF SIOP FUNCTION ------------------------------------------ The CPU initialises the SIOP function by the following means:- 1) Disabling the channel by clearing the two channel priority bits. 2) Selecting the SIOP function on the channel by writing the assigned SIOP function number to the function select bits. 3) Writing CHAN_CONTROL in the clock channel parameter RAM. 4) Writing HALF_PERIOD, BIT_D and XFER_SIZE in the clock channel parameter RAM to determine the speed, shift direction and size of the transfer. 5) Writing SIOP_DATA if the data output is to be used. 6) Selecting the required operating mode via the two host sequence bits. 7) Issuing a host service request type %11. 8) Enabling service by assigning H,M or L priority to the clock channel via the two channel priority bits. The TPU then starts the data transfer, and issues an interrupt request when the transfer is complete. Once the function has been initialised, the CPU only needs to write SIOP_DATA with the new data and issue a HSR %11 to initiate a new transfer. In input or clock only modes, just the HSR %11 is required. NOTES ON USE AND PERFORMANCE OF SIOP FUNCTION ---------------------------------------------- PERFORMANCE Like all TPU functions, the performance limit of the SIOP function in a given application is dependent to some extent on the service time (latency) associated with other active TPU channels. This is due to the operational nature of the scheduler. Where 2 channels are being used for a uni- directional system, and no other TPU channels are active, the maximum baud rate is approximately 230KHZ at a bus speed of 16.77MHz. A three channel bi- directional system under the same conditions has a maximum baud rate of approximately 200 KHz. When more TPU channels are active, these performance figures will be degraded. XFER_SIZE GREATER THAN 16 XFER_SIZE is normally programmed to be in the range 1 to 16 to match the size of SIOP_DATA, and has thus been described as a five bit value. However, the TPU actually uses all 16 bits of the XFER_SIZE parameter when loading BIT_COUNT. In some unusual circumstances this could be used to the users advantage:- if an input device is producing a data stream of greater than 16 bits then manipulation of XFER_SIZE will allow selective capturing of the data. In clock only mode, the extended XFER_SIZE can be used to generate up to $FFFF clocks. DATA POSITIONING As already mentioned, no 'justifying' of the data position in SIOP_DATA is performed by the TPU. This means that in the case of a byte transfer the data output will be sourced from one byte and the data input will shift into the other byte. This rule holds for all data size options except 16 bits when the full SIOP_DATA register is used for both data output and input. DATA TIMING Since the data channels are manipulated directly by microcode software while servicing the clock edge, there is a finite delay between the relevant clock edge and the data out being valid or the data in being latched. This delay is equivalent to the latency in servicing the clock channel due to other TPU activity(Td). Td is the delay between the clock edge and the next output data being valid and also the delay between the opposite clock edge and the input data being read. For the vast majority of applications, the delay Td will not present a problem and can be ignored. Only for a system which heavily loads the TPU should the user calculate the worst case latency for the SIOP clock channel + actual SIOP service time ( = Td) and ensure that the baud rate is chosen such that HALF_PERIOD - Td is not less that the minimum setup time of the receiving device. A transmitting device must also hold data valid for a minimum time of Td after the clock.