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(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : LRAUV_BATT-CONN_TEMPLATE.brd                  )
(    Software Version : 16.6S025                                      )
(    Date/Time        : Tue Mar 18 17:52:15 2014                      )
(                                                                     )
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------ Directives ------------

Ripup etch:                  No
Ripup delete first segment:  No
Ripup retain bondwire:       No
Ripup symbols:               Always
Missing symbol has error:    No
DRC update:                  Yes
Schematic directory:         '.'
Design Directory:            '.'
Old design name:             'J:/PCB_Layout/Open_Work_Space/10021057pA-BPC1/allegro/LRAUV_BATT-CONN_TEMPLATE.brd'
New design name:             'J:/PCB_Layout/Open_Work_Space/10021057pA-BPC1/allegro/LRAUV_BATT-CONN_TEMPLATE.brd'

CmdLine: netrev -$ -i . -y 1 -q netrev_constraint_report.xml J:/PCB_Layout/Open_Work_Space/10021057pA-BPC1/allegro/#Taaaaaj07228.tmp

------ Preparing to read pst files ------

Starting to read ./pstchip.dat 
   Finished reading ./pstchip.dat (00:00:00.05)
Starting to read ./pstxprt.dat 
   Finished reading ./pstxprt.dat (00:00:00.00)
Starting to read ./pstxnet.dat 
   Finished reading ./pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------


#1   WARNING(SPMHNI-192): Device/Symbol check warning detected. [help]

ERROR(SPMHNI-196): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' has extra pin 'B1'.

ERROR(SPMHNI-196): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' has extra pin 'B2'.

ERROR(SPMHNI-196): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' has extra pin 'B3'.

ERROR(SPMHNI-196): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' has extra pin 'B4'.

ERROR(SPMHNI-196): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' has extra pin 'B5'.

ERROR(SPMHNI-195): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' is missing pin 'A10'.

ERROR(SPMHNI-195): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' is missing pin 'A6'.

ERROR(SPMHNI-195): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' is missing pin 'A7'.

ERROR(SPMHNI-195): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' is missing pin 'A8'.

ERROR(SPMHNI-195): Symbol 'TE_5787446' for device 'CON5X2_SYM-MOD1_TE_5787446_IO_5' is missing pin 'A9'.

------ Library Paths ------
MODULEPATH =  . 
           C:/Cadence/SPB_16.6/share/local/pcb/modules 

PSMPATH =  . 
           //WATER/Allegro_Library/Symbols 
           //WATER/Allegro_Library/FORMAT 
           //WATER/Allegro_Library/Pads 

PADPATH =  . 
           //WATER/Allegro_Library/Pads 
           J:/PCB_Layout/Layout_Libraries/LIBRARIES/CNC_PAD-LIBRARY/ 


------ Summary Statistics ------


netrev run on Mar 18 17:52:15 2014
   DESIGN NAME : '10021057-BPC1'
   PACKAGING ON Jan 13 2014 18:46:08

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

 No error detected
 No oversight detected
  1 warnings detected

cpu time      0:00:58
elapsed time  0:00:00