(ExpressProject "BURNWIRE_DC-DC"
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  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\burnwire_dc-dc.dsn"
      (Type "Schematic Design"))
    (Netlist_TAB "0"))
  (Folder "Outputs"
    (File ".\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\allegro\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat")))
  (Folder "Referenced Projects")
  (MPSSessionName "jrosal")
  (PartMRUSelector)
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources"
         "J:\PCB_Layout\Open_Work_Space\BURNWIRE_DC-DC\burnwire_dc-dc.dsn")
      (Path "Design Resources"
         "J:\PCB_Layout\Open_Work_Space\BURNWIRE_DC-DC\burnwire_dc-dc.dsn"
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      (Path "Outputs")
      (Select "Design Resources"
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    (HierarchyView)
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      (Tab 0))
    (Doc
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        (Placement "44 0 1 -1 -1 -8 -30 225 2338 225 1094")
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      (Path "J:\PCB_LAYOUT\OPEN_WORK_SPACE\BURNWIRE_DC-DC\BURNWIRE_DC-DC.DSN")
      (Schematic "SCHEMATIC1")
      (Page "PAGE1")))
  (ISPCBBASICLICENSE "false"))