(---------------------------------------------------------------------) ( ) ( Allegro Netrev Import Logic ) ( ) ( Drawing : GENE.brd ) ( Software Version : 16.6S021 ) ( Date/Time : Tue Feb 11 13:36:35 2014 ) ( ) (---------------------------------------------------------------------) ------ Directives ------ RIPUP_ETCH FALSE; RIPUP_DELETE_FIRST_SEGMENT FALSE; RIPUP_RETAIN_BONDWIRE FALSE; RIPUP_SYMBOLS ALWAYS; Missing symbol has error FALSE; SCHEMATIC_DIRECTORY '.'; BOARD_DIRECTORY ''; OLD_BOARD_NAME 'J:/PCB_Layout/Open_Work_Space/GENE/allegro/GENE.brd'; NEW_BOARD_NAME 'J:/PCB_Layout/Open_Work_Space/GENE/allegro/GENE.brd'; CmdLine: netrev -$ -i . -y 1 -q netrev_constraint_report.xml J:/PCB_Layout/Open_Work_Space/GENE/allegro/#Taaaaaf12728.tmp ------ Preparing to read pst files ------ Starting to read ./pstchip.dat Finished reading ./pstchip.dat (00:00:00.05) Starting to read ./pstxprt.dat Finished reading ./pstxprt.dat (00:00:00.00) Starting to read ./pstxnet.dat Finished reading ./pstxnet.dat (00:00:00.00) ------ Oversights/Warnings/Errors ------ ------ Library Paths ------ MODULEPATH = . C:/Cadence/SPB_16.6/share/local/pcb/modules PSMPATH = . //WATER/Allegro_Library/Symbols //WATER/Allegro_Library/FORMAT //WATER/Allegro_Library/Pads PADPATH = . //WATER/Allegro_Library/Pads J:/PCB_Layout/Layout_Libraries/LIBRARIES/CNC_PAD-LIBRARY/ ------ Summary Statistics ------ netrev run on Feb 11 13:36:35 2014 DESIGN NAME : 'GENE_OP-AMP' PACKAGING ON Oct 28 2013 13:12:55 COMPILE 'logic' CHECK_PIN_NAMES OFF CROSS_REFERENCE OFF FEEDBACK OFF INCREMENTAL OFF INTERFACE_TYPE PHYSICAL MAX_ERRORS 500 MERGE_MINIMUM 5 NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|' NET_NAME_LENGTH 24 OVERSIGHTS ON REPLACE_CHECK OFF SINGLE_NODE_NETS ON SPLIT_MINIMUM 0 SUPPRESS 20 WARNINGS ON No error detected No oversight detected No warning detected cpu time 0:01:21 elapsed time 0:00:01