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( Allegro Netrev Import Logic )
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( Drawing : GENE_12TS.brd )
( Software Version : 16.6S042 )
( Date/Time : Mon Feb 02 11:54:10 2015 )
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------ Directives ------------
Ripup etch: No
Ripup delete first segment: No
Ripup retain bondwire: No
Ripup symbols: Always
Missing symbol has error: No
DRC update: Yes
Schematic directory: 'X:/TechServices/PCB_Layout/Open_Work_Space/10020900_ESP_DWSM_VOLTAGE_ATTENUATOR/allegro'
Design Directory: '.'
Old design name: 'J:/PCB_Layout/Open_Work_Space/GENE_12TS/allegro/GENE_12TS.brd'
New design name: 'J:/PCB_Layout/Open_Work_Space/GENE_12TS/allegro/GENE_12TS.brd'
CmdLine: netrev -$ -i X:/TechServices/PCB_Layout/Open_Work_Space/10020900_ESP_DWSM_VOLTAGE_ATTENUATOR/allegro -y 1 -q netrev_constraint_report.xml J:/PCB_Layout/Open_Work_Space/GENE_12TS/allegro/#Taaaaae10664.tmp
------ Preparing to read pst files ------
#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Feb 2 11:54:10 2015
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:28
elapsed time 0:00:00