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|                                 ECO   REPORT                                 |
|                                                                    Page   1  |
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|  J:/PCB_Layout/Open_Work_Space/GENE_AD-PROTO/allegro/Size_B_2LAYERS.brd      |
|                                                    Mon Apr 21 11:09:25 2014  |
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| NET CHANGES                                                                  |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
|   net  name |  type of change |    pin_id     |   x   |   y   |   to  net    |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
  GND_SIGNAL   pins ADDED TO this existing net (pins not previously on any net)
                                 TP1.1                          
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|                                 ECO   REPORT                                 |
|                                                                    Page   2  |
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|  J:/PCB_Layout/Open_Work_Space/GENE_AD-PROTO/allegro/Size_B_2LAYERS.brd      |
|                                                    Mon Apr 21 11:09:25 2014  |
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| COMPONENT DEFINITION added to design                                         |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
|    device type                                                               |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
 TESTPOINT_TP_KEYSTONE_5000S_COM
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|                                 ECO   REPORT                                 |
|                                                                    Page   3  |
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|  J:/PCB_Layout/Open_Work_Space/GENE_AD-PROTO/allegro/Size_B_2LAYERS.brd      |
|                                                    Mon Apr 21 11:09:25 2014  |
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| COMPONENTS ADDED to design                                                   |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
|    ref des        |    device type                                           |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
 TP1                 TESTPOINT_TP_KEYSTONE_5000S_COM 
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|                                 ECO   REPORT                                 |
|                                                                    Page   4  |
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|  J:/PCB_Layout/Open_Work_Space/GENE_AD-PROTO/allegro/Size_B_2LAYERS.brd      |
|                                                    Mon Apr 21 11:09:25 2014  |
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| SLOT PROPERTIES added to design                                              |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
|   slot_id    |   x   |   y   |   property   |             value              |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
 TP1.1                          PRIM_FILE      .\pstchip.dat
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|   total ECO changes reported  4                                              |
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