\t (00:00:06) allegro 16.5 S014 (v16-5-13AJ) i86
\t (00:00:06)     Journal start - Wed Feb 01 08:31:05 2012
\t (00:00:06)         Host=QUEEN-ELIZABETH User=jrosal Pid=4104 CPUs=2
\t (00:00:06) 
\t (00:00:07) Opening existing design...
\d (00:00:07) Database opened: J:/PCB_Layout/Open_Work_Space/PB_PID_Wayne/allegro/PB_WAYNE_PID.brd
\i (00:00:07) trapsize 63
\i (00:00:08) trapsize 64
\i (00:00:08) trapsize 64
\i (00:00:09) generaledit 
\i (00:00:11) cmgr 
\i (00:00:11) setwindow cmgr
\i (00:00:11) cm newView ( worksheet 78:Spacing "79:Spacing Constraint Set" "80:All Layers" 84:Shape )
\i (00:00:13) cm newView ( worksheet "171:Same Net Spacing" "172:Same Net Spacing Constraint Set" "173:All Layers" 177:Shape )
\i (00:00:14) cm fetch SN_LINE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_LINE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_THRUPIN_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_THRUPIN_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_SHAPE_TO_SMDPIN_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_SHAPE_TO_SMDPIN_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_SHAPE_TO_TESTPIN_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_SHAPE_TO_TESTPIN_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_SHAPE_TO_THRUVIA_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_SHAPE_TO_THRUVIA_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_BBV_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_BBV_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_SHAPE_TO_TESTVIA_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_SHAPE_TO_TESTVIA_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_SHAPE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_SHAPE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_BONDPAD_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_BONDPAD_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm fetch SN_HOLE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:14) cm fetch SN_HOLE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Same Net Spacing CSet"
\i (00:00:14) cm endUndoBlock
\i (00:00:14) cm fetch DRC_IS_UPTODATE ( System "System" ) System
\i (00:00:14) cm fetch ONLINE_DRC ( System "System" ) System
\i (00:00:14) setwindow pcb
\i (00:00:14) generaledit 
\i (00:00:19) setwindow cmgr
\i (00:00:19) cm select ( worksheet "171:Same Net Spacing" "172:Same Net Spacing Constraint Set" "173:All Layers" 177:Shape )
\i (00:00:19) cm select ( worksheet "171:Same Net Spacing" "172:Same Net Spacing Constraint Set" "173:All Layers" 177:Shape )
\i (00:00:19) cm select ( worksheet "171:Same Net Spacing" "172:Same Net Spacing Constraint Set" "173:All Layers" 177:Shape )
\i (00:00:19) cm select ( worksheet "171:Same Net Spacing" "172:Same Net Spacing Constraint Set" "173:All Layers" 177:Shape )
\i (00:00:21) cm fetch LINE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch LINE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch THRUPIN_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch THRUPIN_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch SHAPE_TO_SMDPIN_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch SHAPE_TO_SMDPIN_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch SHAPE_TO_TESTPIN_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch SHAPE_TO_TESTPIN_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch SHAPE_TO_THRUVIA_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch SHAPE_TO_THRUVIA_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch BBV_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch BBV_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch SHAPE_TO_TESTVIA_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch SHAPE_TO_TESTVIA_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch SHAPE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch SHAPE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch BONDPAD_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch BONDPAD_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm fetch HOLE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) Design
\i (00:00:21) cm fetch HOLE_TO_SHAPE_SPACING ( Design "PB_WAYNE_PID" ) "Spacing CSet"
\i (00:00:21) cm select ( frame ( workbook 78:Spacing "79:Spacing Constraint Set" "80:All Layers" ) )
\i (00:00:26) cm exit
\i (00:00:33) setwindow pcb
\i (00:00:33) open 
\e (00:00:33) Do you want to save the changes you made to PB_WAYNE_PID.brd?
\i (00:00:35) fillin no 
\i (00:00:47) fillin "J:\PCB_Layout\Open_Work_Space\PB_PWM-FILTER_WAYNE\allegro\PB_PWB-FILTER.brd"
\i (00:00:47) cd "J:\PCB_Layout\Open_Work_Space\PB_PWM-FILTER_WAYNE\allegro"
\t (00:00:47) Opening existing design...
\i (00:00:47) trapsize 103
\t (00:00:48)     Journal end - Wed Feb 01 08:31:47 2012