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    (File ".\tethys_motherboard_rev1.dsn"
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    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (BOM_Scope "0")
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    (BOM_Report_File "C:\0_Work_Space\Tethys_Motherboard\JOSE_BOM_novalue.xls")
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       "{Item}\t{Quantity}\t{Reference}\t{Manufacturer}\t{Manuf PN}\t{Package}\t{Supplier}\t{Supplier PN}\t{Description}\t{PCB Footprint}")
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    (BOM_Include_File
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    (NoModify)
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    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
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    (DRC_Visible_Power_pins "FALSE")
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    (DRC_View_Output "FALSE")
    (DRC_Report_File
       "C:\PROJECTS\LR AUV\TETHYS\SCHEMATICS\TETHYS MOTHERBOARD COPY OCT09 .DRC")
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    ("Create Allegro Netlist" "TRUE")
    ("Allegro Netlist Directory" "ALLEGRO")
    ("View Allegro Netlist Files" "FALSE")
    ("Update Allegro Board" "FALSE")
    ("Allegro Netlist Output Board File"
       "allegro\tethys motherboard copy oct09 .brd")
    ("Allegro Netlist Remove Etch" "FALSE")
    ("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
    ("Allegro Netlist Open Board in Allegro" "ALLEGRO")
    ("Allegro Setup Configuration File"
       "C:\Cadence\SPB_16.01\tools\capture\allegro.cfg")
    ("Allegro Setup Backup Versions" "3")
    ("Allegro Netlist Combine Property String" "PCB Footprint")
    ("Allegro Netlist Ignore Fixed Property" "FALSE")
    ("Allegro Netlist User Defined Property" "FALSE")
    (Board_sim_option "VHDL_flow"))
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    (File "..\tethys motherboard copy oct09 .bom"
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    (File "..\jose_bom_novalue.xls"
      (Type "Report"))
    (File "..\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File "..\allegro\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File "..\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat"))
    (File ".\allegro\pstxnet.dat"
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      (DisplayName "pstxnet.dat"))
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    (File ".\allegro\pstchip.dat"
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