(ExpressProject "10020690rA_ROV1k-WHISTLE-ADAPTER"
  (ProjectVersion "19981106")
  (SoftwareVersion "23.1 S008 (4266294)  [1/8/2025]-[01/31/13]")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library"
      (File ".\10020690_rov1k-whistle-adapter_sch-lib.olb"
        (Type "Schematic Library")))
    (NoModify)
    (File ".\10020690ra_rov1k-whistle-adapter.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (Netlist_TAB "0")
    (Board_sim_option "VHDL_flow")
    (DOCKED "TRUE")
    (DOCKING_POSITION "59420"))
  (Folder "Layout")
  (Folder "Outputs"
    (File ".\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\allegro\pstxprt.dat"
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      (DisplayName "pstxprt.dat"))
    (File ".\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat")))
  (Folder "Referenced Projects")
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      (FullPartName "CAP.Normal")
      (LibraryName "\\WATER\SCHEMATIC_SYMBOLS\CAPACITORS.OLB")
      (DeviceIndex "0"))
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      (DeviceIndex "0")))
  (GlobalState
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      (Path "Design Resources"
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      (Path "Design Resources"
         "X:\TechServices\PCB_Layout\Completed\10020690rA-1_ROV1k-WHISTLE-ADAPTER\10020690ra_rov1k-whistle-adapter.dsn"
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      (Path "Design Resources" "Library")
      (Path "Outputs")
      (Select "Design Resources"
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    (HierarchyView)
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      (Frame
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      (Tab 0))
    (Doc
      (Type "COrSchematicDoc")
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        (Scroll "85 504")
        (Zoom "160")
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      (Path
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      (Page "PAGE1")))
  (ISPCBBASICLICENSE "false")
  (MPSSessionName "cbeebe")
  (Folder "PSpice Resources"
    (Folder "Simulation Profiles")
    (Folder "Model Libraries"
      (Sort User))
    (Folder "Stimulus Files"
      (Sort User))
    (Folder "Include Files"
      (Sort User)))
  (Folder "Logs"))