(ExpressProject ""
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (File ".\cf2_cntl.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (NoModify)
    (BOM_Scope "0")
    (BOM_Mode "0")
    (BOM_Report_File
       "J:\PCB_LAYOUT\OPEN_WORK_SPACE\10021035_ISUS-DURA-CF2_CONTROLLER_REVA\10021035rA_BOM.xls")
    (BOM_Merge_Include "FALSE")
    (BOM_Property_Combine_7.0
       "{Item}\t{Quantity}\t{Reference}\t{Value}\t{Description}\t{MANUFACTURER}\t{NUMBER}\t{PACKAGE}\t{RATING}\t{TOLERANCE}")
    (BOM_Header
       "Item\tQuantity\tReference\tPart\tDescription\tManufacturer\tManufacturer_PN\tPackage\tRating\tTolerance")
    (BOM_Include_File
       "J:\PCB_LAYOUT\OPEN_WORK_SPACE\10021035_ISUS-DURA-CF2_CONTROLLER_REVA\CF2_CNTL.INC")
    (BOM_Include_File_Combine_7.0 "{Item}\t{Quantity}\t{Reference}\t{Value}")
    (BOM_One_Part_Per_Line "FALSE")
    (Open_BOM_in_Excel "FALSE")
    (BOM_View_Output "TRUE")
    (Netlist_TAB "0")
    (DRC_Scope "0")
    (DRC_Action "0")
    (DRC_Create_Warnings "FALSE")
    (DRC_View_Output "FALSE")
    (DRC_Preserved_Waived "FALSE")
    (DRC_Run_Electrical_Rules "TRUE")
    (DRC_Run_Physical_Rules "FALSE")
    (DRC_Report_File
       "J:\PCB_LAYOUT\OPEN_WORK_SPACE\10021035_ISUS-DURA-CF2_CONTROLLER_REVA\CF2_CNTL.DRC")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Report_Netnames "FALSE")
    (DRC_Check_Single_Node_Nets "TRUE")
    (DRC_Run_Electrical_Custom_DRC "FALSE")
    (DRC_Check_No_Driving_Source "TRUE")
    (DRC_Check_Duplicate_NetNames "TRUE")
    (DRC_Check_Floating_Pins "TRUE")
    (DRC_Check_Physical_Power_Pins_Visibility "TRUE")
    (DRC_Check_PCB_Footprint_Property "TRUE")
    (DRC_Check_Normal_Convert_View_Sync "TRUE")
    (DRC_Check_Incorrect_PinGroup_Assignment "TRUE")
    (DRC_Check_High_Speed_Props_Syntax "TRUE")
    (DRC_Check_Missing_Pin_Numbers "TRUE")
    (DRC_Check_Device_With_No_Pins "TRUE")
    (DRC_Check_Power_Ground_Short "TRUE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Visible_Power_pins "FALSE")
    (DRC_Report_Unused_Part_Packages "TRUE")
    (DRC_Check_Name_Prop_For_HierBlocks "TRUE")
    (DRC_Run_Physical_Custom_DRC "FALSE"))
  (Folder "Outputs"
    (File ".\cf2_cntl.xls"
      (Type "Report"))
    (File ".\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\allegro\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat"))
    (File ".\cf2_cntl.drc"
      (Type "Report"))
    (File ".\10021035ra_bom.xls"
      (Type "Report")))
  (Folder "Referenced Projects")
  (PartMRUSelector
    (BATTERY_2P-1N
      (FullPartName "BATTERY_2P-1N.Normal")
      (LibraryName "\\WATER\SCHEMATIC_SYMBOLS\MISC.OLB")
      (DeviceIndex "0")))
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources" ".\cf2_cntl.dsn")
      (Path "Outputs")
      (Select "Design Resources" ".\cf2_cntl.dsn"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -8 -30 0 1112 0 618"))
      (Tab 0))
    (Doc
      (Type "COrSchematicDoc")
      (Frame
        (Placement "44 2 3 -1 -1 -8 -30 50 855 50 762")
        (Scroll "1375 952")
        (Zoom "100")
        (Occurrence "/POWER SUPPLIES"))
      (Path
         "J:\PCB_LAYOUT\COMPLETED\10021035_ISUS-DURA-CF2_CONTROLLER_REVA\CF2_CNTL.DSN")
      (Schematic "CF2_PWR")
      (Page "CF2_PWR.SCH")))
  (ISPCBBASICLICENSE "false")
  (MPSSessionName "jrosal"))