(---------------------------------------------------------------------)
(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : 10021035rB_ISUS-DURA-CF2_Controller.brd       )
(    Software Version : 16.6S042                                      )
(    Date/Time        : Mon Mar 09 11:27:30 2015                      )
(                                                                     )
(---------------------------------------------------------------------)


------ Directives ------------

Ripup etch:                  No
Ripup delete first segment:  No
Ripup retain bondwire:       No
Ripup symbols:               Always
Missing symbol has error:    No
DRC update:                  Yes
Schematic directory:         '.'
Design Directory:            '.'
Old design name:             'J:/PCB_Layout/Open_Work_Space/10021035rB_ISUS-DURA-CF2_Controller_RevB/allegro/10021035rB_ISUS-DURA-CF2_Controller.brd'
New design name:             'J:/PCB_Layout/Open_Work_Space/10021035rB_ISUS-DURA-CF2_Controller_RevB/allegro/10021035rB_ISUS-DURA-CF2_Controller.brd'

CmdLine: netrev -$ -i . -y 1 -q netrev_constraint_report.xml J:/PCB_Layout/Open_Work_Space/10021035rB_ISUS-DURA-CF2_Controller_RevB/allegro/#Taaaaab12864.tmp

------ Preparing to read pst files ------

Starting to read ./pstchip.dat 
   Finished reading ./pstchip.dat (00:00:00.11)
Starting to read ./pstxprt.dat 
   Finished reading ./pstxprt.dat (00:00:00.01)
Starting to read ./pstxnet.dat 
   Finished reading ./pstxnet.dat (00:00:00.02)

------ Oversights/Warnings/Errors ------


------ Library Paths ------
MODULEPATH =  . 
           C:/Cadence/SPB_16.6/share/local/pcb/modules 

PSMPATH =  . 
           //WATER/Allegro_Library/Symbols 
           //WATER/Allegro_Library/FORMAT 
           //WATER/Allegro_Library/Pads 
           J:/PCB_Layout/Layout_Libraries/LIBRARIES/SYMBOLS_2009 

PADPATH =  . 
           //WATER/Allegro_Library/Pads 
           J:/PCB_Layout/Layout_Libraries/LIBRARIES/CNC_PAD-LIBRARY/ 
           J:/PCB_Layout/Layout_Libraries/LIBRARIES/PADSTACKS_2009 


------ Summary Statistics ------


netrev run on Mar 9 11:27:30 2015
   DESIGN NAME : 'CF2_CNTL'
   PACKAGING ON Oct 15 2014 05:53:32

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

 No error detected
 No oversight detected
 No warning detected

cpu time      0:01:48
elapsed time  0:00:00