\t (00:00:31) allegro 16.6-2015 S069 (v16-6-112FP) Windows 32
\t (00:00:31)     Journal start - Wed Jun 08 11:28:23 2016
\t (00:00:31)         Host=PACMAN User=jrosal Pid=17536 CPUs=24
\t (00:00:31) CmdLine= C:\Cadence\SPB_16.6\tools\pcb\bin\allegro.exe
\t (00:00:31) 
\d (00:00:31) Design opened: J:/PCB_Layout/Open_Work_Space/hostegate/allegro/ARCHIVE/ESP_HostGate.brd
\i (00:00:31) etchedit 
\i (00:00:41) open 
\i (00:01:26) fillin "J:\PCB_Layout\Open_Work_Space\hostegate\allegro\ESP_G3HostGate.brd"
\i (00:01:26) cd "J:\PCB_Layout\Open_Work_Space\hostegate\allegro"
\t (00:01:27) Opening existing design...
\w (00:01:27) WARNING(SPMHDB-212): This design has functionality disabled due to the current product plus options selected. The following features are disabled: Via Z.  [help]
\i (00:01:28) fillin confirm
\i (00:01:28) trapsize 565
\t (00:01:28)     Journal end - Wed Jun 08 11:29:20 2016