|------------------------------------------------------------------------------| | ECO REPORT | | Page 1 | |------------------------------------------------------------------------------| | J:/PCB_Layout/Open_Work_Space/DFrench_DC-DC/allegro/DFRENCH_DC-DC.brd | | Mon Feb 29 17:21:20 2016 | |------------------------------------------------------------------------------| | NET CHANGES | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | | net name | type of change | pin_id | x | y | to net | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | 12V pins ADDED TO this existing net (pins not previously on any net) MOD3.2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GND_SIGNAL pins ADDED TO this existing net (pins not previously on any net) J5.3 1400.0 1125.0 J5.4 1400.0 1225.0 MOD2.K1 MOD2.K2 MOD3.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N15228154 pins ADDED TO this existing net (pins not previously on any net) MOD2.6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N15564006 pins ADDED TO this new net J6.3 J6.4 MOD2.1 MOD3.3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N15564013 pins ADDED TO this new net MOD2.2 MOD2.3 MOD3.4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N15564064 pins ADDED TO this new net J6.1 MOD2.4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N15564068 pins ADDED TO this new net J6.2 MOD2.5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N15564341 pins ADDED TO this new net J5.1 1400.0 925.0 MOD2.7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N15564356 pins ADDED TO this new net J5.2 1400.0 1025.0 MOD2.8 |------------------------------------------------------------------------------| | ECO REPORT | | Page 2 | |------------------------------------------------------------------------------| | J:/PCB_Layout/Open_Work_Space/DFrench_DC-DC/allegro/DFRENCH_DC-DC.brd | | Mon Feb 29 17:21:20 2016 | |------------------------------------------------------------------------------| | COMPONENT DEFINITION added to design | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | | device type | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | XPORT DS_LANTRONIX_XP1001000-04 XPPOWER_IE_SIP_XPPOWER_IE_SIP_D |------------------------------------------------------------------------------| | ECO REPORT | | Page 3 | |------------------------------------------------------------------------------| | J:/PCB_Layout/Open_Work_Space/DFrench_DC-DC/allegro/DFRENCH_DC-DC.brd | | Mon Feb 29 17:21:20 2016 | |------------------------------------------------------------------------------| | COMPONENTS ADDED to design | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | | ref des | device type | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | J6 CON4_PHOENIX_1725672_IO_1725672 MOD2 XPORT DS_LANTRONIX_XP1001000-04 MOD3 XPPOWER_IE_SIP_XPPOWER_IE_SIP_D |------------------------------------------------------------------------------| | ECO REPORT | | Page 4 | |------------------------------------------------------------------------------| | J:/PCB_Layout/Open_Work_Space/DFrench_DC-DC/allegro/DFRENCH_DC-DC.brd | | Mon Feb 29 17:21:20 2016 | |------------------------------------------------------------------------------| | COMPONENTS CHANGED from one device type to another in design | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | | ref des | new device type | x | y | old device type | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | J5 CON4_PHOENIX_1725672_IO_1725672 1400.0 1075.0 CON2_PHOENIX_1725656_IO_1725656 |------------------------------------------------------------------------------| | ECO REPORT | | Page 5 | |------------------------------------------------------------------------------| | J:/PCB_Layout/Open_Work_Space/DFrench_DC-DC/allegro/DFRENCH_DC-DC.brd | | Mon Feb 29 17:21:20 2016 | |------------------------------------------------------------------------------| | SLOT PROPERTIES added to design | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | | slot_id | x | y | property | value | |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | J5.4 1400.0 1075.0 PRIM_FILE .\pstchip.dat J6.4 PRIM_FILE .\pstchip.dat MOD2.2 PRIM_FILE .\pstchip.dat MOD3.3 PRIM_FILE .\pstchip.dat |------------------------------------------------------------------------------| | Nets changed : 22 | | Comp definitions added: 2 | | Components added : 3 | | Components changed : 1 | | Slot property added : 4 | | | | Total ECO changes reported: 32 | |------------------------------------------------------------------------------|