\t (00:00:02) allegro 16.6-2015 S069 (v16-6-112FP) Windows 32
\t (00:00:02)     Journal start - Wed Jun 22 13:57:03 2016
\t (00:00:02)         Host=PACMAN User=jrosal Pid=11968 CPUs=24
\t (00:00:02) CmdLine= C:\Cadence\SPB_16.6\tools\pcb\bin\allegro.exe
\t (00:00:02) 
\t (00:00:03) Opening existing design...
\d (00:00:03) Design opened: J:/PCB_Layout/Open_Work_Space/CambridgeIC Blue prints/100221141rA_ESP_CambridgeIC.brd
\i (00:00:03) trapsize 43144
\i (00:00:03) trapsize 42584
\i (00:00:03) trapsize 43239
\i (00:00:04) trapsize 43239
\i (00:00:04) placementedit 
\i (00:45:54) exit 
\t (00:45:55)     Journal end - Wed Jun 22 14:42:57 2016