\t (00:30:36) allegro 17.2 S005 Windows SPB 64-bit Edition
\t (00:30:36)     Journal start - Tue Oct 04 14:08:11 2016
\t (00:30:36)         Host=PACMAN User=jrosal Pid=17112 CPUs=24
\t (00:30:36) CmdLine= c:\cadence\spb_17.2\tools\bin\allegro.exe J:\PCB_Layout\Open_Work_Space\ESP_ElfCamT6\allegro\ESP+ElfCamT6.brd
\t (00:30:36) 
\d (00:30:36) Design opened: J:/PCB_Layout/Open_Work_Space/100221147 rA_PB_STR8interface/allegro/100221147 rA_PB_STR8interface.brd
\i (00:30:36) generaledit 
\i (00:31:06) open 
\i (00:31:09) fillin "PB_STR8interface.brd"
\t (00:31:09) Opening existing design...
\i (00:31:10) fillin yes 
\w (00:31:11) WARNING(SPMHDB-213): DRC set to "out of date". The current product selection supports a different DRC capability than what is saved in the design.
\i (00:31:11) trapsize 113
\d (00:31:11) Design opened: J:/PCB_Layout/Open_Work_Space/100221147 rA_PB_STR8interface/allegro/PB_STR8interface.brd
\i (00:31:11) generaledit 
\i (00:31:18) opencd J:/PCB_Layout/Open_Work_Space/ESP_ElfCamT6/allegro/ESP+ElfCamT6.brd 
\t (00:31:18) Opening existing design...
\i (00:31:19) fillin yes 
\w (00:31:19)  Design outline not created.
\w (00:31:19) WARNING(SPMHDB-213): DRC set to "out of date". The current product selection supports a different DRC capability than what is saved in the design.
\i (00:31:19) trapsize 398
\t (00:31:19)     Journal end - Tue Oct 04 14:08:54 2016