(---------------------------------------------------------------------)
(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : 11021164rA_LRAUV-LONGBACKPLANE.brd            )
(    Software Version : 16.6-2015S053                                 )
(    Date/Time        : Thu Jul 30 12:56:28 2015                      )
(                                                                     )
(---------------------------------------------------------------------)


------ Directives ------------

Ripup etch:                  No
Ripup delete first segment:  No
Ripup retain bondwire:       No
Ripup symbols:               Always
Missing symbol has error:    No
DRC update:                  Yes
Schematic directory:         '.'
Design Directory:            '.'
Old design name:             'J:/PCB_Layout/Open_Work_Space/BackplaneLong2013/Schematic/allegro/11021164rA_LRAUV-LONGBACKPLANE.brd'
New design name:             'J:/PCB_Layout/Open_Work_Space/BackplaneLong2013/Schematic/allegro/11021164rA_LRAUV-LONGBACKPLANE.brd'

CmdLine: netrev -$ -i . -y 1 -q netrev_constraint_report.xml J:/PCB_Layout/Open_Work_Space/BackplaneLong2013/Schematic/allegro/#Taaaabf10632.tmp

------ Preparing to read pst files ------

Starting to read ./pstchip.dat 
   Finished reading ./pstchip.dat (00:00:00.04)
Starting to read ./pstxprt.dat 
   Finished reading ./pstxprt.dat (00:00:00.01)
Starting to read ./pstxnet.dat 
   Finished reading ./pstxnet.dat (00:00:00.01)

------ Oversights/Warnings/Errors ------


#1   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST9 component device pin number mismatch; cannot replace.

#2   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST8 component device pin number mismatch; cannot replace.

#3   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST7 component device pin number mismatch; cannot replace.

#4   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST6 component device pin number mismatch; cannot replace.

#5   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST5 component device pin number mismatch; cannot replace.

#6   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST4 component device pin number mismatch; cannot replace.

#7   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST3 component device pin number mismatch; cannot replace.

#8   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST2 component device pin number mismatch; cannot replace.

#9   WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST14 component device pin number mismatch; cannot replace.

#10  WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST13 component device pin number mismatch; cannot replace.

#11  WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST12 component device pin number mismatch; cannot replace.

#12  WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST11 component device pin number mismatch; cannot replace.

#13  WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST10 component device pin number mismatch; cannot replace.

#14  WARNING(SPMHNI-184): Device library warning detected.

WARNING: ST1 component device pin number mismatch; cannot replace.

#1   ERROR(SPMHNI-191): Device/Symbol check error detected.

ERROR(SPMHNI-195): Symbol 'MNT_C220H125' for device 'SCREW-TERMINAL_MNT_C220H125_DIS' is missing pin '1'.

------ Library Paths ------
MODULEPATH =  . 
           C:/Cadence/SPB_16.6/share/local/pcb/modules 

PSMPATH =  . 
           //WATER/Allegro_Library/Symbols 
           //WATER/Allegro_Library/FORMAT 
           //WATER/Allegro_Library/Pads 

PADPATH =  . 
           //WATER/Allegro_Library/Pads 
           J:/PCB_Layout/Layout_Libraries/LIBRARIES/CNC_PAD-LIBRARY/ 


------ Summary Statistics ------


#2   Run stopped because errors were detected

netrev run on Jul 30 12:56:28 2015
   DESIGN NAME : '11021164 LOAD CONTROL LONG BACKPLANE'
   PACKAGING ON Jun  8 2015 17:42:25

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

  2 errors detected
 No oversight detected
 14 warnings detected

cpu time      0:01:19
elapsed time  0:00:00