(---------------------------------------------------------------------)
(                                                                     )
(    Netrev Allegro Import Logic                                      )
(                                                                     )
(    Drawing          : LV_LOAD_SWITCHER_PROTO.brd                    )
(    Software Version : 16.3p004                                      )
(    Date/Time        : Wed May 04 09:38:04 2011                      )
(                                                                     )
(---------------------------------------------------------------------)


------ Directives ------

RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY '.';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'X:/TechServices/PCB_Layout/Open_Work_Space/LV_LOAD_SWITCHER_PROTO/Allegro/LV_LOAD_SWITCHER_PROTO.brd';
NEW_BOARD_NAME 'X:/TechServices/PCB_Layout/Open_Work_Space/LV_LOAD_SWITCHER_PROTO/Allegro/LV_LOAD_SWITCHER_PROTO.brd';

CmdLine: netrev -$ -i . -y 1 X:/TechServices/PCB_Layout/Open_Work_Space/LV_LOAD_SWITCHER_PROTO/Allegro/#Taaaaaa03396.tmp

------ Preparing to read pst files ------

Starting to read ./pstchip.dat 
   Finished reading ./pstchip.dat (00:00:00.17)
Starting to read ./pstxprt.dat 
   Finished reading ./pstxprt.dat (00:00:00.01)
Starting to read ./pstxnet.dat 
   Finished reading ./pstxnet.dat (00:00:00.04)

------ Oversights/Warnings/Errors ------


------ Library Paths ------
MODULEPATH =  . 
           C:/Cadence/SPB_16.3/share/local/pcb/modules 

PSMPATH =  \\Water\Allegro_Library\Symbols 
           . 
           . 
           symbols 
           .. 
           ../symbols 

PADPATH =  \\Water\Allegro_Library\Pads 
           . 
           . 
           symbols 
           .. 
           ../symbols 
           C:/Cadence/SPB_16.3/share/pcb/allegrolib/symbols 


------ Summary Statistics ------


netrev run on May 4 9:38:04 2011
   DESIGN NAME : 'LV LOAD SWITCHER PROTO V2'
   PACKAGING ON Mar 14 2011 20:40:40

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

 No error detected
 No oversight detected
 No warning detected

cpu time      0:10:51
elapsed time  0:00:06