\t (00:00:02) allegro 17.4 S023 Windows SPB 64-bit Edition
\t (00:00:02)     Journal start - Fri Jul 22 13:47:08 2022
\t (00:00:02)         Host=PERISCOPE User=tanner Pid=19020 CPUs=16
\t (00:00:02) CmdLine= c:\cadence\spb_17.4\tools\bin\allegro.exe \\atlas\ProjectLibrary\TechServices\PCB_Layout\Layout_Libraries\Board_Templates\Size_B_2LAYERS_CNC.brd
\t (00:00:02) 
   (00:00:02) Loading axlcore.cxt 
\t (00:00:02) Loading "C:/SPB_Data/cdssetup/OrCAD_Capture/17.4.0/tclscripts/capAutoLoad/EDMClient/EDM/ClientAdapter/Skill/edm.csj"
\t (00:00:02) Log will be written to C:\Users\tanner\AppData\Roaming/edm/edmSkill.log
\t (00:00:02) Opening existing design...
\i (00:00:04) fillin yes 
\w (00:00:04)  Design outline not created.
\w (00:00:04) WARNING(SPMHDB-213): DRC set to "out of date". The current product selection supports a different DRC capability than what is saved in the design.
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Size_B_2LAYERS_CNC"
\d (00:00:04) Design opened: //atlas/ProjectLibrary/TechServices/PCB_Layout/Layout_Libraries/Board_Templates/Size_B_2LAYERS_CNC.brd
\i (00:00:04) trapsize 746
\i (00:00:04) trapsize 778
\i (00:00:05) trapsize 746
\i (00:00:05) trapsize 627
\i (00:00:05) trapsize 627
\i (00:00:05) generaledit 
\i (00:00:07) save_as 
\i (00:00:28) fillin "C:/1_EDMWorkspace/AUV/100221658_GPSantennaStrobe/A/Schematic/allegro/prototype_2.brd"
\i (00:00:28) cd "C:/1_EDMWorkspace/AUV/100221658_GPSantennaStrobe/A/Schematic/allegro"
\i (00:00:28) generaledit 
\i (00:00:30) exit 
\t (00:00:31)     Journal end - Fri Jul 22 13:47:36 2022