\t (00:00:02) allegro 17.4 S023 Windows SPB 64-bit Edition
\t (00:00:02)     Journal start - Fri Jul 22 13:46:50 2022
\t (00:00:02)         Host=PERISCOPE User=tanner Pid=4716 CPUs=16
\t (00:00:02) CmdLine= c:\cadence\spb_17.4\tools\bin\allegro.exe \\atlas\ProjectLibrary\TechServices\PCB_Layout\Layout_Libraries\Board_Templates\Size_B_4LAYER_2.brd
\t (00:00:02) 
   (00:00:02) Loading axlcore.cxt 
\t (00:00:02) Loading "C:/SPB_Data/cdssetup/OrCAD_Capture/17.4.0/tclscripts/capAutoLoad/EDMClient/EDM/ClientAdapter/Skill/edm.csj"
\t (00:00:02) Log will be written to C:\Users\tanner\AppData\Roaming/edm/edmSkill.log
\t (00:00:02) Opening existing design...
\i (00:00:04) fillin yes 
\w (00:00:04) WARNING(SPMHDB-213): DRC set to "out of date". The current product selection supports a different DRC capability than what is saved in the design.
\i (00:00:04) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Size_B_4LAYER_2"
\d (00:00:04) Design opened: //atlas/ProjectLibrary/TechServices/PCB_Layout/Layout_Libraries/Board_Templates/Size_B_4LAYER_2.brd
\i (00:00:04) trapsize 746
\i (00:00:05) trapsize 778
\i (00:00:05) trapsize 746
\i (00:00:05) trapsize 627
\i (00:00:05) trapsize 627
\i (00:00:05) generaledit 
\i (00:00:08) xsection 
\i (00:00:11) QtSignal SPBMainWindow CCMQtXSectionDlg closed
\i (00:00:11) QtSignal m_vSplitter m_stackupsTab currentChanged
\i (00:00:11) QtSignal m_vSplitter m_stackupsTab currentChanged
\i (00:00:11) QtSignal CCMQtXSectionDlg AddLayerDlg closed
\i (00:00:12) generaledit 
\i (00:00:12) exit 
\e (00:00:12) Do you want to save the changes you made to Size_B_4LAYER_2.brd?
\i (00:00:14) fillin no 
   (00:00:14) Loading consmgr.cxt 
   (00:00:14) Loading acns_formula.cxt 
\t (00:00:14)     Journal end - Fri Jul 22 13:47:02 2022